mvreg.h revision 294439
1183840Sraj/*- 2239277Sgonzo * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 3183840Sraj * All rights reserved. 4183840Sraj * 5183840Sraj * Developed by Semihalf. 6183840Sraj * 7183840Sraj * Redistribution and use in source and binary forms, with or without 8183840Sraj * modification, are permitted provided that the following conditions 9183840Sraj * are met: 10183840Sraj * 1. Redistributions of source code must retain the above copyright 11183840Sraj * notice, this list of conditions and the following disclaimer. 12183840Sraj * 2. Redistributions in binary form must reproduce the above copyright 13183840Sraj * notice, this list of conditions and the following disclaimer in the 14183840Sraj * documentation and/or other materials provided with the distribution. 15183840Sraj * 3. Neither the name of MARVELL nor the names of contributors 16183840Sraj * may be used to endorse or promote products derived from this software 17183840Sraj * without specific prior written permission. 18183840Sraj * 19183840Sraj * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20183840Sraj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21183840Sraj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22183840Sraj * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23183840Sraj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24183840Sraj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25183840Sraj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26183840Sraj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27183840Sraj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28183840Sraj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29183840Sraj * SUCH DAMAGE. 30183840Sraj * 31183840Sraj * $FreeBSD: head/sys/arm/mv/mvreg.h 294439 2016-01-20 14:45:54Z zbb $ 32183840Sraj */ 33183840Sraj 34183840Sraj#ifndef _MVREG_H_ 35183840Sraj#define _MVREG_H_ 36183840Sraj 37294426Szbb#include <arm/mv/mvwin.h> 38294426Szbb 39183840Sraj#if defined(SOC_MV_DISCOVERY) 40183840Sraj#define IRQ_CAUSE_ERROR 0x0 41183840Sraj#define IRQ_CAUSE 0x4 42183840Sraj#define IRQ_CAUSE_HI 0x8 43183840Sraj#define IRQ_MASK_ERROR 0xC 44183840Sraj#define IRQ_MASK 0x10 45183840Sraj#define IRQ_MASK_HI 0x14 46183840Sraj#define IRQ_CAUSE_SELECT 0x18 47183840Sraj#define FIQ_MASK_ERROR 0x1C 48183840Sraj#define FIQ_MASK 0x20 49183840Sraj#define FIQ_MASK_HI 0x24 50183840Sraj#define FIQ_CAUSE_SELECT 0x28 51239277Sgonzo#define ENDPOINT_IRQ_MASK_ERROR(n) 0x2C 52239277Sgonzo#define ENDPOINT_IRQ_MASK(n) 0x30 53239277Sgonzo#define ENDPOINT_IRQ_MASK_HI(n) 0x34 54183840Sraj#define ENDPOINT_IRQ_CAUSE_SELECT 0x38 55239277Sgonzo#elif defined (SOC_MV_LOKIPLUS) || defined (SOC_MV_FREY) 56183840Sraj#define IRQ_CAUSE 0x0 57183840Sraj#define IRQ_MASK 0x4 58183840Sraj#define FIQ_MASK 0x8 59239277Sgonzo#define ENDPOINT_IRQ_MASK(n) (0xC + (n) * 4) 60239277Sgonzo#define IRQ_CAUSE_HI (-1) /* Fake defines for unified */ 61239277Sgonzo#define IRQ_MASK_HI (-1) /* interrupt controller code */ 62239277Sgonzo#define FIQ_MASK_HI (-1) 63239277Sgonzo#define ENDPOINT_IRQ_MASK_HI(n) (-1) 64239277Sgonzo#define ENDPOINT_IRQ_MASK_ERROR(n) (-1) 65239277Sgonzo#define IRQ_CAUSE_ERROR (-1) 66239277Sgonzo#define IRQ_MASK_ERROR (-1) 67239277Sgonzo#elif defined (SOC_MV_ARMADAXP) 68239277Sgonzo#define IRQ_CAUSE 0x18 69239277Sgonzo#define IRQ_MASK 0x30 70239277Sgonzo#else /* !SOC_MV_DISCOVERY && !SOC_MV_LOKIPLUS */ 71239277Sgonzo#define IRQ_CAUSE 0x0 72239277Sgonzo#define IRQ_MASK 0x4 73239277Sgonzo#define FIQ_MASK 0x8 74239277Sgonzo#define ENDPOINT_IRQ_MASK(n) 0xC 75183840Sraj#define IRQ_CAUSE_HI 0x10 76183840Sraj#define IRQ_MASK_HI 0x14 77183840Sraj#define FIQ_MASK_HI 0x18 78239277Sgonzo#define ENDPOINT_IRQ_MASK_HI(n) 0x1C 79239277Sgonzo#define ENDPOINT_IRQ_MASK_ERROR(n) (-1) 80183840Sraj#define IRQ_CAUSE_ERROR (-1) /* Fake defines for unified */ 81183840Sraj#define IRQ_MASK_ERROR (-1) /* interrupt controller code */ 82183840Sraj#endif 83183840Sraj 84239277Sgonzo#if defined(SOC_MV_FREY) 85239277Sgonzo#define BRIDGE_IRQ_CAUSE 0x118 86239277Sgonzo#define IRQ_TIMER0 0x00000002 87239277Sgonzo#define IRQ_TIMER1 0x00000004 88239277Sgonzo#define IRQ_TIMER_WD 0x00000008 89239277Sgonzo 90239277Sgonzo#define BRIDGE_IRQ_MASK 0x11c 91239277Sgonzo#define IRQ_TIMER0_MASK 0x00000002 92239277Sgonzo#define IRQ_TIMER1_MASK 0x00000004 93239277Sgonzo#define IRQ_TIMER_WD_MASK 0x00000008 94239277Sgonzo#elif defined(SOC_MV_ARMADAXP) 95239277Sgonzo#define BRIDGE_IRQ_CAUSE 0x68 96239277Sgonzo#define IRQ_TIMER0 0x00000001 97239277Sgonzo#define IRQ_TIMER1 0x00000002 98239277Sgonzo#define IRQ_TIMER_WD 0x00000004 99239277Sgonzo#else 100183840Sraj#define BRIDGE_IRQ_CAUSE 0x10 101183840Sraj#define IRQ_CPU_SELF 0x00000001 102183840Sraj#define IRQ_TIMER0 0x00000002 103183840Sraj#define IRQ_TIMER1 0x00000004 104183840Sraj#define IRQ_TIMER_WD 0x00000008 105183840Sraj 106183840Sraj#define BRIDGE_IRQ_MASK 0x14 107183840Sraj#define IRQ_CPU_MASK 0x00000001 108183840Sraj#define IRQ_TIMER0_MASK 0x00000002 109183840Sraj#define IRQ_TIMER1_MASK 0x00000004 110183840Sraj#define IRQ_TIMER_WD_MASK 0x00000008 111239277Sgonzo#endif 112183840Sraj 113239277Sgonzo#if defined(SOC_MV_LOKIPLUS) || defined(SOC_MV_FREY) 114239277Sgonzo#define IRQ_CPU_SELF_CLR IRQ_CPU_SELF 115239277Sgonzo#define IRQ_TIMER0_CLR IRQ_TIMER0 116239277Sgonzo#define IRQ_TIMER1_CLR IRQ_TIMER1 117239277Sgonzo#define IRQ_TIMER_WD_CLR IRQ_TIMER_WD 118239277Sgonzo#else 119239277Sgonzo#define IRQ_CPU_SELF_CLR (~IRQ_CPU_SELF) 120239277Sgonzo#define IRQ_TIMER0_CLR (~IRQ_TIMER0) 121239277Sgonzo#define IRQ_TIMER1_CLR (~IRQ_TIMER1) 122239277Sgonzo#define IRQ_TIMER_WD_CLR (~IRQ_TIMER_WD) 123239277Sgonzo#endif 124239277Sgonzo 125183840Sraj/* 126183840Sraj * System reset 127183840Sraj */ 128294416Szbb#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) 129240488Sgber#define RSTOUTn_MASK 0x60 130294436Szbb#define RSTOUTn_MASK_WD 0x400 131240488Sgber#define SYSTEM_SOFT_RESET 0x64 132240488Sgber#define WD_RSTOUTn_MASK 0x4 133240488Sgber#define WD_GLOBAL_MASK 0x00000100 134240488Sgber#define WD_CPU0_MASK 0x00000001 135240488Sgber#define SOFT_RST_OUT_EN 0x00000001 136240488Sgber#define SYS_SOFT_RST 0x00000001 137240488Sgber#else 138183840Sraj#define RSTOUTn_MASK 0x8 139183840Sraj#define WD_RST_OUT_EN 0x00000002 140183840Sraj#define SOFT_RST_OUT_EN 0x00000004 141183840Sraj#define SYSTEM_SOFT_RESET 0xc 142183840Sraj#define SYS_SOFT_RST 0x00000001 143240488Sgber#endif 144183840Sraj 145183840Sraj/* 146183840Sraj * Power Control 147183840Sraj */ 148256760Srrs#if defined(SOC_MV_KIRKWOOD) 149256760Srrs#define CPU_PM_CTRL 0x18 150256760Srrs#else 151183840Sraj#define CPU_PM_CTRL 0x1C 152256760Srrs#endif 153183840Sraj#define CPU_PM_CTRL_NONE 0 154196532Sraj#define CPU_PM_CTRL_ALL ~0x0 155183840Sraj 156183840Sraj#if defined(SOC_MV_KIRKWOOD) 157183840Sraj#define CPU_PM_CTRL_GE0 (1 << 0) 158183840Sraj#define CPU_PM_CTRL_PEX0_PHY (1 << 1) 159183840Sraj#define CPU_PM_CTRL_PEX0 (1 << 2) 160183840Sraj#define CPU_PM_CTRL_USB0 (1 << 3) 161183840Sraj#define CPU_PM_CTRL_SDIO (1 << 4) 162183840Sraj#define CPU_PM_CTRL_TSU (1 << 5) 163183840Sraj#define CPU_PM_CTRL_DUNIT (1 << 6) 164183840Sraj#define CPU_PM_CTRL_RUNIT (1 << 7) 165183840Sraj#define CPU_PM_CTRL_XOR0 (1 << 8) 166183840Sraj#define CPU_PM_CTRL_AUDIO (1 << 9) 167183840Sraj#define CPU_PM_CTRL_SATA0 (1 << 14) 168183840Sraj#define CPU_PM_CTRL_SATA1 (1 << 15) 169183840Sraj#define CPU_PM_CTRL_XOR1 (1 << 16) 170183840Sraj#define CPU_PM_CTRL_CRYPTO (1 << 17) 171196532Sraj#define CPU_PM_CTRL_GE1 (1 << 19) 172196532Sraj#define CPU_PM_CTRL_TDM (1 << 20) 173196532Sraj#define CPU_PM_CTRL_XOR (CPU_PM_CTRL_XOR0 | CPU_PM_CTRL_XOR1) 174196532Sraj#define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_USB0) 175196532Sraj#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1) 176209131Sraj#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \ 177209131Sraj (1 - (u))) 178209131Sraj#define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE) 179183840Sraj#elif defined(SOC_MV_DISCOVERY) 180183840Sraj#define CPU_PM_CTRL_GE0 (1 << 1) 181183840Sraj#define CPU_PM_CTRL_GE1 (1 << 2) 182183840Sraj#define CPU_PM_CTRL_PEX00 (1 << 5) 183183840Sraj#define CPU_PM_CTRL_PEX01 (1 << 6) 184183840Sraj#define CPU_PM_CTRL_PEX02 (1 << 7) 185183840Sraj#define CPU_PM_CTRL_PEX03 (1 << 8) 186183840Sraj#define CPU_PM_CTRL_PEX10 (1 << 9) 187183840Sraj#define CPU_PM_CTRL_PEX11 (1 << 10) 188183840Sraj#define CPU_PM_CTRL_PEX12 (1 << 11) 189183840Sraj#define CPU_PM_CTRL_PEX13 (1 << 12) 190183840Sraj#define CPU_PM_CTRL_SATA0_PHY (1 << 13) 191183840Sraj#define CPU_PM_CTRL_SATA0 (1 << 14) 192183840Sraj#define CPU_PM_CTRL_SATA1_PHY (1 << 15) 193183840Sraj#define CPU_PM_CTRL_SATA1 (1 << 16) 194183840Sraj#define CPU_PM_CTRL_USB0 (1 << 17) 195183840Sraj#define CPU_PM_CTRL_USB1 (1 << 18) 196183840Sraj#define CPU_PM_CTRL_USB2 (1 << 19) 197183840Sraj#define CPU_PM_CTRL_IDMA (1 << 20) 198183840Sraj#define CPU_PM_CTRL_XOR (1 << 21) 199183840Sraj#define CPU_PM_CTRL_CRYPTO (1 << 22) 200183840Sraj#define CPU_PM_CTRL_DEVICE (1 << 23) 201196532Sraj#define CPU_PM_CTRL_USB(u) (1 << (17 + (u))) 202196532Sraj#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1) 203209131Sraj#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \ 204209131Sraj (1 - (u))) 205196532Sraj#else 206196532Sraj#define CPU_PM_CTRL_CRYPTO (CPU_PM_CTRL_NONE) 207196532Sraj#define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE) 208196532Sraj#define CPU_PM_CTRL_XOR (CPU_PM_CTRL_NONE) 209196532Sraj#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_NONE) 210196532Sraj#define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_NONE) 211209131Sraj#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_NONE) 212183840Sraj#endif 213183840Sraj 214183840Sraj/* 215183840Sraj * Timers 216183840Sraj */ 217239277Sgonzo#define CPU_TIMERS_BASE 0x300 218183840Sraj#define CPU_TIMER_CONTROL 0x0 219183840Sraj#define CPU_TIMER0_EN 0x00000001 220183840Sraj#define CPU_TIMER0_AUTO 0x00000002 221183840Sraj#define CPU_TIMER1_EN 0x00000004 222183840Sraj#define CPU_TIMER1_AUTO 0x00000008 223294436Szbb#define CPU_TIMER2_EN 0x00000010 224294436Szbb#define CPU_TIMER2_AUTO 0x00000020 225294436Szbb#define CPU_TIMER_WD_EN 0x00000100 226294436Szbb#define CPU_TIMER_WD_AUTO 0x00000200 227251371Sgber/* 25MHz mode is Armada XP - specific */ 228251371Sgber#define CPU_TIMER_WD_25MHZ_EN 0x00000400 229251371Sgber#define CPU_TIMER0_25MHZ_EN 0x00000800 230251371Sgber#define CPU_TIMER1_25MHZ_EN 0x00001000 231183840Sraj#define CPU_TIMER0_REL 0x10 232183840Sraj#define CPU_TIMER0 0x14 233183840Sraj 234183840Sraj/* 235194845Sraj * SATA 236194845Sraj */ 237194845Sraj#define SATA_CHAN_NUM 2 238194845Sraj 239194845Sraj#define EDMA_REGISTERS_OFFSET 0x2000 240194845Sraj#define EDMA_REGISTERS_SIZE 0x2000 241194845Sraj#define SATA_EDMA_BASE(ch) (EDMA_REGISTERS_OFFSET + \ 242194845Sraj ((ch) * EDMA_REGISTERS_SIZE)) 243194845Sraj 244194845Sraj/* SATAHC registers */ 245194845Sraj#define SATA_CR 0x000 /* Configuration Reg. */ 246194845Sraj#define SATA_CR_NODMABS (1 << 8) 247194845Sraj#define SATA_CR_NOEDMABS (1 << 9) 248194845Sraj#define SATA_CR_NOPRDPBS (1 << 10) 249194845Sraj#define SATA_CR_COALDIS(ch) (1 << (24 + ch)) 250194845Sraj 251239277Sgonzo/* Interrupt Coalescing Threshold Reg. */ 252239277Sgonzo#define SATA_ICTR 0x00C 253239277Sgonzo#define SATA_ICTR_MAX ((1 << 8) - 1) 254239277Sgonzo 255239277Sgonzo/* Interrupt Time Threshold Reg. */ 256239277Sgonzo#define SATA_ITTR 0x010 257239277Sgonzo#define SATA_ITTR_MAX ((1 << 24) - 1) 258239277Sgonzo 259239277Sgonzo#define SATA_ICR 0x014 /* Interrupt Cause Reg. */ 260194845Sraj#define SATA_ICR_DMADONE(ch) (1 << (ch)) 261194845Sraj#define SATA_ICR_COAL (1 << 4) 262194845Sraj#define SATA_ICR_DEV(ch) (1 << (8 + ch)) 263194845Sraj 264194845Sraj#define SATA_MICR 0x020 /* Main Interrupt Cause Reg. */ 265194845Sraj#define SATA_MICR_ERR(ch) (1 << (2 * ch)) 266194845Sraj#define SATA_MICR_DONE(ch) (1 << ((2 * ch) + 1)) 267194845Sraj#define SATA_MICR_DMADONE(ch) (1 << (4 + ch)) 268194845Sraj#define SATA_MICR_COAL (1 << 8) 269194845Sraj 270194845Sraj#define SATA_MIMR 0x024 /* Main Interrupt Mask Reg. */ 271194845Sraj 272194845Sraj/* Shadow registers */ 273194845Sraj#define SATA_SHADOWR_BASE(ch) (SATA_EDMA_BASE(ch) + 0x100) 274194845Sraj#define SATA_SHADOWR_CONTROL(ch) (SATA_EDMA_BASE(ch) + 0x120) 275194845Sraj 276194845Sraj/* SATA registers */ 277194845Sraj#define SATA_SATA_SSTATUS(ch) (SATA_EDMA_BASE(ch) + 0x300) 278194845Sraj#define SATA_SATA_SERROR(ch) (SATA_EDMA_BASE(ch) + 0x304) 279194845Sraj#define SATA_SATA_SCONTROL(ch) (SATA_EDMA_BASE(ch) + 0x308) 280194845Sraj#define SATA_SATA_FISICR(ch) (SATA_EDMA_BASE(ch) + 0x364) 281194845Sraj 282194845Sraj/* EDMA registers */ 283194845Sraj#define SATA_EDMA_CFG(ch) (SATA_EDMA_BASE(ch) + 0x000) 284194845Sraj#define SATA_EDMA_CFG_QL128 (1 << 19) 285194845Sraj#define SATA_EDMA_CFG_HQCACHE (1 << 22) 286194845Sraj 287194845Sraj#define SATA_EDMA_IECR(ch) (SATA_EDMA_BASE(ch) + 0x008) 288194845Sraj 289194845Sraj#define SATA_EDMA_IEMR(ch) (SATA_EDMA_BASE(ch) + 0x00C) 290194845Sraj#define SATA_EDMA_REQBAHR(ch) (SATA_EDMA_BASE(ch) + 0x010) 291194845Sraj#define SATA_EDMA_REQIPR(ch) (SATA_EDMA_BASE(ch) + 0x014) 292194845Sraj#define SATA_EDMA_REQOPR(ch) (SATA_EDMA_BASE(ch) + 0x018) 293194845Sraj#define SATA_EDMA_RESBAHR(ch) (SATA_EDMA_BASE(ch) + 0x01C) 294194845Sraj#define SATA_EDMA_RESIPR(ch) (SATA_EDMA_BASE(ch) + 0x020) 295194845Sraj#define SATA_EDMA_RESOPR(ch) (SATA_EDMA_BASE(ch) + 0x024) 296194845Sraj 297194845Sraj#define SATA_EDMA_CMD(ch) (SATA_EDMA_BASE(ch) + 0x028) 298194845Sraj#define SATA_EDMA_CMD_ENABLE (1 << 0) 299194845Sraj#define SATA_EDMA_CMD_DISABLE (1 << 1) 300194845Sraj#define SATA_EDMA_CMD_RESET (1 << 2) 301194845Sraj 302194845Sraj#define SATA_EDMA_STATUS(ch) (SATA_EDMA_BASE(ch) + 0x030) 303194845Sraj#define SATA_EDMA_STATUS_IDLE (1 << 7) 304194845Sraj 305194845Sraj/* Offset to extract input slot from REQIPR register */ 306194845Sraj#define SATA_EDMA_REQIS_OFS 5 307194845Sraj 308194845Sraj/* Offset to extract input slot from RESOPR register */ 309194845Sraj#define SATA_EDMA_RESOS_OFS 3 310194845Sraj 311194845Sraj/* 312183840Sraj * GPIO 313183840Sraj */ 314183840Sraj#define GPIO_DATA_OUT 0x00 315183840Sraj#define GPIO_DATA_OUT_EN_CTRL 0x04 316183840Sraj#define GPIO_BLINK_EN 0x08 317183840Sraj#define GPIO_DATA_IN_POLAR 0x0c 318183840Sraj#define GPIO_DATA_IN 0x10 319183840Sraj#define GPIO_INT_CAUSE 0x14 320183840Sraj#define GPIO_INT_EDGE_MASK 0x18 321183840Sraj#define GPIO_INT_LEV_MASK 0x1c 322183840Sraj 323183840Sraj#define GPIO_HI_DATA_OUT 0x40 324183840Sraj#define GPIO_HI_DATA_OUT_EN_CTRL 0x44 325183840Sraj#define GPIO_HI_BLINK_EN 0x48 326183840Sraj#define GPIO_HI_DATA_IN_POLAR 0x4c 327183840Sraj#define GPIO_HI_DATA_IN 0x50 328183840Sraj#define GPIO_HI_INT_CAUSE 0x54 329183840Sraj#define GPIO_HI_INT_EDGE_MASK 0x58 330183840Sraj#define GPIO_HI_INT_LEV_MASK 0x5c 331183840Sraj 332183840Sraj#define GPIO(n) (1 << (n)) 333183840Sraj#define MV_GPIO_MAX_NPINS 64 334183840Sraj 335209131Sraj#define MV_GPIO_IN_NONE 0x0 336209131Sraj#define MV_GPIO_IN_POL_LOW (1 << 16) 337209131Sraj#define MV_GPIO_IN_IRQ_EDGE (2 << 16) 338209131Sraj#define MV_GPIO_IN_IRQ_LEVEL (4 << 16) 339209131Sraj#define MV_GPIO_OUT_NONE 0x0 340209131Sraj#define MV_GPIO_OUT_BLINK 0x1 341209131Sraj#define MV_GPIO_OUT_OPEN_DRAIN 0x2 342209131Sraj#define MV_GPIO_OUT_OPEN_SRC 0x4 343183840Sraj 344183840Sraj#define IS_GPIO_IRQ(irq) ((irq) >= NIRQ && (irq) < NIRQ + MV_GPIO_MAX_NPINS) 345183840Sraj#define GPIO2IRQ(gpio) ((gpio) + NIRQ) 346183840Sraj#define IRQ2GPIO(irq) ((irq) - NIRQ) 347183840Sraj 348239277Sgonzo#if defined(SOC_MV_ORION) || defined(SOC_MV_LOKIPLUS) 349183840Sraj#define SAMPLE_AT_RESET 0x10 350186899Sraj#elif defined(SOC_MV_KIRKWOOD) 351183840Sraj#define SAMPLE_AT_RESET 0x30 352243580Smarcel#elif defined(SOC_MV_FREY) 353243580Smarcel#define SAMPLE_AT_RESET 0x100 354294416Szbb#elif defined(SOC_MV_ARMADA38X) 355294416Szbb#define SAMPLE_AT_RESET 0x400 356243580Smarcel#endif 357243580Smarcel#if defined(SOC_MV_DISCOVERY) 358186899Sraj#define SAMPLE_AT_RESET_LO 0x30 359186899Sraj#define SAMPLE_AT_RESET_HI 0x34 360239277Sgonzo#elif defined(SOC_MV_DOVE) 361239277Sgonzo#define SAMPLE_AT_RESET_LO 0x14 362239277Sgonzo#define SAMPLE_AT_RESET_HI 0x18 363240488Sgber#elif defined(SOC_MV_ARMADAXP) 364240488Sgber#define SAMPLE_AT_RESET_LO 0x30 365240488Sgber#define SAMPLE_AT_RESET_HI 0x34 366183840Sraj#endif 367183840Sraj 368183840Sraj/* 369183840Sraj * Clocks 370183840Sraj */ 371186899Sraj#if defined(SOC_MV_ORION) 372186899Sraj#define TCLK_MASK 0x00000300 373186899Sraj#define TCLK_SHIFT 0x08 374186899Sraj#elif defined(SOC_MV_DISCOVERY) 375186899Sraj#define TCLK_MASK 0x00000180 376186899Sraj#define TCLK_SHIFT 0x07 377239277Sgonzo#elif defined(SOC_MV_LOKIPLUS) 378239277Sgonzo#define TCLK_MASK 0x0000F000 379239277Sgonzo#define TCLK_SHIFT 0x0C 380294416Szbb#elif defined(SOC_MV_ARMADA38X) 381294416Szbb#define TCLK_MASK 0x00008000 382294416Szbb#define TCLK_SHIFT 15 383183840Sraj#endif 384183840Sraj 385183840Sraj#define TCLK_100MHZ 100000000 386183840Sraj#define TCLK_125MHZ 125000000 387183840Sraj#define TCLK_133MHZ 133333333 388183840Sraj#define TCLK_150MHZ 150000000 389183840Sraj#define TCLK_166MHZ 166666667 390183840Sraj#define TCLK_200MHZ 200000000 391239277Sgonzo#define TCLK_250MHZ 250000000 392239277Sgonzo#define TCLK_300MHZ 300000000 393239277Sgonzo#define TCLK_667MHZ 667000000 394183840Sraj 395183840Sraj/* 396239277Sgonzo * CPU Cache Configuration 397239277Sgonzo */ 398239277Sgonzo 399239277Sgonzo#define CPU_CONFIG 0x00000000 400239277Sgonzo#define CPU_CONFIG_IC_PREF 0x00010000 401239277Sgonzo#define CPU_CONFIG_DC_PREF 0x00020000 402239277Sgonzo#define CPU_CONTROL 0x00000004 403239277Sgonzo#define CPU_CONTROL_L2_SIZE 0x00200000 /* Only on Discovery */ 404239277Sgonzo#define CPU_CONTROL_L2_MODE 0x00020000 /* Only on Discovery */ 405239277Sgonzo#define CPU_L2_CONFIG 0x00000028 /* Only on Kirkwood */ 406239277Sgonzo#define CPU_L2_CONFIG_MODE 0x00000010 /* Only on Kirkwood */ 407239277Sgonzo 408239277Sgonzo/* 409239277Sgonzo * PCI Express port control (CPU Control registers) 410239277Sgonzo */ 411239277Sgonzo#define CPU_CONTROL_PCIE_DISABLE(n) (1 << (3 * (n))) 412239277Sgonzo 413239277Sgonzo/* 414239277Sgonzo * Vendor ID 415239277Sgonzo */ 416239277Sgonzo#define PCI_VENDORID_MRVL 0x11AB 417239277Sgonzo#define PCI_VENDORID_MRVL2 0x1B4B 418239277Sgonzo 419239277Sgonzo/* 420183840Sraj * Chip ID 421183840Sraj */ 422191140Sraj#define MV_DEV_88F5181 0x5181 423191140Sraj#define MV_DEV_88F5182 0x5182 424191140Sraj#define MV_DEV_88F5281 0x5281 425191140Sraj#define MV_DEV_88F6281 0x6281 426239370Shrs#define MV_DEV_88F6282 0x6282 427239277Sgonzo#define MV_DEV_88F6781 0x6781 428294416Szbb#define MV_DEV_88F6828 0x6828 429294416Szbb#define MV_DEV_88F6820 0x6820 430294416Szbb#define MV_DEV_88F6810 0x6810 431191140Sraj#define MV_DEV_MV78100_Z0 0x6381 432191140Sraj#define MV_DEV_MV78100 0x7810 433239277Sgonzo#define MV_DEV_MV78130 0x7813 434239277Sgonzo#define MV_DEV_MV78160 0x7816 435239277Sgonzo#define MV_DEV_MV78230 0x7823 436239277Sgonzo#define MV_DEV_MV78260 0x7826 437239277Sgonzo#define MV_DEV_MV78460 0x7846 438239277Sgonzo#define MV_DEV_88RC8180 0x8180 439239277Sgonzo#define MV_DEV_88RC9480 0x9480 440239277Sgonzo#define MV_DEV_88RC9580 0x9580 441183840Sraj 442239277Sgonzo#define MV_DEV_FAMILY_MASK 0xff00 443239277Sgonzo#define MV_DEV_DISCOVERY 0x7800 444294430Szbb#define MV_DEV_ARMADA38X 0x6800 445239277Sgonzo 446239277Sgonzo/* 447239277Sgonzo * Doorbell register control 448239277Sgonzo */ 449239277Sgonzo#define MV_DRBL_PCIE_TO_CPU 0 450239277Sgonzo#define MV_DRBL_CPU_TO_PCIE 1 451239277Sgonzo 452239277Sgonzo#if defined(SOC_MV_FREY) 453239277Sgonzo#define MV_DRBL_CAUSE(d,u) (0x60 + 0x20 * (d) + 0x8 * (u)) 454239277Sgonzo#define MV_DRBL_MASK(d,u) (0x60 + 0x20 * (d) + 0x8 * (u) + 0x4) 455239277Sgonzo#define MV_DRBL_MSG(m,d,u) (0x8 * (u) + 0x20 * (d) + 0x4 * (m)) 456239277Sgonzo#else 457239277Sgonzo#define MV_DRBL_CAUSE(d,u) (0x10 * (u) + 0x8 * (d)) 458239277Sgonzo#define MV_DRBL_MASK(d,u) (0x10 * (u) + 0x8 * (d) + 0x4) 459239277Sgonzo#define MV_DRBL_MSG(m,d,u) (0x10 * (u) + 0x8 * (d) + 0x4 * (m) + 0x30) 460239277Sgonzo#endif 461294426Szbb 462294426Szbb/* 463294426Szbb * SCU 464294426Szbb */ 465294426Szbb#if defined(SOC_MV_ARMADA38X) 466294426Szbb#define MV_SCU_BASE (MV_BASE + 0xc000) 467294426Szbb#define MV_SCU_REGS_LEN 0x100 468294439Szbb#define MV_SCU_REG_CTRL 0x00 469294439Szbb#define MV_SCU_REG_CONFIG 0x04 470294426Szbb#define MV_SCU_ENABLE 1 471294426Szbb#endif 472294426Szbb 473294439Szbb/* 474294439Szbb * PMSU 475294439Szbb */ 476294439Szbb#if defined(SOC_MV_ARMADA38X) 477294439Szbb#define MV_PMSU_BASE (MV_BASE + 0x22000) 478294439Szbb#define MV_PMSU_REGS_LEN 0x1000 479294439Szbb#define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) (((cpu) * 0x100) + 0x124) 480294439Szbb#endif 481294439Szbb 482294439Szbb/* 483294439Szbb * CPU RESET 484294439Szbb */ 485294439Szbb#if defined(SOC_MV_ARMADA38X) 486294439Szbb#define MV_CPU_RESET_BASE (MV_BASE + 0x20800) 487294439Szbb#define MV_CPU_RESET_REGS_LEN 0x8 488294439Szbb#define CPU_RESET_OFFSET(cpu) ((cpu) * 0x8) 489294439Szbb#define CPU_RESET_ASSERT 0x1 490294439Szbb#endif 491294439Szbb 492183840Sraj#endif /* _MVREG_H_ */ 493