mvreg.h revision 294426
1183840Sraj/*- 2239277Sgonzo * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 3183840Sraj * All rights reserved. 4183840Sraj * 5183840Sraj * Developed by Semihalf. 6183840Sraj * 7183840Sraj * Redistribution and use in source and binary forms, with or without 8183840Sraj * modification, are permitted provided that the following conditions 9183840Sraj * are met: 10183840Sraj * 1. Redistributions of source code must retain the above copyright 11183840Sraj * notice, this list of conditions and the following disclaimer. 12183840Sraj * 2. Redistributions in binary form must reproduce the above copyright 13183840Sraj * notice, this list of conditions and the following disclaimer in the 14183840Sraj * documentation and/or other materials provided with the distribution. 15183840Sraj * 3. Neither the name of MARVELL nor the names of contributors 16183840Sraj * may be used to endorse or promote products derived from this software 17183840Sraj * without specific prior written permission. 18183840Sraj * 19183840Sraj * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20183840Sraj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21183840Sraj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22183840Sraj * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23183840Sraj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24183840Sraj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25183840Sraj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26183840Sraj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27183840Sraj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28183840Sraj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29183840Sraj * SUCH DAMAGE. 30183840Sraj * 31183840Sraj * $FreeBSD: head/sys/arm/mv/mvreg.h 294426 2016-01-20 13:55:51Z zbb $ 32183840Sraj */ 33183840Sraj 34183840Sraj#ifndef _MVREG_H_ 35183840Sraj#define _MVREG_H_ 36183840Sraj 37294426Szbb#include <arm/mv/mvwin.h> 38294426Szbb 39183840Sraj#if defined(SOC_MV_DISCOVERY) 40183840Sraj#define IRQ_CAUSE_ERROR 0x0 41183840Sraj#define IRQ_CAUSE 0x4 42183840Sraj#define IRQ_CAUSE_HI 0x8 43183840Sraj#define IRQ_MASK_ERROR 0xC 44183840Sraj#define IRQ_MASK 0x10 45183840Sraj#define IRQ_MASK_HI 0x14 46183840Sraj#define IRQ_CAUSE_SELECT 0x18 47183840Sraj#define FIQ_MASK_ERROR 0x1C 48183840Sraj#define FIQ_MASK 0x20 49183840Sraj#define FIQ_MASK_HI 0x24 50183840Sraj#define FIQ_CAUSE_SELECT 0x28 51239277Sgonzo#define ENDPOINT_IRQ_MASK_ERROR(n) 0x2C 52239277Sgonzo#define ENDPOINT_IRQ_MASK(n) 0x30 53239277Sgonzo#define ENDPOINT_IRQ_MASK_HI(n) 0x34 54183840Sraj#define ENDPOINT_IRQ_CAUSE_SELECT 0x38 55239277Sgonzo#elif defined (SOC_MV_LOKIPLUS) || defined (SOC_MV_FREY) 56183840Sraj#define IRQ_CAUSE 0x0 57183840Sraj#define IRQ_MASK 0x4 58183840Sraj#define FIQ_MASK 0x8 59239277Sgonzo#define ENDPOINT_IRQ_MASK(n) (0xC + (n) * 4) 60239277Sgonzo#define IRQ_CAUSE_HI (-1) /* Fake defines for unified */ 61239277Sgonzo#define IRQ_MASK_HI (-1) /* interrupt controller code */ 62239277Sgonzo#define FIQ_MASK_HI (-1) 63239277Sgonzo#define ENDPOINT_IRQ_MASK_HI(n) (-1) 64239277Sgonzo#define ENDPOINT_IRQ_MASK_ERROR(n) (-1) 65239277Sgonzo#define IRQ_CAUSE_ERROR (-1) 66239277Sgonzo#define IRQ_MASK_ERROR (-1) 67239277Sgonzo#elif defined (SOC_MV_ARMADAXP) 68239277Sgonzo#define IRQ_CAUSE 0x18 69239277Sgonzo#define IRQ_MASK 0x30 70239277Sgonzo#else /* !SOC_MV_DISCOVERY && !SOC_MV_LOKIPLUS */ 71239277Sgonzo#define IRQ_CAUSE 0x0 72239277Sgonzo#define IRQ_MASK 0x4 73239277Sgonzo#define FIQ_MASK 0x8 74239277Sgonzo#define ENDPOINT_IRQ_MASK(n) 0xC 75183840Sraj#define IRQ_CAUSE_HI 0x10 76183840Sraj#define IRQ_MASK_HI 0x14 77183840Sraj#define FIQ_MASK_HI 0x18 78239277Sgonzo#define ENDPOINT_IRQ_MASK_HI(n) 0x1C 79239277Sgonzo#define ENDPOINT_IRQ_MASK_ERROR(n) (-1) 80183840Sraj#define IRQ_CAUSE_ERROR (-1) /* Fake defines for unified */ 81183840Sraj#define IRQ_MASK_ERROR (-1) /* interrupt controller code */ 82183840Sraj#endif 83183840Sraj 84239277Sgonzo#if defined(SOC_MV_FREY) 85239277Sgonzo#define BRIDGE_IRQ_CAUSE 0x118 86239277Sgonzo#define IRQ_TIMER0 0x00000002 87239277Sgonzo#define IRQ_TIMER1 0x00000004 88239277Sgonzo#define IRQ_TIMER_WD 0x00000008 89239277Sgonzo 90239277Sgonzo#define BRIDGE_IRQ_MASK 0x11c 91239277Sgonzo#define IRQ_TIMER0_MASK 0x00000002 92239277Sgonzo#define IRQ_TIMER1_MASK 0x00000004 93239277Sgonzo#define IRQ_TIMER_WD_MASK 0x00000008 94239277Sgonzo#elif defined(SOC_MV_ARMADAXP) 95239277Sgonzo#define BRIDGE_IRQ_CAUSE 0x68 96239277Sgonzo#define IRQ_TIMER0 0x00000001 97239277Sgonzo#define IRQ_TIMER1 0x00000002 98239277Sgonzo#define IRQ_TIMER_WD 0x00000004 99239277Sgonzo#else 100183840Sraj#define BRIDGE_IRQ_CAUSE 0x10 101183840Sraj#define IRQ_CPU_SELF 0x00000001 102183840Sraj#define IRQ_TIMER0 0x00000002 103183840Sraj#define IRQ_TIMER1 0x00000004 104183840Sraj#define IRQ_TIMER_WD 0x00000008 105183840Sraj 106183840Sraj#define BRIDGE_IRQ_MASK 0x14 107183840Sraj#define IRQ_CPU_MASK 0x00000001 108183840Sraj#define IRQ_TIMER0_MASK 0x00000002 109183840Sraj#define IRQ_TIMER1_MASK 0x00000004 110183840Sraj#define IRQ_TIMER_WD_MASK 0x00000008 111239277Sgonzo#endif 112183840Sraj 113239277Sgonzo#if defined(SOC_MV_LOKIPLUS) || defined(SOC_MV_FREY) 114239277Sgonzo#define IRQ_CPU_SELF_CLR IRQ_CPU_SELF 115239277Sgonzo#define IRQ_TIMER0_CLR IRQ_TIMER0 116239277Sgonzo#define IRQ_TIMER1_CLR IRQ_TIMER1 117239277Sgonzo#define IRQ_TIMER_WD_CLR IRQ_TIMER_WD 118239277Sgonzo#else 119239277Sgonzo#define IRQ_CPU_SELF_CLR (~IRQ_CPU_SELF) 120239277Sgonzo#define IRQ_TIMER0_CLR (~IRQ_TIMER0) 121239277Sgonzo#define IRQ_TIMER1_CLR (~IRQ_TIMER1) 122239277Sgonzo#define IRQ_TIMER_WD_CLR (~IRQ_TIMER_WD) 123239277Sgonzo#endif 124239277Sgonzo 125183840Sraj/* 126183840Sraj * System reset 127183840Sraj */ 128294416Szbb#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) 129240488Sgber#define RSTOUTn_MASK 0x60 130240488Sgber#define SYSTEM_SOFT_RESET 0x64 131240488Sgber#define WD_RSTOUTn_MASK 0x4 132240488Sgber#define WD_GLOBAL_MASK 0x00000100 133240488Sgber#define WD_CPU0_MASK 0x00000001 134240488Sgber#define SOFT_RST_OUT_EN 0x00000001 135240488Sgber#define SYS_SOFT_RST 0x00000001 136240488Sgber#else 137183840Sraj#define RSTOUTn_MASK 0x8 138183840Sraj#define WD_RST_OUT_EN 0x00000002 139183840Sraj#define SOFT_RST_OUT_EN 0x00000004 140183840Sraj#define SYSTEM_SOFT_RESET 0xc 141183840Sraj#define SYS_SOFT_RST 0x00000001 142240488Sgber#endif 143183840Sraj 144183840Sraj/* 145183840Sraj * Power Control 146183840Sraj */ 147256760Srrs#if defined(SOC_MV_KIRKWOOD) 148256760Srrs#define CPU_PM_CTRL 0x18 149256760Srrs#else 150183840Sraj#define CPU_PM_CTRL 0x1C 151256760Srrs#endif 152183840Sraj#define CPU_PM_CTRL_NONE 0 153196532Sraj#define CPU_PM_CTRL_ALL ~0x0 154183840Sraj 155183840Sraj#if defined(SOC_MV_KIRKWOOD) 156183840Sraj#define CPU_PM_CTRL_GE0 (1 << 0) 157183840Sraj#define CPU_PM_CTRL_PEX0_PHY (1 << 1) 158183840Sraj#define CPU_PM_CTRL_PEX0 (1 << 2) 159183840Sraj#define CPU_PM_CTRL_USB0 (1 << 3) 160183840Sraj#define CPU_PM_CTRL_SDIO (1 << 4) 161183840Sraj#define CPU_PM_CTRL_TSU (1 << 5) 162183840Sraj#define CPU_PM_CTRL_DUNIT (1 << 6) 163183840Sraj#define CPU_PM_CTRL_RUNIT (1 << 7) 164183840Sraj#define CPU_PM_CTRL_XOR0 (1 << 8) 165183840Sraj#define CPU_PM_CTRL_AUDIO (1 << 9) 166183840Sraj#define CPU_PM_CTRL_SATA0 (1 << 14) 167183840Sraj#define CPU_PM_CTRL_SATA1 (1 << 15) 168183840Sraj#define CPU_PM_CTRL_XOR1 (1 << 16) 169183840Sraj#define CPU_PM_CTRL_CRYPTO (1 << 17) 170196532Sraj#define CPU_PM_CTRL_GE1 (1 << 19) 171196532Sraj#define CPU_PM_CTRL_TDM (1 << 20) 172196532Sraj#define CPU_PM_CTRL_XOR (CPU_PM_CTRL_XOR0 | CPU_PM_CTRL_XOR1) 173196532Sraj#define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_USB0) 174196532Sraj#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1) 175209131Sraj#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \ 176209131Sraj (1 - (u))) 177209131Sraj#define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE) 178183840Sraj#elif defined(SOC_MV_DISCOVERY) 179183840Sraj#define CPU_PM_CTRL_GE0 (1 << 1) 180183840Sraj#define CPU_PM_CTRL_GE1 (1 << 2) 181183840Sraj#define CPU_PM_CTRL_PEX00 (1 << 5) 182183840Sraj#define CPU_PM_CTRL_PEX01 (1 << 6) 183183840Sraj#define CPU_PM_CTRL_PEX02 (1 << 7) 184183840Sraj#define CPU_PM_CTRL_PEX03 (1 << 8) 185183840Sraj#define CPU_PM_CTRL_PEX10 (1 << 9) 186183840Sraj#define CPU_PM_CTRL_PEX11 (1 << 10) 187183840Sraj#define CPU_PM_CTRL_PEX12 (1 << 11) 188183840Sraj#define CPU_PM_CTRL_PEX13 (1 << 12) 189183840Sraj#define CPU_PM_CTRL_SATA0_PHY (1 << 13) 190183840Sraj#define CPU_PM_CTRL_SATA0 (1 << 14) 191183840Sraj#define CPU_PM_CTRL_SATA1_PHY (1 << 15) 192183840Sraj#define CPU_PM_CTRL_SATA1 (1 << 16) 193183840Sraj#define CPU_PM_CTRL_USB0 (1 << 17) 194183840Sraj#define CPU_PM_CTRL_USB1 (1 << 18) 195183840Sraj#define CPU_PM_CTRL_USB2 (1 << 19) 196183840Sraj#define CPU_PM_CTRL_IDMA (1 << 20) 197183840Sraj#define CPU_PM_CTRL_XOR (1 << 21) 198183840Sraj#define CPU_PM_CTRL_CRYPTO (1 << 22) 199183840Sraj#define CPU_PM_CTRL_DEVICE (1 << 23) 200196532Sraj#define CPU_PM_CTRL_USB(u) (1 << (17 + (u))) 201196532Sraj#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1) 202209131Sraj#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \ 203209131Sraj (1 - (u))) 204196532Sraj#else 205196532Sraj#define CPU_PM_CTRL_CRYPTO (CPU_PM_CTRL_NONE) 206196532Sraj#define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE) 207196532Sraj#define CPU_PM_CTRL_XOR (CPU_PM_CTRL_NONE) 208196532Sraj#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_NONE) 209196532Sraj#define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_NONE) 210209131Sraj#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_NONE) 211183840Sraj#endif 212183840Sraj 213183840Sraj/* 214183840Sraj * Timers 215183840Sraj */ 216239277Sgonzo#define CPU_TIMERS_BASE 0x300 217183840Sraj#define CPU_TIMER_CONTROL 0x0 218183840Sraj#define CPU_TIMER0_EN 0x00000001 219183840Sraj#define CPU_TIMER0_AUTO 0x00000002 220183840Sraj#define CPU_TIMER1_EN 0x00000004 221183840Sraj#define CPU_TIMER1_AUTO 0x00000008 222183840Sraj#define CPU_TIMER_WD_EN 0x00000010 223183840Sraj#define CPU_TIMER_WD_AUTO 0x00000020 224251371Sgber/* 25MHz mode is Armada XP - specific */ 225251371Sgber#define CPU_TIMER_WD_25MHZ_EN 0x00000400 226251371Sgber#define CPU_TIMER0_25MHZ_EN 0x00000800 227251371Sgber#define CPU_TIMER1_25MHZ_EN 0x00001000 228183840Sraj#define CPU_TIMER0_REL 0x10 229183840Sraj#define CPU_TIMER0 0x14 230183840Sraj 231183840Sraj/* 232194845Sraj * SATA 233194845Sraj */ 234194845Sraj#define SATA_CHAN_NUM 2 235194845Sraj 236194845Sraj#define EDMA_REGISTERS_OFFSET 0x2000 237194845Sraj#define EDMA_REGISTERS_SIZE 0x2000 238194845Sraj#define SATA_EDMA_BASE(ch) (EDMA_REGISTERS_OFFSET + \ 239194845Sraj ((ch) * EDMA_REGISTERS_SIZE)) 240194845Sraj 241194845Sraj/* SATAHC registers */ 242194845Sraj#define SATA_CR 0x000 /* Configuration Reg. */ 243194845Sraj#define SATA_CR_NODMABS (1 << 8) 244194845Sraj#define SATA_CR_NOEDMABS (1 << 9) 245194845Sraj#define SATA_CR_NOPRDPBS (1 << 10) 246194845Sraj#define SATA_CR_COALDIS(ch) (1 << (24 + ch)) 247194845Sraj 248239277Sgonzo/* Interrupt Coalescing Threshold Reg. */ 249239277Sgonzo#define SATA_ICTR 0x00C 250239277Sgonzo#define SATA_ICTR_MAX ((1 << 8) - 1) 251239277Sgonzo 252239277Sgonzo/* Interrupt Time Threshold Reg. */ 253239277Sgonzo#define SATA_ITTR 0x010 254239277Sgonzo#define SATA_ITTR_MAX ((1 << 24) - 1) 255239277Sgonzo 256239277Sgonzo#define SATA_ICR 0x014 /* Interrupt Cause Reg. */ 257194845Sraj#define SATA_ICR_DMADONE(ch) (1 << (ch)) 258194845Sraj#define SATA_ICR_COAL (1 << 4) 259194845Sraj#define SATA_ICR_DEV(ch) (1 << (8 + ch)) 260194845Sraj 261194845Sraj#define SATA_MICR 0x020 /* Main Interrupt Cause Reg. */ 262194845Sraj#define SATA_MICR_ERR(ch) (1 << (2 * ch)) 263194845Sraj#define SATA_MICR_DONE(ch) (1 << ((2 * ch) + 1)) 264194845Sraj#define SATA_MICR_DMADONE(ch) (1 << (4 + ch)) 265194845Sraj#define SATA_MICR_COAL (1 << 8) 266194845Sraj 267194845Sraj#define SATA_MIMR 0x024 /* Main Interrupt Mask Reg. */ 268194845Sraj 269194845Sraj/* Shadow registers */ 270194845Sraj#define SATA_SHADOWR_BASE(ch) (SATA_EDMA_BASE(ch) + 0x100) 271194845Sraj#define SATA_SHADOWR_CONTROL(ch) (SATA_EDMA_BASE(ch) + 0x120) 272194845Sraj 273194845Sraj/* SATA registers */ 274194845Sraj#define SATA_SATA_SSTATUS(ch) (SATA_EDMA_BASE(ch) + 0x300) 275194845Sraj#define SATA_SATA_SERROR(ch) (SATA_EDMA_BASE(ch) + 0x304) 276194845Sraj#define SATA_SATA_SCONTROL(ch) (SATA_EDMA_BASE(ch) + 0x308) 277194845Sraj#define SATA_SATA_FISICR(ch) (SATA_EDMA_BASE(ch) + 0x364) 278194845Sraj 279194845Sraj/* EDMA registers */ 280194845Sraj#define SATA_EDMA_CFG(ch) (SATA_EDMA_BASE(ch) + 0x000) 281194845Sraj#define SATA_EDMA_CFG_QL128 (1 << 19) 282194845Sraj#define SATA_EDMA_CFG_HQCACHE (1 << 22) 283194845Sraj 284194845Sraj#define SATA_EDMA_IECR(ch) (SATA_EDMA_BASE(ch) + 0x008) 285194845Sraj 286194845Sraj#define SATA_EDMA_IEMR(ch) (SATA_EDMA_BASE(ch) + 0x00C) 287194845Sraj#define SATA_EDMA_REQBAHR(ch) (SATA_EDMA_BASE(ch) + 0x010) 288194845Sraj#define SATA_EDMA_REQIPR(ch) (SATA_EDMA_BASE(ch) + 0x014) 289194845Sraj#define SATA_EDMA_REQOPR(ch) (SATA_EDMA_BASE(ch) + 0x018) 290194845Sraj#define SATA_EDMA_RESBAHR(ch) (SATA_EDMA_BASE(ch) + 0x01C) 291194845Sraj#define SATA_EDMA_RESIPR(ch) (SATA_EDMA_BASE(ch) + 0x020) 292194845Sraj#define SATA_EDMA_RESOPR(ch) (SATA_EDMA_BASE(ch) + 0x024) 293194845Sraj 294194845Sraj#define SATA_EDMA_CMD(ch) (SATA_EDMA_BASE(ch) + 0x028) 295194845Sraj#define SATA_EDMA_CMD_ENABLE (1 << 0) 296194845Sraj#define SATA_EDMA_CMD_DISABLE (1 << 1) 297194845Sraj#define SATA_EDMA_CMD_RESET (1 << 2) 298194845Sraj 299194845Sraj#define SATA_EDMA_STATUS(ch) (SATA_EDMA_BASE(ch) + 0x030) 300194845Sraj#define SATA_EDMA_STATUS_IDLE (1 << 7) 301194845Sraj 302194845Sraj/* Offset to extract input slot from REQIPR register */ 303194845Sraj#define SATA_EDMA_REQIS_OFS 5 304194845Sraj 305194845Sraj/* Offset to extract input slot from RESOPR register */ 306194845Sraj#define SATA_EDMA_RESOS_OFS 3 307194845Sraj 308194845Sraj/* 309183840Sraj * GPIO 310183840Sraj */ 311183840Sraj#define GPIO_DATA_OUT 0x00 312183840Sraj#define GPIO_DATA_OUT_EN_CTRL 0x04 313183840Sraj#define GPIO_BLINK_EN 0x08 314183840Sraj#define GPIO_DATA_IN_POLAR 0x0c 315183840Sraj#define GPIO_DATA_IN 0x10 316183840Sraj#define GPIO_INT_CAUSE 0x14 317183840Sraj#define GPIO_INT_EDGE_MASK 0x18 318183840Sraj#define GPIO_INT_LEV_MASK 0x1c 319183840Sraj 320183840Sraj#define GPIO_HI_DATA_OUT 0x40 321183840Sraj#define GPIO_HI_DATA_OUT_EN_CTRL 0x44 322183840Sraj#define GPIO_HI_BLINK_EN 0x48 323183840Sraj#define GPIO_HI_DATA_IN_POLAR 0x4c 324183840Sraj#define GPIO_HI_DATA_IN 0x50 325183840Sraj#define GPIO_HI_INT_CAUSE 0x54 326183840Sraj#define GPIO_HI_INT_EDGE_MASK 0x58 327183840Sraj#define GPIO_HI_INT_LEV_MASK 0x5c 328183840Sraj 329183840Sraj#define GPIO(n) (1 << (n)) 330183840Sraj#define MV_GPIO_MAX_NPINS 64 331183840Sraj 332209131Sraj#define MV_GPIO_IN_NONE 0x0 333209131Sraj#define MV_GPIO_IN_POL_LOW (1 << 16) 334209131Sraj#define MV_GPIO_IN_IRQ_EDGE (2 << 16) 335209131Sraj#define MV_GPIO_IN_IRQ_LEVEL (4 << 16) 336209131Sraj#define MV_GPIO_OUT_NONE 0x0 337209131Sraj#define MV_GPIO_OUT_BLINK 0x1 338209131Sraj#define MV_GPIO_OUT_OPEN_DRAIN 0x2 339209131Sraj#define MV_GPIO_OUT_OPEN_SRC 0x4 340183840Sraj 341183840Sraj#define IS_GPIO_IRQ(irq) ((irq) >= NIRQ && (irq) < NIRQ + MV_GPIO_MAX_NPINS) 342183840Sraj#define GPIO2IRQ(gpio) ((gpio) + NIRQ) 343183840Sraj#define IRQ2GPIO(irq) ((irq) - NIRQ) 344183840Sraj 345239277Sgonzo#if defined(SOC_MV_ORION) || defined(SOC_MV_LOKIPLUS) 346183840Sraj#define SAMPLE_AT_RESET 0x10 347186899Sraj#elif defined(SOC_MV_KIRKWOOD) 348183840Sraj#define SAMPLE_AT_RESET 0x30 349243580Smarcel#elif defined(SOC_MV_FREY) 350243580Smarcel#define SAMPLE_AT_RESET 0x100 351294416Szbb#elif defined(SOC_MV_ARMADA38X) 352294416Szbb#define SAMPLE_AT_RESET 0x400 353243580Smarcel#endif 354243580Smarcel#if defined(SOC_MV_DISCOVERY) 355186899Sraj#define SAMPLE_AT_RESET_LO 0x30 356186899Sraj#define SAMPLE_AT_RESET_HI 0x34 357239277Sgonzo#elif defined(SOC_MV_DOVE) 358239277Sgonzo#define SAMPLE_AT_RESET_LO 0x14 359239277Sgonzo#define SAMPLE_AT_RESET_HI 0x18 360240488Sgber#elif defined(SOC_MV_ARMADAXP) 361240488Sgber#define SAMPLE_AT_RESET_LO 0x30 362240488Sgber#define SAMPLE_AT_RESET_HI 0x34 363183840Sraj#endif 364183840Sraj 365183840Sraj/* 366183840Sraj * Clocks 367183840Sraj */ 368186899Sraj#if defined(SOC_MV_ORION) 369186899Sraj#define TCLK_MASK 0x00000300 370186899Sraj#define TCLK_SHIFT 0x08 371186899Sraj#elif defined(SOC_MV_DISCOVERY) 372186899Sraj#define TCLK_MASK 0x00000180 373186899Sraj#define TCLK_SHIFT 0x07 374239277Sgonzo#elif defined(SOC_MV_LOKIPLUS) 375239277Sgonzo#define TCLK_MASK 0x0000F000 376239277Sgonzo#define TCLK_SHIFT 0x0C 377294416Szbb#elif defined(SOC_MV_ARMADA38X) 378294416Szbb#define TCLK_MASK 0x00008000 379294416Szbb#define TCLK_SHIFT 15 380183840Sraj#endif 381183840Sraj 382183840Sraj#define TCLK_100MHZ 100000000 383183840Sraj#define TCLK_125MHZ 125000000 384183840Sraj#define TCLK_133MHZ 133333333 385183840Sraj#define TCLK_150MHZ 150000000 386183840Sraj#define TCLK_166MHZ 166666667 387183840Sraj#define TCLK_200MHZ 200000000 388239277Sgonzo#define TCLK_250MHZ 250000000 389239277Sgonzo#define TCLK_300MHZ 300000000 390239277Sgonzo#define TCLK_667MHZ 667000000 391183840Sraj 392183840Sraj/* 393239277Sgonzo * CPU Cache Configuration 394239277Sgonzo */ 395239277Sgonzo 396239277Sgonzo#define CPU_CONFIG 0x00000000 397239277Sgonzo#define CPU_CONFIG_IC_PREF 0x00010000 398239277Sgonzo#define CPU_CONFIG_DC_PREF 0x00020000 399239277Sgonzo#define CPU_CONTROL 0x00000004 400239277Sgonzo#define CPU_CONTROL_L2_SIZE 0x00200000 /* Only on Discovery */ 401239277Sgonzo#define CPU_CONTROL_L2_MODE 0x00020000 /* Only on Discovery */ 402239277Sgonzo#define CPU_L2_CONFIG 0x00000028 /* Only on Kirkwood */ 403239277Sgonzo#define CPU_L2_CONFIG_MODE 0x00000010 /* Only on Kirkwood */ 404239277Sgonzo 405239277Sgonzo/* 406239277Sgonzo * PCI Express port control (CPU Control registers) 407239277Sgonzo */ 408239277Sgonzo#define CPU_CONTROL_PCIE_DISABLE(n) (1 << (3 * (n))) 409239277Sgonzo 410239277Sgonzo/* 411239277Sgonzo * Vendor ID 412239277Sgonzo */ 413239277Sgonzo#define PCI_VENDORID_MRVL 0x11AB 414239277Sgonzo#define PCI_VENDORID_MRVL2 0x1B4B 415239277Sgonzo 416239277Sgonzo/* 417183840Sraj * Chip ID 418183840Sraj */ 419191140Sraj#define MV_DEV_88F5181 0x5181 420191140Sraj#define MV_DEV_88F5182 0x5182 421191140Sraj#define MV_DEV_88F5281 0x5281 422191140Sraj#define MV_DEV_88F6281 0x6281 423239370Shrs#define MV_DEV_88F6282 0x6282 424239277Sgonzo#define MV_DEV_88F6781 0x6781 425294416Szbb#define MV_DEV_88F6828 0x6828 426294416Szbb#define MV_DEV_88F6820 0x6820 427294416Szbb#define MV_DEV_88F6810 0x6810 428191140Sraj#define MV_DEV_MV78100_Z0 0x6381 429191140Sraj#define MV_DEV_MV78100 0x7810 430239277Sgonzo#define MV_DEV_MV78130 0x7813 431239277Sgonzo#define MV_DEV_MV78160 0x7816 432239277Sgonzo#define MV_DEV_MV78230 0x7823 433239277Sgonzo#define MV_DEV_MV78260 0x7826 434239277Sgonzo#define MV_DEV_MV78460 0x7846 435239277Sgonzo#define MV_DEV_88RC8180 0x8180 436239277Sgonzo#define MV_DEV_88RC9480 0x9480 437239277Sgonzo#define MV_DEV_88RC9580 0x9580 438183840Sraj 439239277Sgonzo#define MV_DEV_FAMILY_MASK 0xff00 440239277Sgonzo#define MV_DEV_DISCOVERY 0x7800 441239277Sgonzo 442239277Sgonzo/* 443239277Sgonzo * Doorbell register control 444239277Sgonzo */ 445239277Sgonzo#define MV_DRBL_PCIE_TO_CPU 0 446239277Sgonzo#define MV_DRBL_CPU_TO_PCIE 1 447239277Sgonzo 448239277Sgonzo#if defined(SOC_MV_FREY) 449239277Sgonzo#define MV_DRBL_CAUSE(d,u) (0x60 + 0x20 * (d) + 0x8 * (u)) 450239277Sgonzo#define MV_DRBL_MASK(d,u) (0x60 + 0x20 * (d) + 0x8 * (u) + 0x4) 451239277Sgonzo#define MV_DRBL_MSG(m,d,u) (0x8 * (u) + 0x20 * (d) + 0x4 * (m)) 452239277Sgonzo#else 453239277Sgonzo#define MV_DRBL_CAUSE(d,u) (0x10 * (u) + 0x8 * (d)) 454239277Sgonzo#define MV_DRBL_MASK(d,u) (0x10 * (u) + 0x8 * (d) + 0x4) 455239277Sgonzo#define MV_DRBL_MSG(m,d,u) (0x10 * (u) + 0x8 * (d) + 0x4 * (m) + 0x30) 456239277Sgonzo#endif 457294426Szbb 458294426Szbb/* 459294426Szbb * SCU 460294426Szbb */ 461294426Szbb#if defined(SOC_MV_ARMADA38X) 462294426Szbb#define MV_SCU_BASE (MV_BASE + 0xc000) 463294426Szbb#define MV_SCU_REGS_LEN 0x100 464294426Szbb#define MV_SCU_REG_CTRL 0 465294426Szbb#define MV_SCU_ENABLE 1 466294426Szbb#endif 467294426Szbb 468183840Sraj#endif /* _MVREG_H_ */ 469