mvreg.h revision 239277
1183840Sraj/*- 2239277Sgonzo * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 3183840Sraj * All rights reserved. 4183840Sraj * 5183840Sraj * Developed by Semihalf. 6183840Sraj * 7183840Sraj * Redistribution and use in source and binary forms, with or without 8183840Sraj * modification, are permitted provided that the following conditions 9183840Sraj * are met: 10183840Sraj * 1. Redistributions of source code must retain the above copyright 11183840Sraj * notice, this list of conditions and the following disclaimer. 12183840Sraj * 2. Redistributions in binary form must reproduce the above copyright 13183840Sraj * notice, this list of conditions and the following disclaimer in the 14183840Sraj * documentation and/or other materials provided with the distribution. 15183840Sraj * 3. Neither the name of MARVELL nor the names of contributors 16183840Sraj * may be used to endorse or promote products derived from this software 17183840Sraj * without specific prior written permission. 18183840Sraj * 19183840Sraj * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20183840Sraj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21183840Sraj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22183840Sraj * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23183840Sraj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24183840Sraj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25183840Sraj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26183840Sraj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27183840Sraj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28183840Sraj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29183840Sraj * SUCH DAMAGE. 30183840Sraj * 31183840Sraj * $FreeBSD: head/sys/arm/mv/mvreg.h 239277 2012-08-15 05:15:49Z gonzo $ 32183840Sraj */ 33183840Sraj 34183840Sraj#ifndef _MVREG_H_ 35183840Sraj#define _MVREG_H_ 36183840Sraj 37183840Sraj#if defined(SOC_MV_DISCOVERY) 38183840Sraj#define IRQ_CAUSE_ERROR 0x0 39183840Sraj#define IRQ_CAUSE 0x4 40183840Sraj#define IRQ_CAUSE_HI 0x8 41183840Sraj#define IRQ_MASK_ERROR 0xC 42183840Sraj#define IRQ_MASK 0x10 43183840Sraj#define IRQ_MASK_HI 0x14 44183840Sraj#define IRQ_CAUSE_SELECT 0x18 45183840Sraj#define FIQ_MASK_ERROR 0x1C 46183840Sraj#define FIQ_MASK 0x20 47183840Sraj#define FIQ_MASK_HI 0x24 48183840Sraj#define FIQ_CAUSE_SELECT 0x28 49239277Sgonzo#define ENDPOINT_IRQ_MASK_ERROR(n) 0x2C 50239277Sgonzo#define ENDPOINT_IRQ_MASK(n) 0x30 51239277Sgonzo#define ENDPOINT_IRQ_MASK_HI(n) 0x34 52183840Sraj#define ENDPOINT_IRQ_CAUSE_SELECT 0x38 53239277Sgonzo#elif defined (SOC_MV_LOKIPLUS) || defined (SOC_MV_FREY) 54183840Sraj#define IRQ_CAUSE 0x0 55183840Sraj#define IRQ_MASK 0x4 56183840Sraj#define FIQ_MASK 0x8 57239277Sgonzo#define ENDPOINT_IRQ_MASK(n) (0xC + (n) * 4) 58239277Sgonzo#define IRQ_CAUSE_HI (-1) /* Fake defines for unified */ 59239277Sgonzo#define IRQ_MASK_HI (-1) /* interrupt controller code */ 60239277Sgonzo#define FIQ_MASK_HI (-1) 61239277Sgonzo#define ENDPOINT_IRQ_MASK_HI(n) (-1) 62239277Sgonzo#define ENDPOINT_IRQ_MASK_ERROR(n) (-1) 63239277Sgonzo#define IRQ_CAUSE_ERROR (-1) 64239277Sgonzo#define IRQ_MASK_ERROR (-1) 65239277Sgonzo#elif defined (SOC_MV_ARMADAXP) 66239277Sgonzo#define IRQ_CAUSE 0x18 67239277Sgonzo#define IRQ_MASK 0x30 68239277Sgonzo#else /* !SOC_MV_DISCOVERY && !SOC_MV_LOKIPLUS */ 69239277Sgonzo#define IRQ_CAUSE 0x0 70239277Sgonzo#define IRQ_MASK 0x4 71239277Sgonzo#define FIQ_MASK 0x8 72239277Sgonzo#define ENDPOINT_IRQ_MASK(n) 0xC 73183840Sraj#define IRQ_CAUSE_HI 0x10 74183840Sraj#define IRQ_MASK_HI 0x14 75183840Sraj#define FIQ_MASK_HI 0x18 76239277Sgonzo#define ENDPOINT_IRQ_MASK_HI(n) 0x1C 77239277Sgonzo#define ENDPOINT_IRQ_MASK_ERROR(n) (-1) 78183840Sraj#define IRQ_CAUSE_ERROR (-1) /* Fake defines for unified */ 79183840Sraj#define IRQ_MASK_ERROR (-1) /* interrupt controller code */ 80183840Sraj#endif 81183840Sraj 82239277Sgonzo#if defined(SOC_MV_FREY) 83239277Sgonzo#define BRIDGE_IRQ_CAUSE 0x118 84239277Sgonzo#define IRQ_TIMER0 0x00000002 85239277Sgonzo#define IRQ_TIMER1 0x00000004 86239277Sgonzo#define IRQ_TIMER_WD 0x00000008 87239277Sgonzo 88239277Sgonzo#define BRIDGE_IRQ_MASK 0x11c 89239277Sgonzo#define IRQ_TIMER0_MASK 0x00000002 90239277Sgonzo#define IRQ_TIMER1_MASK 0x00000004 91239277Sgonzo#define IRQ_TIMER_WD_MASK 0x00000008 92239277Sgonzo#elif defined(SOC_MV_ARMADAXP) 93239277Sgonzo#define BRIDGE_IRQ_CAUSE 0x68 94239277Sgonzo#define IRQ_TIMER0 0x00000001 95239277Sgonzo#define IRQ_TIMER1 0x00000002 96239277Sgonzo#define IRQ_TIMER_WD 0x00000004 97239277Sgonzo#else 98183840Sraj#define BRIDGE_IRQ_CAUSE 0x10 99183840Sraj#define IRQ_CPU_SELF 0x00000001 100183840Sraj#define IRQ_TIMER0 0x00000002 101183840Sraj#define IRQ_TIMER1 0x00000004 102183840Sraj#define IRQ_TIMER_WD 0x00000008 103183840Sraj 104183840Sraj#define BRIDGE_IRQ_MASK 0x14 105183840Sraj#define IRQ_CPU_MASK 0x00000001 106183840Sraj#define IRQ_TIMER0_MASK 0x00000002 107183840Sraj#define IRQ_TIMER1_MASK 0x00000004 108183840Sraj#define IRQ_TIMER_WD_MASK 0x00000008 109239277Sgonzo#endif 110183840Sraj 111239277Sgonzo#if defined(SOC_MV_LOKIPLUS) || defined(SOC_MV_FREY) 112239277Sgonzo#define IRQ_CPU_SELF_CLR IRQ_CPU_SELF 113239277Sgonzo#define IRQ_TIMER0_CLR IRQ_TIMER0 114239277Sgonzo#define IRQ_TIMER1_CLR IRQ_TIMER1 115239277Sgonzo#define IRQ_TIMER_WD_CLR IRQ_TIMER_WD 116239277Sgonzo#else 117239277Sgonzo#define IRQ_CPU_SELF_CLR (~IRQ_CPU_SELF) 118239277Sgonzo#define IRQ_TIMER0_CLR (~IRQ_TIMER0) 119239277Sgonzo#define IRQ_TIMER1_CLR (~IRQ_TIMER1) 120239277Sgonzo#define IRQ_TIMER_WD_CLR (~IRQ_TIMER_WD) 121239277Sgonzo#endif 122239277Sgonzo 123183840Sraj/* 124183840Sraj * System reset 125183840Sraj */ 126183840Sraj#define RSTOUTn_MASK 0x8 127183840Sraj#define WD_RST_OUT_EN 0x00000002 128183840Sraj#define SOFT_RST_OUT_EN 0x00000004 129183840Sraj#define SYSTEM_SOFT_RESET 0xc 130183840Sraj#define SYS_SOFT_RST 0x00000001 131183840Sraj 132183840Sraj/* 133183840Sraj * Power Control 134183840Sraj */ 135183840Sraj#define CPU_PM_CTRL 0x1C 136183840Sraj#define CPU_PM_CTRL_NONE 0 137196532Sraj#define CPU_PM_CTRL_ALL ~0x0 138183840Sraj 139183840Sraj#if defined(SOC_MV_KIRKWOOD) 140183840Sraj#define CPU_PM_CTRL_GE0 (1 << 0) 141183840Sraj#define CPU_PM_CTRL_PEX0_PHY (1 << 1) 142183840Sraj#define CPU_PM_CTRL_PEX0 (1 << 2) 143183840Sraj#define CPU_PM_CTRL_USB0 (1 << 3) 144183840Sraj#define CPU_PM_CTRL_SDIO (1 << 4) 145183840Sraj#define CPU_PM_CTRL_TSU (1 << 5) 146183840Sraj#define CPU_PM_CTRL_DUNIT (1 << 6) 147183840Sraj#define CPU_PM_CTRL_RUNIT (1 << 7) 148183840Sraj#define CPU_PM_CTRL_XOR0 (1 << 8) 149183840Sraj#define CPU_PM_CTRL_AUDIO (1 << 9) 150183840Sraj#define CPU_PM_CTRL_SATA0 (1 << 14) 151183840Sraj#define CPU_PM_CTRL_SATA1 (1 << 15) 152183840Sraj#define CPU_PM_CTRL_XOR1 (1 << 16) 153183840Sraj#define CPU_PM_CTRL_CRYPTO (1 << 17) 154196532Sraj#define CPU_PM_CTRL_GE1 (1 << 19) 155196532Sraj#define CPU_PM_CTRL_TDM (1 << 20) 156196532Sraj#define CPU_PM_CTRL_XOR (CPU_PM_CTRL_XOR0 | CPU_PM_CTRL_XOR1) 157196532Sraj#define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_USB0) 158196532Sraj#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1) 159209131Sraj#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \ 160209131Sraj (1 - (u))) 161209131Sraj#define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE) 162183840Sraj#elif defined(SOC_MV_DISCOVERY) 163183840Sraj#define CPU_PM_CTRL_GE0 (1 << 1) 164183840Sraj#define CPU_PM_CTRL_GE1 (1 << 2) 165183840Sraj#define CPU_PM_CTRL_PEX00 (1 << 5) 166183840Sraj#define CPU_PM_CTRL_PEX01 (1 << 6) 167183840Sraj#define CPU_PM_CTRL_PEX02 (1 << 7) 168183840Sraj#define CPU_PM_CTRL_PEX03 (1 << 8) 169183840Sraj#define CPU_PM_CTRL_PEX10 (1 << 9) 170183840Sraj#define CPU_PM_CTRL_PEX11 (1 << 10) 171183840Sraj#define CPU_PM_CTRL_PEX12 (1 << 11) 172183840Sraj#define CPU_PM_CTRL_PEX13 (1 << 12) 173183840Sraj#define CPU_PM_CTRL_SATA0_PHY (1 << 13) 174183840Sraj#define CPU_PM_CTRL_SATA0 (1 << 14) 175183840Sraj#define CPU_PM_CTRL_SATA1_PHY (1 << 15) 176183840Sraj#define CPU_PM_CTRL_SATA1 (1 << 16) 177183840Sraj#define CPU_PM_CTRL_USB0 (1 << 17) 178183840Sraj#define CPU_PM_CTRL_USB1 (1 << 18) 179183840Sraj#define CPU_PM_CTRL_USB2 (1 << 19) 180183840Sraj#define CPU_PM_CTRL_IDMA (1 << 20) 181183840Sraj#define CPU_PM_CTRL_XOR (1 << 21) 182183840Sraj#define CPU_PM_CTRL_CRYPTO (1 << 22) 183183840Sraj#define CPU_PM_CTRL_DEVICE (1 << 23) 184196532Sraj#define CPU_PM_CTRL_USB(u) (1 << (17 + (u))) 185196532Sraj#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1) 186209131Sraj#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \ 187209131Sraj (1 - (u))) 188196532Sraj#else 189196532Sraj#define CPU_PM_CTRL_CRYPTO (CPU_PM_CTRL_NONE) 190196532Sraj#define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE) 191196532Sraj#define CPU_PM_CTRL_XOR (CPU_PM_CTRL_NONE) 192196532Sraj#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_NONE) 193196532Sraj#define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_NONE) 194209131Sraj#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_NONE) 195183840Sraj#endif 196183840Sraj 197183840Sraj/* 198183840Sraj * Timers 199183840Sraj */ 200239277Sgonzo#define CPU_TIMERS_BASE 0x300 201183840Sraj#define CPU_TIMER_CONTROL 0x0 202183840Sraj#define CPU_TIMER0_EN 0x00000001 203183840Sraj#define CPU_TIMER0_AUTO 0x00000002 204183840Sraj#define CPU_TIMER1_EN 0x00000004 205183840Sraj#define CPU_TIMER1_AUTO 0x00000008 206183840Sraj#define CPU_TIMER_WD_EN 0x00000010 207183840Sraj#define CPU_TIMER_WD_AUTO 0x00000020 208183840Sraj#define CPU_TIMER0_REL 0x10 209183840Sraj#define CPU_TIMER0 0x14 210183840Sraj 211183840Sraj/* 212194845Sraj * SATA 213194845Sraj */ 214194845Sraj#define SATA_CHAN_NUM 2 215194845Sraj 216194845Sraj#define EDMA_REGISTERS_OFFSET 0x2000 217194845Sraj#define EDMA_REGISTERS_SIZE 0x2000 218194845Sraj#define SATA_EDMA_BASE(ch) (EDMA_REGISTERS_OFFSET + \ 219194845Sraj ((ch) * EDMA_REGISTERS_SIZE)) 220194845Sraj 221194845Sraj/* SATAHC registers */ 222194845Sraj#define SATA_CR 0x000 /* Configuration Reg. */ 223194845Sraj#define SATA_CR_NODMABS (1 << 8) 224194845Sraj#define SATA_CR_NOEDMABS (1 << 9) 225194845Sraj#define SATA_CR_NOPRDPBS (1 << 10) 226194845Sraj#define SATA_CR_COALDIS(ch) (1 << (24 + ch)) 227194845Sraj 228239277Sgonzo/* Interrupt Coalescing Threshold Reg. */ 229239277Sgonzo#define SATA_ICTR 0x00C 230239277Sgonzo#define SATA_ICTR_MAX ((1 << 8) - 1) 231239277Sgonzo 232239277Sgonzo/* Interrupt Time Threshold Reg. */ 233239277Sgonzo#define SATA_ITTR 0x010 234239277Sgonzo#define SATA_ITTR_MAX ((1 << 24) - 1) 235239277Sgonzo 236239277Sgonzo#define SATA_ICR 0x014 /* Interrupt Cause Reg. */ 237194845Sraj#define SATA_ICR_DMADONE(ch) (1 << (ch)) 238194845Sraj#define SATA_ICR_COAL (1 << 4) 239194845Sraj#define SATA_ICR_DEV(ch) (1 << (8 + ch)) 240194845Sraj 241194845Sraj#define SATA_MICR 0x020 /* Main Interrupt Cause Reg. */ 242194845Sraj#define SATA_MICR_ERR(ch) (1 << (2 * ch)) 243194845Sraj#define SATA_MICR_DONE(ch) (1 << ((2 * ch) + 1)) 244194845Sraj#define SATA_MICR_DMADONE(ch) (1 << (4 + ch)) 245194845Sraj#define SATA_MICR_COAL (1 << 8) 246194845Sraj 247194845Sraj#define SATA_MIMR 0x024 /* Main Interrupt Mask Reg. */ 248194845Sraj 249194845Sraj/* Shadow registers */ 250194845Sraj#define SATA_SHADOWR_BASE(ch) (SATA_EDMA_BASE(ch) + 0x100) 251194845Sraj#define SATA_SHADOWR_CONTROL(ch) (SATA_EDMA_BASE(ch) + 0x120) 252194845Sraj 253194845Sraj/* SATA registers */ 254194845Sraj#define SATA_SATA_SSTATUS(ch) (SATA_EDMA_BASE(ch) + 0x300) 255194845Sraj#define SATA_SATA_SERROR(ch) (SATA_EDMA_BASE(ch) + 0x304) 256194845Sraj#define SATA_SATA_SCONTROL(ch) (SATA_EDMA_BASE(ch) + 0x308) 257194845Sraj#define SATA_SATA_FISICR(ch) (SATA_EDMA_BASE(ch) + 0x364) 258194845Sraj 259194845Sraj/* EDMA registers */ 260194845Sraj#define SATA_EDMA_CFG(ch) (SATA_EDMA_BASE(ch) + 0x000) 261194845Sraj#define SATA_EDMA_CFG_QL128 (1 << 19) 262194845Sraj#define SATA_EDMA_CFG_HQCACHE (1 << 22) 263194845Sraj 264194845Sraj#define SATA_EDMA_IECR(ch) (SATA_EDMA_BASE(ch) + 0x008) 265194845Sraj 266194845Sraj#define SATA_EDMA_IEMR(ch) (SATA_EDMA_BASE(ch) + 0x00C) 267194845Sraj#define SATA_EDMA_REQBAHR(ch) (SATA_EDMA_BASE(ch) + 0x010) 268194845Sraj#define SATA_EDMA_REQIPR(ch) (SATA_EDMA_BASE(ch) + 0x014) 269194845Sraj#define SATA_EDMA_REQOPR(ch) (SATA_EDMA_BASE(ch) + 0x018) 270194845Sraj#define SATA_EDMA_RESBAHR(ch) (SATA_EDMA_BASE(ch) + 0x01C) 271194845Sraj#define SATA_EDMA_RESIPR(ch) (SATA_EDMA_BASE(ch) + 0x020) 272194845Sraj#define SATA_EDMA_RESOPR(ch) (SATA_EDMA_BASE(ch) + 0x024) 273194845Sraj 274194845Sraj#define SATA_EDMA_CMD(ch) (SATA_EDMA_BASE(ch) + 0x028) 275194845Sraj#define SATA_EDMA_CMD_ENABLE (1 << 0) 276194845Sraj#define SATA_EDMA_CMD_DISABLE (1 << 1) 277194845Sraj#define SATA_EDMA_CMD_RESET (1 << 2) 278194845Sraj 279194845Sraj#define SATA_EDMA_STATUS(ch) (SATA_EDMA_BASE(ch) + 0x030) 280194845Sraj#define SATA_EDMA_STATUS_IDLE (1 << 7) 281194845Sraj 282194845Sraj/* Offset to extract input slot from REQIPR register */ 283194845Sraj#define SATA_EDMA_REQIS_OFS 5 284194845Sraj 285194845Sraj/* Offset to extract input slot from RESOPR register */ 286194845Sraj#define SATA_EDMA_RESOS_OFS 3 287194845Sraj 288194845Sraj/* 289183840Sraj * GPIO 290183840Sraj */ 291183840Sraj#define GPIO_DATA_OUT 0x00 292183840Sraj#define GPIO_DATA_OUT_EN_CTRL 0x04 293183840Sraj#define GPIO_BLINK_EN 0x08 294183840Sraj#define GPIO_DATA_IN_POLAR 0x0c 295183840Sraj#define GPIO_DATA_IN 0x10 296183840Sraj#define GPIO_INT_CAUSE 0x14 297183840Sraj#define GPIO_INT_EDGE_MASK 0x18 298183840Sraj#define GPIO_INT_LEV_MASK 0x1c 299183840Sraj 300183840Sraj#define GPIO_HI_DATA_OUT 0x40 301183840Sraj#define GPIO_HI_DATA_OUT_EN_CTRL 0x44 302183840Sraj#define GPIO_HI_BLINK_EN 0x48 303183840Sraj#define GPIO_HI_DATA_IN_POLAR 0x4c 304183840Sraj#define GPIO_HI_DATA_IN 0x50 305183840Sraj#define GPIO_HI_INT_CAUSE 0x54 306183840Sraj#define GPIO_HI_INT_EDGE_MASK 0x58 307183840Sraj#define GPIO_HI_INT_LEV_MASK 0x5c 308183840Sraj 309183840Sraj#define GPIO(n) (1 << (n)) 310183840Sraj#define MV_GPIO_MAX_NPINS 64 311183840Sraj 312209131Sraj#define MV_GPIO_IN_NONE 0x0 313209131Sraj#define MV_GPIO_IN_POL_LOW (1 << 16) 314209131Sraj#define MV_GPIO_IN_IRQ_EDGE (2 << 16) 315209131Sraj#define MV_GPIO_IN_IRQ_LEVEL (4 << 16) 316209131Sraj#define MV_GPIO_OUT_NONE 0x0 317209131Sraj#define MV_GPIO_OUT_BLINK 0x1 318209131Sraj#define MV_GPIO_OUT_OPEN_DRAIN 0x2 319209131Sraj#define MV_GPIO_OUT_OPEN_SRC 0x4 320183840Sraj 321183840Sraj#define IS_GPIO_IRQ(irq) ((irq) >= NIRQ && (irq) < NIRQ + MV_GPIO_MAX_NPINS) 322183840Sraj#define GPIO2IRQ(gpio) ((gpio) + NIRQ) 323183840Sraj#define IRQ2GPIO(irq) ((irq) - NIRQ) 324183840Sraj 325239277Sgonzo#if defined(SOC_MV_ORION) || defined(SOC_MV_LOKIPLUS) 326183840Sraj#define SAMPLE_AT_RESET 0x10 327186899Sraj#elif defined(SOC_MV_KIRKWOOD) 328183840Sraj#define SAMPLE_AT_RESET 0x30 329186899Sraj#elif defined(SOC_MV_DISCOVERY) 330186899Sraj#define SAMPLE_AT_RESET_LO 0x30 331186899Sraj#define SAMPLE_AT_RESET_HI 0x34 332239277Sgonzo#elif defined(SOC_MV_DOVE) 333239277Sgonzo#define SAMPLE_AT_RESET_LO 0x14 334239277Sgonzo#define SAMPLE_AT_RESET_HI 0x18 335239277Sgonzo#elif defined(SOC_MV_FREY) 336239277Sgonzo#define SAMPLE_AT_RESET 0x100 337183840Sraj#endif 338183840Sraj 339183840Sraj/* 340183840Sraj * Clocks 341183840Sraj */ 342186899Sraj#if defined(SOC_MV_ORION) 343186899Sraj#define TCLK_MASK 0x00000300 344186899Sraj#define TCLK_SHIFT 0x08 345186899Sraj#elif defined(SOC_MV_DISCOVERY) 346186899Sraj#define TCLK_MASK 0x00000180 347186899Sraj#define TCLK_SHIFT 0x07 348239277Sgonzo#elif defined(SOC_MV_LOKIPLUS) 349239277Sgonzo#define TCLK_MASK 0x0000F000 350239277Sgonzo#define TCLK_SHIFT 0x0C 351183840Sraj#endif 352183840Sraj 353183840Sraj#define TCLK_100MHZ 100000000 354183840Sraj#define TCLK_125MHZ 125000000 355183840Sraj#define TCLK_133MHZ 133333333 356183840Sraj#define TCLK_150MHZ 150000000 357183840Sraj#define TCLK_166MHZ 166666667 358183840Sraj#define TCLK_200MHZ 200000000 359239277Sgonzo#define TCLK_250MHZ 250000000 360239277Sgonzo#define TCLK_300MHZ 300000000 361239277Sgonzo#define TCLK_667MHZ 667000000 362183840Sraj 363183840Sraj/* 364239277Sgonzo * CPU Cache Configuration 365239277Sgonzo */ 366239277Sgonzo 367239277Sgonzo#define CPU_CONFIG 0x00000000 368239277Sgonzo#define CPU_CONFIG_IC_PREF 0x00010000 369239277Sgonzo#define CPU_CONFIG_DC_PREF 0x00020000 370239277Sgonzo#define CPU_CONTROL 0x00000004 371239277Sgonzo#define CPU_CONTROL_L2_SIZE 0x00200000 /* Only on Discovery */ 372239277Sgonzo#define CPU_CONTROL_L2_MODE 0x00020000 /* Only on Discovery */ 373239277Sgonzo#define CPU_L2_CONFIG 0x00000028 /* Only on Kirkwood */ 374239277Sgonzo#define CPU_L2_CONFIG_MODE 0x00000010 /* Only on Kirkwood */ 375239277Sgonzo 376239277Sgonzo/* 377239277Sgonzo * PCI Express port control (CPU Control registers) 378239277Sgonzo */ 379239277Sgonzo#define CPU_CONTROL_PCIE_DISABLE(n) (1 << (3 * (n))) 380239277Sgonzo 381239277Sgonzo/* 382239277Sgonzo * Vendor ID 383239277Sgonzo */ 384239277Sgonzo#define PCI_VENDORID_MRVL 0x11AB 385239277Sgonzo#define PCI_VENDORID_MRVL2 0x1B4B 386239277Sgonzo 387239277Sgonzo/* 388183840Sraj * Chip ID 389183840Sraj */ 390191140Sraj#define MV_DEV_88F5181 0x5181 391191140Sraj#define MV_DEV_88F5182 0x5182 392191140Sraj#define MV_DEV_88F5281 0x5281 393191140Sraj#define MV_DEV_88F6281 0x6281 394239277Sgonzo#define MV_DEV_88F6781 0x6781 395238873Shrs#define MV_DEV_88F6282 0x6282 396191140Sraj#define MV_DEV_MV78100_Z0 0x6381 397191140Sraj#define MV_DEV_MV78100 0x7810 398239277Sgonzo#define MV_DEV_MV78130 0x7813 399239277Sgonzo#define MV_DEV_MV78160 0x7816 400239277Sgonzo#define MV_DEV_MV78230 0x7823 401239277Sgonzo#define MV_DEV_MV78260 0x7826 402239277Sgonzo#define MV_DEV_MV78460 0x7846 403239277Sgonzo#define MV_DEV_88RC8180 0x8180 404239277Sgonzo#define MV_DEV_88RC9480 0x9480 405239277Sgonzo#define MV_DEV_88RC9580 0x9580 406183840Sraj 407239277Sgonzo#define MV_DEV_FAMILY_MASK 0xff00 408239277Sgonzo#define MV_DEV_DISCOVERY 0x7800 409239277Sgonzo 410239277Sgonzo/* 411239277Sgonzo * Doorbell register control 412239277Sgonzo */ 413239277Sgonzo#define MV_DRBL_PCIE_TO_CPU 0 414239277Sgonzo#define MV_DRBL_CPU_TO_PCIE 1 415239277Sgonzo 416239277Sgonzo#if defined(SOC_MV_FREY) 417239277Sgonzo#define MV_DRBL_CAUSE(d,u) (0x60 + 0x20 * (d) + 0x8 * (u)) 418239277Sgonzo#define MV_DRBL_MASK(d,u) (0x60 + 0x20 * (d) + 0x8 * (u) + 0x4) 419239277Sgonzo#define MV_DRBL_MSG(m,d,u) (0x8 * (u) + 0x20 * (d) + 0x4 * (m)) 420239277Sgonzo#else 421239277Sgonzo#define MV_DRBL_CAUSE(d,u) (0x10 * (u) + 0x8 * (d)) 422239277Sgonzo#define MV_DRBL_MASK(d,u) (0x10 * (u) + 0x8 * (d) + 0x4) 423239277Sgonzo#define MV_DRBL_MSG(m,d,u) (0x10 * (u) + 0x8 * (d) + 0x4 * (m) + 0x30) 424239277Sgonzo#endif 425183840Sraj#endif /* _MVREG_H_ */ 426