mvreg.h revision 238873
1183840Sraj/*- 2183840Sraj * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD. 3183840Sraj * All rights reserved. 4183840Sraj * 5183840Sraj * Developed by Semihalf. 6183840Sraj * 7183840Sraj * Redistribution and use in source and binary forms, with or without 8183840Sraj * modification, are permitted provided that the following conditions 9183840Sraj * are met: 10183840Sraj * 1. Redistributions of source code must retain the above copyright 11183840Sraj * notice, this list of conditions and the following disclaimer. 12183840Sraj * 2. Redistributions in binary form must reproduce the above copyright 13183840Sraj * notice, this list of conditions and the following disclaimer in the 14183840Sraj * documentation and/or other materials provided with the distribution. 15183840Sraj * 3. Neither the name of MARVELL nor the names of contributors 16183840Sraj * may be used to endorse or promote products derived from this software 17183840Sraj * without specific prior written permission. 18183840Sraj * 19183840Sraj * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20183840Sraj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21183840Sraj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22183840Sraj * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23183840Sraj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24183840Sraj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25183840Sraj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26183840Sraj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27183840Sraj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28183840Sraj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29183840Sraj * SUCH DAMAGE. 30183840Sraj * 31183840Sraj * $FreeBSD: head/sys/arm/mv/mvreg.h 238873 2012-07-28 21:56:24Z hrs $ 32183840Sraj */ 33183840Sraj 34183840Sraj#ifndef _MVREG_H_ 35183840Sraj#define _MVREG_H_ 36183840Sraj 37183840Sraj#define BRIDGE_IRQ_CAUSE 0x10 38183840Sraj#define BRIGDE_IRQ_MASK 0x14 39183840Sraj 40183840Sraj#if defined(SOC_MV_DISCOVERY) 41183840Sraj#define IRQ_CAUSE_ERROR 0x0 42183840Sraj#define IRQ_CAUSE 0x4 43183840Sraj#define IRQ_CAUSE_HI 0x8 44183840Sraj#define IRQ_MASK_ERROR 0xC 45183840Sraj#define IRQ_MASK 0x10 46183840Sraj#define IRQ_MASK_HI 0x14 47183840Sraj#define IRQ_CAUSE_SELECT 0x18 48183840Sraj#define FIQ_MASK_ERROR 0x1C 49183840Sraj#define FIQ_MASK 0x20 50183840Sraj#define FIQ_MASK_HI 0x24 51183840Sraj#define FIQ_CAUSE_SELECT 0x28 52183840Sraj#define ENDPOINT_IRQ_MASK_ERROR 0x2C 53183840Sraj#define ENDPOINT_IRQ_MASK 0x30 54183840Sraj#define ENDPOINT_IRQ_MASK_HI 0x34 55183840Sraj#define ENDPOINT_IRQ_CAUSE_SELECT 0x38 56183840Sraj#else /* !SOC_MV_DISCOVERY */ 57183840Sraj#define IRQ_CAUSE 0x0 58183840Sraj#define IRQ_MASK 0x4 59183840Sraj#define FIQ_MASK 0x8 60183840Sraj#define ENDPOINT_IRQ_MASK 0xC 61183840Sraj#define IRQ_CAUSE_HI 0x10 62183840Sraj#define IRQ_MASK_HI 0x14 63183840Sraj#define FIQ_MASK_HI 0x18 64183840Sraj#define ENDPOINT_IRQ_MASK_HI 0x1C 65183840Sraj#define IRQ_CAUSE_ERROR (-1) /* Fake defines for unified */ 66183840Sraj#define IRQ_MASK_ERROR (-1) /* interrupt controller code */ 67183840Sraj#endif 68183840Sraj 69183840Sraj#define BRIDGE_IRQ_CAUSE 0x10 70183840Sraj#define IRQ_CPU_SELF 0x00000001 71183840Sraj#define IRQ_TIMER0 0x00000002 72183840Sraj#define IRQ_TIMER1 0x00000004 73183840Sraj#define IRQ_TIMER_WD 0x00000008 74183840Sraj 75183840Sraj#define BRIDGE_IRQ_MASK 0x14 76183840Sraj#define IRQ_CPU_MASK 0x00000001 77183840Sraj#define IRQ_TIMER0_MASK 0x00000002 78183840Sraj#define IRQ_TIMER1_MASK 0x00000004 79183840Sraj#define IRQ_TIMER_WD_MASK 0x00000008 80183840Sraj 81183840Sraj/* 82183840Sraj * System reset 83183840Sraj */ 84183840Sraj#define RSTOUTn_MASK 0x8 85183840Sraj#define WD_RST_OUT_EN 0x00000002 86183840Sraj#define SOFT_RST_OUT_EN 0x00000004 87183840Sraj#define SYSTEM_SOFT_RESET 0xc 88183840Sraj#define SYS_SOFT_RST 0x00000001 89183840Sraj 90183840Sraj/* 91183840Sraj * Power Control 92183840Sraj */ 93183840Sraj#define CPU_PM_CTRL 0x1C 94183840Sraj#define CPU_PM_CTRL_NONE 0 95196532Sraj#define CPU_PM_CTRL_ALL ~0x0 96183840Sraj 97183840Sraj#if defined(SOC_MV_KIRKWOOD) 98183840Sraj#define CPU_PM_CTRL_GE0 (1 << 0) 99183840Sraj#define CPU_PM_CTRL_PEX0_PHY (1 << 1) 100183840Sraj#define CPU_PM_CTRL_PEX0 (1 << 2) 101183840Sraj#define CPU_PM_CTRL_USB0 (1 << 3) 102183840Sraj#define CPU_PM_CTRL_SDIO (1 << 4) 103183840Sraj#define CPU_PM_CTRL_TSU (1 << 5) 104183840Sraj#define CPU_PM_CTRL_DUNIT (1 << 6) 105183840Sraj#define CPU_PM_CTRL_RUNIT (1 << 7) 106183840Sraj#define CPU_PM_CTRL_XOR0 (1 << 8) 107183840Sraj#define CPU_PM_CTRL_AUDIO (1 << 9) 108183840Sraj#define CPU_PM_CTRL_SATA0 (1 << 14) 109183840Sraj#define CPU_PM_CTRL_SATA1 (1 << 15) 110183840Sraj#define CPU_PM_CTRL_XOR1 (1 << 16) 111183840Sraj#define CPU_PM_CTRL_CRYPTO (1 << 17) 112196532Sraj#define CPU_PM_CTRL_GE1 (1 << 19) 113196532Sraj#define CPU_PM_CTRL_TDM (1 << 20) 114196532Sraj#define CPU_PM_CTRL_XOR (CPU_PM_CTRL_XOR0 | CPU_PM_CTRL_XOR1) 115196532Sraj#define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_USB0) 116196532Sraj#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1) 117209131Sraj#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \ 118209131Sraj (1 - (u))) 119209131Sraj#define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE) 120183840Sraj#elif defined(SOC_MV_DISCOVERY) 121183840Sraj#define CPU_PM_CTRL_GE0 (1 << 1) 122183840Sraj#define CPU_PM_CTRL_GE1 (1 << 2) 123183840Sraj#define CPU_PM_CTRL_PEX00 (1 << 5) 124183840Sraj#define CPU_PM_CTRL_PEX01 (1 << 6) 125183840Sraj#define CPU_PM_CTRL_PEX02 (1 << 7) 126183840Sraj#define CPU_PM_CTRL_PEX03 (1 << 8) 127183840Sraj#define CPU_PM_CTRL_PEX10 (1 << 9) 128183840Sraj#define CPU_PM_CTRL_PEX11 (1 << 10) 129183840Sraj#define CPU_PM_CTRL_PEX12 (1 << 11) 130183840Sraj#define CPU_PM_CTRL_PEX13 (1 << 12) 131183840Sraj#define CPU_PM_CTRL_SATA0_PHY (1 << 13) 132183840Sraj#define CPU_PM_CTRL_SATA0 (1 << 14) 133183840Sraj#define CPU_PM_CTRL_SATA1_PHY (1 << 15) 134183840Sraj#define CPU_PM_CTRL_SATA1 (1 << 16) 135183840Sraj#define CPU_PM_CTRL_USB0 (1 << 17) 136183840Sraj#define CPU_PM_CTRL_USB1 (1 << 18) 137183840Sraj#define CPU_PM_CTRL_USB2 (1 << 19) 138183840Sraj#define CPU_PM_CTRL_IDMA (1 << 20) 139183840Sraj#define CPU_PM_CTRL_XOR (1 << 21) 140183840Sraj#define CPU_PM_CTRL_CRYPTO (1 << 22) 141183840Sraj#define CPU_PM_CTRL_DEVICE (1 << 23) 142196532Sraj#define CPU_PM_CTRL_USB(u) (1 << (17 + (u))) 143196532Sraj#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1) 144209131Sraj#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \ 145209131Sraj (1 - (u))) 146196532Sraj#else 147196532Sraj#define CPU_PM_CTRL_CRYPTO (CPU_PM_CTRL_NONE) 148196532Sraj#define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE) 149196532Sraj#define CPU_PM_CTRL_XOR (CPU_PM_CTRL_NONE) 150196532Sraj#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_NONE) 151196532Sraj#define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_NONE) 152209131Sraj#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_NONE) 153183840Sraj#endif 154183840Sraj 155183840Sraj/* 156183840Sraj * Timers 157183840Sraj */ 158183840Sraj#define CPU_TIMER_CONTROL 0x0 159183840Sraj#define CPU_TIMER0_EN 0x00000001 160183840Sraj#define CPU_TIMER0_AUTO 0x00000002 161183840Sraj#define CPU_TIMER1_EN 0x00000004 162183840Sraj#define CPU_TIMER1_AUTO 0x00000008 163183840Sraj#define CPU_TIMER_WD_EN 0x00000010 164183840Sraj#define CPU_TIMER_WD_AUTO 0x00000020 165183840Sraj#define CPU_TIMER0_REL 0x10 166183840Sraj#define CPU_TIMER0 0x14 167183840Sraj 168183840Sraj/* 169194845Sraj * SATA 170194845Sraj */ 171194845Sraj#define SATA_CHAN_NUM 2 172194845Sraj 173194845Sraj#define EDMA_REGISTERS_OFFSET 0x2000 174194845Sraj#define EDMA_REGISTERS_SIZE 0x2000 175194845Sraj#define SATA_EDMA_BASE(ch) (EDMA_REGISTERS_OFFSET + \ 176194845Sraj ((ch) * EDMA_REGISTERS_SIZE)) 177194845Sraj 178194845Sraj/* SATAHC registers */ 179194845Sraj#define SATA_CR 0x000 /* Configuration Reg. */ 180194845Sraj#define SATA_CR_NODMABS (1 << 8) 181194845Sraj#define SATA_CR_NOEDMABS (1 << 9) 182194845Sraj#define SATA_CR_NOPRDPBS (1 << 10) 183194845Sraj#define SATA_CR_COALDIS(ch) (1 << (24 + ch)) 184194845Sraj 185194845Sraj#define SATA_ICR 0x014 /* Interrupt Cause Reg. */ 186194845Sraj#define SATA_ICR_DMADONE(ch) (1 << (ch)) 187194845Sraj#define SATA_ICR_COAL (1 << 4) 188194845Sraj#define SATA_ICR_DEV(ch) (1 << (8 + ch)) 189194845Sraj 190194845Sraj#define SATA_MICR 0x020 /* Main Interrupt Cause Reg. */ 191194845Sraj#define SATA_MICR_ERR(ch) (1 << (2 * ch)) 192194845Sraj#define SATA_MICR_DONE(ch) (1 << ((2 * ch) + 1)) 193194845Sraj#define SATA_MICR_DMADONE(ch) (1 << (4 + ch)) 194194845Sraj#define SATA_MICR_COAL (1 << 8) 195194845Sraj 196194845Sraj#define SATA_MIMR 0x024 /* Main Interrupt Mask Reg. */ 197194845Sraj 198194845Sraj/* Shadow registers */ 199194845Sraj#define SATA_SHADOWR_BASE(ch) (SATA_EDMA_BASE(ch) + 0x100) 200194845Sraj#define SATA_SHADOWR_CONTROL(ch) (SATA_EDMA_BASE(ch) + 0x120) 201194845Sraj 202194845Sraj/* SATA registers */ 203194845Sraj#define SATA_SATA_SSTATUS(ch) (SATA_EDMA_BASE(ch) + 0x300) 204194845Sraj#define SATA_SATA_SERROR(ch) (SATA_EDMA_BASE(ch) + 0x304) 205194845Sraj#define SATA_SATA_SCONTROL(ch) (SATA_EDMA_BASE(ch) + 0x308) 206194845Sraj#define SATA_SATA_FISICR(ch) (SATA_EDMA_BASE(ch) + 0x364) 207194845Sraj 208194845Sraj/* EDMA registers */ 209194845Sraj#define SATA_EDMA_CFG(ch) (SATA_EDMA_BASE(ch) + 0x000) 210194845Sraj#define SATA_EDMA_CFG_QL128 (1 << 19) 211194845Sraj#define SATA_EDMA_CFG_HQCACHE (1 << 22) 212194845Sraj 213194845Sraj#define SATA_EDMA_IECR(ch) (SATA_EDMA_BASE(ch) + 0x008) 214194845Sraj 215194845Sraj#define SATA_EDMA_IEMR(ch) (SATA_EDMA_BASE(ch) + 0x00C) 216194845Sraj#define SATA_EDMA_REQBAHR(ch) (SATA_EDMA_BASE(ch) + 0x010) 217194845Sraj#define SATA_EDMA_REQIPR(ch) (SATA_EDMA_BASE(ch) + 0x014) 218194845Sraj#define SATA_EDMA_REQOPR(ch) (SATA_EDMA_BASE(ch) + 0x018) 219194845Sraj#define SATA_EDMA_RESBAHR(ch) (SATA_EDMA_BASE(ch) + 0x01C) 220194845Sraj#define SATA_EDMA_RESIPR(ch) (SATA_EDMA_BASE(ch) + 0x020) 221194845Sraj#define SATA_EDMA_RESOPR(ch) (SATA_EDMA_BASE(ch) + 0x024) 222194845Sraj 223194845Sraj#define SATA_EDMA_CMD(ch) (SATA_EDMA_BASE(ch) + 0x028) 224194845Sraj#define SATA_EDMA_CMD_ENABLE (1 << 0) 225194845Sraj#define SATA_EDMA_CMD_DISABLE (1 << 1) 226194845Sraj#define SATA_EDMA_CMD_RESET (1 << 2) 227194845Sraj 228194845Sraj#define SATA_EDMA_STATUS(ch) (SATA_EDMA_BASE(ch) + 0x030) 229194845Sraj#define SATA_EDMA_STATUS_IDLE (1 << 7) 230194845Sraj 231194845Sraj/* Offset to extract input slot from REQIPR register */ 232194845Sraj#define SATA_EDMA_REQIS_OFS 5 233194845Sraj 234194845Sraj/* Offset to extract input slot from RESOPR register */ 235194845Sraj#define SATA_EDMA_RESOS_OFS 3 236194845Sraj 237194845Sraj/* 238183840Sraj * GPIO 239183840Sraj */ 240183840Sraj#define GPIO_DATA_OUT 0x00 241183840Sraj#define GPIO_DATA_OUT_EN_CTRL 0x04 242183840Sraj#define GPIO_BLINK_EN 0x08 243183840Sraj#define GPIO_DATA_IN_POLAR 0x0c 244183840Sraj#define GPIO_DATA_IN 0x10 245183840Sraj#define GPIO_INT_CAUSE 0x14 246183840Sraj#define GPIO_INT_EDGE_MASK 0x18 247183840Sraj#define GPIO_INT_LEV_MASK 0x1c 248183840Sraj 249183840Sraj#define GPIO_HI_DATA_OUT 0x40 250183840Sraj#define GPIO_HI_DATA_OUT_EN_CTRL 0x44 251183840Sraj#define GPIO_HI_BLINK_EN 0x48 252183840Sraj#define GPIO_HI_DATA_IN_POLAR 0x4c 253183840Sraj#define GPIO_HI_DATA_IN 0x50 254183840Sraj#define GPIO_HI_INT_CAUSE 0x54 255183840Sraj#define GPIO_HI_INT_EDGE_MASK 0x58 256183840Sraj#define GPIO_HI_INT_LEV_MASK 0x5c 257183840Sraj 258183840Sraj#define GPIO(n) (1 << (n)) 259183840Sraj#define MV_GPIO_MAX_NPINS 64 260183840Sraj 261209131Sraj#define MV_GPIO_IN_NONE 0x0 262209131Sraj#define MV_GPIO_IN_POL_LOW (1 << 16) 263209131Sraj#define MV_GPIO_IN_IRQ_EDGE (2 << 16) 264209131Sraj#define MV_GPIO_IN_IRQ_LEVEL (4 << 16) 265209131Sraj#define MV_GPIO_OUT_NONE 0x0 266209131Sraj#define MV_GPIO_OUT_BLINK 0x1 267209131Sraj#define MV_GPIO_OUT_OPEN_DRAIN 0x2 268209131Sraj#define MV_GPIO_OUT_OPEN_SRC 0x4 269183840Sraj 270183840Sraj#define IS_GPIO_IRQ(irq) ((irq) >= NIRQ && (irq) < NIRQ + MV_GPIO_MAX_NPINS) 271183840Sraj#define GPIO2IRQ(gpio) ((gpio) + NIRQ) 272183840Sraj#define IRQ2GPIO(irq) ((irq) - NIRQ) 273183840Sraj 274183840Sraj/* 275183840Sraj * MPP 276183840Sraj */ 277186899Sraj#if defined(SOC_MV_ORION) 278183840Sraj#define MPP_CONTROL0 0x00 279183840Sraj#define MPP_CONTROL1 0x04 280183840Sraj#define MPP_CONTROL2 0x50 281186899Sraj#elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) 282186899Sraj#define MPP_CONTROL0 0x00 283186899Sraj#define MPP_CONTROL1 0x04 284186899Sraj#define MPP_CONTROL2 0x08 285186899Sraj#define MPP_CONTROL3 0x0C 286186899Sraj#define MPP_CONTROL4 0x10 287186899Sraj#define MPP_CONTROL5 0x14 288186899Sraj#define MPP_CONTROL6 0x18 289186899Sraj#else 290186899Sraj#error SOC_MV_XX not defined 291186899Sraj#endif 292183840Sraj 293183840Sraj#if defined(SOC_MV_ORION) 294183840Sraj#define SAMPLE_AT_RESET 0x10 295186899Sraj#elif defined(SOC_MV_KIRKWOOD) 296183840Sraj#define SAMPLE_AT_RESET 0x30 297186899Sraj#elif defined(SOC_MV_DISCOVERY) 298186899Sraj#define SAMPLE_AT_RESET_LO 0x30 299186899Sraj#define SAMPLE_AT_RESET_HI 0x34 300183840Sraj#else 301183840Sraj#error SOC_MV_XX not defined 302183840Sraj#endif 303183840Sraj 304183840Sraj/* 305183840Sraj * Clocks 306183840Sraj */ 307186899Sraj#if defined(SOC_MV_ORION) 308186899Sraj#define TCLK_MASK 0x00000300 309186899Sraj#define TCLK_SHIFT 0x08 310186899Sraj#elif defined(SOC_MV_DISCOVERY) 311186899Sraj#define TCLK_MASK 0x00000180 312186899Sraj#define TCLK_SHIFT 0x07 313183840Sraj#endif 314183840Sraj 315183840Sraj#define TCLK_100MHZ 100000000 316183840Sraj#define TCLK_125MHZ 125000000 317183840Sraj#define TCLK_133MHZ 133333333 318183840Sraj#define TCLK_150MHZ 150000000 319183840Sraj#define TCLK_166MHZ 166666667 320183840Sraj#define TCLK_200MHZ 200000000 321183840Sraj 322183840Sraj/* 323183840Sraj * Chip ID 324183840Sraj */ 325191140Sraj#define MV_DEV_88F5181 0x5181 326191140Sraj#define MV_DEV_88F5182 0x5182 327191140Sraj#define MV_DEV_88F5281 0x5281 328191140Sraj#define MV_DEV_88F6281 0x6281 329238873Shrs#define MV_DEV_88F6282 0x6282 330191140Sraj#define MV_DEV_MV78100_Z0 0x6381 331191140Sraj#define MV_DEV_MV78100 0x7810 332183840Sraj 333183840Sraj#endif /* _MVREG_H_ */ 334