mvreg.h revision 191140
1183840Sraj/*- 2183840Sraj * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD. 3183840Sraj * All rights reserved. 4183840Sraj * 5183840Sraj * Developed by Semihalf. 6183840Sraj * 7183840Sraj * Redistribution and use in source and binary forms, with or without 8183840Sraj * modification, are permitted provided that the following conditions 9183840Sraj * are met: 10183840Sraj * 1. Redistributions of source code must retain the above copyright 11183840Sraj * notice, this list of conditions and the following disclaimer. 12183840Sraj * 2. Redistributions in binary form must reproduce the above copyright 13183840Sraj * notice, this list of conditions and the following disclaimer in the 14183840Sraj * documentation and/or other materials provided with the distribution. 15183840Sraj * 3. Neither the name of MARVELL nor the names of contributors 16183840Sraj * may be used to endorse or promote products derived from this software 17183840Sraj * without specific prior written permission. 18183840Sraj * 19183840Sraj * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20183840Sraj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21183840Sraj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22183840Sraj * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23183840Sraj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24183840Sraj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25183840Sraj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26183840Sraj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27183840Sraj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28183840Sraj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29183840Sraj * SUCH DAMAGE. 30183840Sraj * 31183840Sraj * $FreeBSD: head/sys/arm/mv/mvreg.h 191140 2009-04-16 11:20:18Z raj $ 32183840Sraj */ 33183840Sraj 34183840Sraj#ifndef _MVREG_H_ 35183840Sraj#define _MVREG_H_ 36183840Sraj 37183840Sraj#include <machine/intr.h> 38183840Sraj 39183840Sraj/* 40183840Sraj * Physical addresses of integrated SoC peripherals 41183840Sraj */ 42183840Sraj#define MV_PHYS_BASE 0xF1000000 43183840Sraj#define MV_SIZE 0x100000 44183840Sraj 45183840Sraj/* 46183840Sraj * Decode windows addresses (physical) 47183840Sraj */ 48183840Sraj#define MV_PCIE_IO_PHYS_BASE (MV_PHYS_BASE + MV_SIZE) 49183840Sraj#define MV_PCIE_IO_BASE MV_PCIE_IO_PHYS_BASE 50183840Sraj#define MV_PCIE_IO_SIZE (1024 * 1024) 51183840Sraj#define MV_PCI_IO_PHYS_BASE (MV_PCIE_IO_PHYS_BASE + MV_PCIE_IO_SIZE) 52183840Sraj#define MV_PCI_IO_BASE MV_PCI_IO_PHYS_BASE 53183840Sraj#define MV_PCI_IO_SIZE (1024 * 1024) 54183840Sraj 55183840Sraj#define MV_PCIE_MEM_PHYS_BASE (MV_PCI_IO_PHYS_BASE + MV_PCI_IO_SIZE) 56183840Sraj#define MV_PCIE_MEM_BASE MV_PCIE_MEM_PHYS_BASE 57183840Sraj#define MV_PCIE_MEM_SIZE (64 * 1024 * 1024) 58183840Sraj#define MV_PCI_MEM_PHYS_BASE (MV_PCIE_MEM_PHYS_BASE + MV_PCIE_MEM_SIZE) 59183840Sraj#define MV_PCI_MEM_BASE MV_PCI_MEM_PHYS_BASE 60183840Sraj#define MV_PCI_MEM_SIZE (64 * 1024 * 1024) 61183840Sraj 62183840Sraj/* XXX DEV_BOOT, CSx are board specific, should be defined per platform */ 63183840Sraj 64183840Sraj/* 512KB NOR FLASH */ 65183840Sraj#define MV_DEV_BOOT_PHYS_BASE (MV_PCI_MEM_PHYS_BASE + MV_PCI_MEM_SIZE) 66183840Sraj#define MV_DEV_BOOT_SIZE (512 * 1024) 67183840Sraj/* CS0: 7-seg LED */ 68183840Sraj#define MV_DEV_CS0_PHYS_BASE 0xFA000000 69183840Sraj#define MV_DEV_CS0_SIZE (1024 * 1024) /* XXX u-boot has 2MB */ 70183840Sraj/* CS1: 32MB NOR FLASH */ 71183840Sraj#define MV_DEV_CS1_PHYS_BASE (MV_DEV_CS0_PHYS_BASE + MV_DEV_CS0_SIZE) 72183840Sraj#define MV_DEV_CS1_SIZE (32 * 1024 * 1024) 73183840Sraj/* CS2: 32MB NAND FLASH */ 74183840Sraj#define MV_DEV_CS2_PHYS_BASE (MV_DEV_CS1_PHYS_BASE + MV_DEV_CS1_SIZE) 75183840Sraj#define MV_DEV_CS2_SIZE 1024 /* XXX u-boot has 1MB */ 76183840Sraj 77186909Sraj#define MV_CESA_SRAM_PHYS_BASE 0xFD000000 78186909Sraj#define MV_CESA_SRAM_BASE MV_CESA_SRAM_PHYS_BASE /* VA == PA mapping */ 79186909Sraj#define MV_CESA_SRAM_SIZE (1024 * 1024) 80186909Sraj 81183840Sraj/* XXX this is probably not robust against wraparounds... */ 82186909Sraj#if ((MV_CESA_SRAM_PHYS_BASE + MV_CESA_SRAM_SIZE) > 0xFFFEFFFF) 83183840Sraj#error Devices memory layout overlaps reset vectors range! 84183840Sraj#endif 85183840Sraj 86183840Sraj/* 87183840Sraj * Integrated SoC peripherals addresses 88183840Sraj */ 89183840Sraj#define MV_BASE MV_PHYS_BASE /* VA == PA mapping */ 90183840Sraj#define MV_DDR_CADR_BASE (MV_BASE + 0x1500) 91183840Sraj#define MV_MPP_BASE (MV_BASE + 0x10000) 92183840Sraj#define MV_GPIO_BASE (MV_BASE + 0x10100) 93183840Sraj#define MV_GPIO_SIZE 0x20 94183840Sraj#define MV_RTC_BASE (MV_BASE + 0x10300) 95183840Sraj#define MV_RTC_SIZE 0x08 96183840Sraj#define MV_TWSI_BASE (MV_BASE + 0x11000) 97183840Sraj#define MV_TWSI_SIZE 0x20 98183840Sraj#define MV_UART0_BASE (MV_BASE + 0x12000) 99183840Sraj#define MV_UART1_BASE (MV_BASE + 0x12100) 100183840Sraj#define MV_UART_SIZE 0x20 101183840Sraj#define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000) 102183840Sraj#define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80) 103183840Sraj#define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x100) 104183840Sraj#define MV_IC_BASE (MV_MBUS_BRIDGE_BASE + 0x200) 105183840Sraj#define MV_IC_SIZE 0x3C 106183840Sraj#define MV_TIMERS_BASE (MV_MBUS_BRIDGE_BASE + 0x300) 107183840Sraj#define MV_TIMERS_SIZE 0x30 108183840Sraj#define MV_PCI_BASE (MV_BASE + 0x30000) 109183840Sraj#define MV_PCI_SIZE 0x2000 110186909Sraj#if defined (SOC_MV_KIRKWOOD) 111186909Sraj#define MV_CESA_BASE (MV_BASE + 0x30000) /* CESA,PCI don't coexist */ 112186909Sraj#elif defined (SOC_MV_ORION) || defined(SOC_MV_DISCOVERY) 113186909Sraj#define MV_CESA_BASE (MV_BASE + 0x90000) 114186909Sraj#endif 115186909Sraj#define MV_CESA_SIZE 0x10000 116183840Sraj#define MV_PCIE_BASE (MV_BASE + 0x40000) 117183840Sraj#define MV_PCIE_SIZE 0x2000 118185089Sraj 119185089Sraj#define MV_PCIE00_BASE (MV_PCIE_BASE + 0x00000) 120185089Sraj#define MV_PCIE01_BASE (MV_PCIE_BASE + 0x04000) 121185089Sraj#define MV_PCIE02_BASE (MV_PCIE_BASE + 0x08000) 122185089Sraj#define MV_PCIE03_BASE (MV_PCIE_BASE + 0x0C000) 123185089Sraj#define MV_PCIE10_BASE (MV_PCIE_BASE + 0x40000) 124185089Sraj#define MV_PCIE11_BASE (MV_PCIE_BASE + 0x44000) 125185089Sraj#define MV_PCIE12_BASE (MV_PCIE_BASE + 0x48000) 126185089Sraj#define MV_PCIE13_BASE (MV_PCIE_BASE + 0x4C000) 127185089Sraj 128183840Sraj#define MV_USB0_BASE (MV_BASE + 0x50000) 129183840Sraj#define MV_USB1_BASE (MV_USB0_BASE + 0x1000) 130183840Sraj#define MV_USB2_BASE (MV_USB0_BASE + 0x2000) 131183840Sraj#define MV_USB_SIZE 0x1000 132183840Sraj#define MV_USB_HOST_OFST 0x0100 /* EHCI HC regs start at this offset within USB range */ 133183840Sraj#define MV_USB_AWR_BASE (MV_USB0_BASE + 0x320) 134183840Sraj#define MV_IDMA_BASE (MV_BASE + 0x60000) 135183840Sraj#define MV_IDMA_SIZE 0x1000 136183840Sraj#define MV_XOR_BASE (MV_BASE + 0x60000) 137183840Sraj#define MV_XOR_SIZE 0x1000 138183840Sraj#define MV_ETH0_BASE (MV_BASE + 0x72000) 139183840Sraj#define MV_ETH1_BASE (MV_BASE + 0x76000) 140183840Sraj#define MV_ETH_SIZE 0x2000 141186909Sraj#if defined(SOC_MV_ORION) || defined(SOC_MV_KIRKWOOD) 142186909Sraj#define MV_SATAHC_BASE (MV_BASE + 0x80000) 143186909Sraj#define MV_SATAHC_SIZE 0x6000 144186909Sraj#elif defined(SOC_MV_DISCOVERY) 145186909Sraj#define MV_SATAHC_BASE (MV_BASE + 0xA0000) 146186909Sraj#define MV_SATAHC_SIZE 0x6000 147186909Sraj#endif 148183840Sraj 149183840Sraj#define MV_DEV_CS0_BASE MV_DEV_CS0_PHYS_BASE 150183840Sraj 151183840Sraj/* 152183840Sraj * Interrupt sources 153183840Sraj */ 154183840Sraj#if defined(SOC_MV_ORION) 155183840Sraj 156183840Sraj#define MV_INT_BRIDGE 0 /* AHB-MBus Bridge Interrupt */ 157183840Sraj#define MV_INT_UART0 3 /* UART0 Interrupt */ 158183840Sraj#define MV_INT_UART1 4 159183840Sraj#define MV_INT_GPIO7_0 6 /* GPIO[7:0] Interrupt */ 160183840Sraj#define MV_INT_GPIO15_8 7 /* GPIO[15:8] Interrupt */ 161183840Sraj#define MV_INT_GPIO23_16 8 /* GPIO[23:16] Interrupt */ 162183840Sraj#define MV_INT_GPIO31_24 9 /* GPIO[31:24] Interrupt */ 163183840Sraj#define MV_INT_PEX0_ERR 10 /* PCI Express Error */ 164183840Sraj#define MV_INT_PEX0 11 /* PCI Express INTA,B,C,D Message */ 165183840Sraj#define MV_INT_PCI_ERR 15 /* PCI Error */ 166183840Sraj#define MV_INT_USB_BERR 16 /* USB Bridge Error */ 167183840Sraj#define MV_INT_USB_CI 17 /* USB Controller interrupt */ 168183840Sraj#define MV_INT_GBERX 18 /* GbE receive interrupt */ 169183840Sraj#define MV_INT_GBETX 19 /* GbE transmit interrupt */ 170183840Sraj#define MV_INT_GBEMISC 20 /* GbE misc. interrupt */ 171183840Sraj#define MV_INT_GBESUM 21 /* GbE summary interrupt */ 172183840Sraj#define MV_INT_GBEERR 22 /* GbE error interrupt */ 173183840Sraj#define MV_INT_IDMA_ERR 23 /* DMA error interrupt */ 174183840Sraj#define MV_INT_IDMA0 24 /* IDMA chan. 0 completion interrupt */ 175183840Sraj#define MV_INT_IDMA1 25 /* IDMA chan. 1 completion interrupt */ 176183840Sraj#define MV_INT_IDMA2 26 /* IDMA chan. 2 completion interrupt */ 177183840Sraj#define MV_INT_IDMA3 27 /* IDMA chan. 3 completion interrupt */ 178183840Sraj#define MV_INT_SATA 29 /* Serial-ATA Interrupt */ 179183840Sraj 180183840Sraj#elif defined(SOC_MV_KIRKWOOD) 181183840Sraj 182183840Sraj#define MV_INT_BRIDGE 1 /* AHB-MBus Bridge Interrupt */ 183183840Sraj#define MV_INT_XOR0_CHAN0 5 /* XOR engine 0 channel 0 Interrupt */ 184183840Sraj#define MV_INT_XOR0_CHAN1 6 /* XOR engine 0 channel 1 Interrupt */ 185183840Sraj#define MV_INT_XOR1_CHAN0 7 /* XOR engine 1 channel 0 Interrupt */ 186183840Sraj#define MV_INT_XOR1_CHAN1 8 /* XOR engine 1 channel 1 Interrupt */ 187183840Sraj#define MV_INT_PEX0 9 /* PCI Express INTA,B,C,D Message */ 188183840Sraj#define MV_INT_GBESUM 11 /* GbE0 summary interrupt */ 189183840Sraj#define MV_INT_GBERX 12 /* GbE0 receive interrupt */ 190183840Sraj#define MV_INT_GBETX 13 /* GbE0 transmit interrupt */ 191183840Sraj#define MV_INT_GBEMISC 14 /* GbE0 misc. interrupt */ 192183840Sraj#define MV_INT_GBE1SUM 15 /* GbE1 summary interrupt */ 193183840Sraj#define MV_INT_GBE1RX 16 /* GbE1 receive interrupt */ 194183840Sraj#define MV_INT_GBE1TX 17 /* GbE1 transmit interrupt */ 195183840Sraj#define MV_INT_GBE1MISC 18 /* GbE1 misc. interrupt */ 196183840Sraj#define MV_INT_USB_CI 19 /* USB Controller interrupt */ 197183840Sraj#define MV_INT_SATA 21 /* Serial-ATA Interrupt */ 198186909Sraj#define MV_INT_CESA 22 /* Security engine completion int. */ 199183840Sraj#define MV_INT_IDMA_ERR 23 /* DMA error interrupt */ 200183840Sraj#define MV_INT_UART0 33 /* UART0 Interrupt */ 201183840Sraj#define MV_INT_UART1 34 202183840Sraj#define MV_INT_GPIO7_0 35 /* GPIO[7:0] Interrupt */ 203183840Sraj#define MV_INT_GPIO15_8 36 /* GPIO[15:8] Interrupt */ 204183840Sraj#define MV_INT_GPIO23_16 37 /* GPIO[23:16] Interrupt */ 205183840Sraj#define MV_INT_GPIO31_24 38 /* GPIO[31:24] Interrupt */ 206183840Sraj#define MV_INT_GPIOHI7_0 39 /* GPIOHI[7:0] Interrupt */ 207183840Sraj#define MV_INT_GPIOHI15_8 40 /* GPIOHI[15:8] Interrupt */ 208183840Sraj#define MV_INT_GPIOHI23_16 41 /* GPIOHI[23:16] Interrupt */ 209183840Sraj#define MV_INT_XOR0_ERR 42 /* XOR engine 0 error Interrupt */ 210183840Sraj#define MV_INT_XOR1_ERR 43 /* XOR engine 1 error Interrupt */ 211183840Sraj#define MV_INT_PEX0_ERR 44 /* PCI Express Error */ 212183840Sraj#define MV_INT_GBEERR 46 /* GbE0 error interrupt */ 213183840Sraj#define MV_INT_GBE1ERR 47 /* GbE1 error interrupt */ 214183840Sraj#define MV_INT_USB_BERR 48 /* USB Bridge Error */ 215183840Sraj 216183840Sraj#elif defined(SOC_MV_DISCOVERY) 217183840Sraj 218183840Sraj#define MV_INT_ERRSUM 0 /* Summary of error interrupts */ 219183840Sraj#define MV_INT_SPI 1 /* SPI interrupt */ 220183840Sraj#define MV_INT_TWSI0 2 /* TWSI0 interrupt */ 221183840Sraj#define MV_INT_TWSI1 3 /* TWSI1 interrupt */ 222183840Sraj#define MV_INT_IDMA0 4 /* IDMA Channel0 completion */ 223183840Sraj#define MV_INT_IDMA1 5 /* IDMA Channel0 completion */ 224183840Sraj#define MV_INT_IDMA2 6 /* IDMA Channel0 completion */ 225183840Sraj#define MV_INT_IDMA3 7 /* IDMA Channel0 completion */ 226183840Sraj#define MV_INT_TIMER0 8 /* Timer0 interrupt */ 227183840Sraj#define MV_INT_TIMER1 9 /* Timer1 interrupt */ 228183840Sraj#define MV_INT_TIMER2 10 /* Timer2 interrupt */ 229183840Sraj#define MV_INT_TIMER3 11 /* Timer3 interrupt */ 230183840Sraj#define MV_INT_UART0 12 /* UART0 interrupt */ 231183840Sraj#define MV_INT_UART1 13 /* UART1 interrupt */ 232183840Sraj#define MV_INT_UART2 14 /* UART2 interrupt */ 233183840Sraj#define MV_INT_UART3 15 /* UART3 interrupt */ 234183840Sraj#define MV_INT_USB0 16 /* USB0 interrupt */ 235183840Sraj#define MV_INT_USB1 17 /* USB1 interrupt */ 236183840Sraj#define MV_INT_USB2 18 /* USB2 interrupt */ 237186909Sraj#define MV_INT_CESA 19 /* Crypto engine completion interrupt */ 238183840Sraj#define MV_INT_XOR0 22 /* XOR engine 0 completion interrupt */ 239183840Sraj#define MV_INT_XOR1 23 /* XOR engine 1 completion interrupt */ 240183840Sraj#define MV_INT_SATA 26 /* SATA interrupt */ 241183840Sraj#define MV_INT_PEX00 32 /* PCI Express port 0.0 INTA/B/C/D */ 242183840Sraj#define MV_INT_PEX01 33 /* PCI Express port 0.1 INTA/B/C/D */ 243183840Sraj#define MV_INT_PEX02 34 /* PCI Express port 0.2 INTA/B/C/D */ 244183840Sraj#define MV_INT_PEX03 35 /* PCI Express port 0.3 INTA/B/C/D */ 245183840Sraj#define MV_INT_PEX10 36 /* PCI Express port 1.0 INTA/B/C/D */ 246183840Sraj#define MV_INT_PEX11 37 /* PCI Express port 1.1 INTA/B/C/D */ 247183840Sraj#define MV_INT_PEX12 38 /* PCI Express port 1.2 INTA/B/C/D */ 248183840Sraj#define MV_INT_PEX13 39 /* PCI Express port 1.3 INTA/B/C/D */ 249183840Sraj#define MV_INT_GBESUM 40 /* Gigabit Ethernet Port 0 summary */ 250183840Sraj#define MV_INT_GBERX 41 /* Gigabit Ethernet Port 0 Rx summary */ 251183840Sraj#define MV_INT_GBETX 42 /* Gigabit Ethernet Port 0 Tx summary */ 252183840Sraj#define MV_INT_GBEMISC 43 /* Gigabit Ethernet Port 0 Misc summ. */ 253183840Sraj#define MV_INT_GBE1SUM 44 /* Gigabit Ethernet Port 1 summary */ 254183840Sraj#define MV_INT_GBE1RX 45 /* Gigabit Ethernet Port 1 Rx summary */ 255183840Sraj#define MV_INT_GBE1TX 46 /* Gigabit Ethernet Port 1 Tx summary */ 256183840Sraj#define MV_INT_GBE1MISC 47 /* Gigabit Ethernet Port 1 Misc summ. */ 257183840Sraj#define MV_INT_GPIO7_0 56 /* GPIO[7:0] Interrupt */ 258183840Sraj#define MV_INT_GPIO15_8 57 /* GPIO[15:8] Interrupt */ 259183840Sraj#define MV_INT_GPIO23_16 58 /* GPIO[23:16] Interrupt */ 260183840Sraj#define MV_INT_GPIO31_24 59 /* GPIO[31:24] Interrupt */ 261183840Sraj#define MV_INT_DB_IN 60 /* Inbound Doorbell Cause reg Summary */ 262183840Sraj#define MV_INT_DB_OUT 61 /* Outbound Doorbell Cause reg Summ. */ 263183840Sraj#define MV_INT_CRYPT_ERR 64 /* Crypto engine error */ 264183840Sraj#define MV_INT_DEV_ERR 65 /* Device bus error */ 265183840Sraj#define MV_INT_IDMA_ERR 66 /* DMA error */ 266183840Sraj#define MV_INT_CPU_ERR 67 /* CPU error */ 267183840Sraj#define MV_INT_PEX0_ERR 68 /* PCI-Express port0 error */ 268183840Sraj#define MV_INT_PEX1_ERR 69 /* PCI-Express port1 error */ 269183840Sraj#define MV_INT_GBE_ERR 70 /* Gigabit Ethernet error */ 270183840Sraj#define MV_INT_USB_ERR 72 /* USB error */ 271183840Sraj#define MV_INT_DRAM_ERR 73 /* DRAM ECC error */ 272183840Sraj#define MV_INT_XOR_ERR 74 /* XOR engine error */ 273183840Sraj#define MV_INT_WD 79 /* WD Timer interrupt */ 274183840Sraj 275183840Sraj#endif /* SOC_MV_ORION */ 276183840Sraj 277183840Sraj#define BRIDGE_IRQ_CAUSE 0x10 278183840Sraj#define BRIGDE_IRQ_MASK 0x14 279183840Sraj 280183840Sraj#if defined(SOC_MV_DISCOVERY) 281183840Sraj#define IRQ_CAUSE_ERROR 0x0 282183840Sraj#define IRQ_CAUSE 0x4 283183840Sraj#define IRQ_CAUSE_HI 0x8 284183840Sraj#define IRQ_MASK_ERROR 0xC 285183840Sraj#define IRQ_MASK 0x10 286183840Sraj#define IRQ_MASK_HI 0x14 287183840Sraj#define IRQ_CAUSE_SELECT 0x18 288183840Sraj#define FIQ_MASK_ERROR 0x1C 289183840Sraj#define FIQ_MASK 0x20 290183840Sraj#define FIQ_MASK_HI 0x24 291183840Sraj#define FIQ_CAUSE_SELECT 0x28 292183840Sraj#define ENDPOINT_IRQ_MASK_ERROR 0x2C 293183840Sraj#define ENDPOINT_IRQ_MASK 0x30 294183840Sraj#define ENDPOINT_IRQ_MASK_HI 0x34 295183840Sraj#define ENDPOINT_IRQ_CAUSE_SELECT 0x38 296183840Sraj#else /* !SOC_MV_DISCOVERY */ 297183840Sraj#define IRQ_CAUSE 0x0 298183840Sraj#define IRQ_MASK 0x4 299183840Sraj#define FIQ_MASK 0x8 300183840Sraj#define ENDPOINT_IRQ_MASK 0xC 301183840Sraj#define IRQ_CAUSE_HI 0x10 302183840Sraj#define IRQ_MASK_HI 0x14 303183840Sraj#define FIQ_MASK_HI 0x18 304183840Sraj#define ENDPOINT_IRQ_MASK_HI 0x1C 305183840Sraj#define IRQ_CAUSE_ERROR (-1) /* Fake defines for unified */ 306183840Sraj#define IRQ_MASK_ERROR (-1) /* interrupt controller code */ 307183840Sraj#endif 308183840Sraj 309183840Sraj#define BRIDGE_IRQ_CAUSE 0x10 310183840Sraj#define IRQ_CPU_SELF 0x00000001 311183840Sraj#define IRQ_TIMER0 0x00000002 312183840Sraj#define IRQ_TIMER1 0x00000004 313183840Sraj#define IRQ_TIMER_WD 0x00000008 314183840Sraj 315183840Sraj#define BRIDGE_IRQ_MASK 0x14 316183840Sraj#define IRQ_CPU_MASK 0x00000001 317183840Sraj#define IRQ_TIMER0_MASK 0x00000002 318183840Sraj#define IRQ_TIMER1_MASK 0x00000004 319183840Sraj#define IRQ_TIMER_WD_MASK 0x00000008 320183840Sraj 321183840Sraj/* 322183840Sraj * System reset 323183840Sraj */ 324183840Sraj#define RSTOUTn_MASK 0x8 325183840Sraj#define WD_RST_OUT_EN 0x00000002 326183840Sraj#define SOFT_RST_OUT_EN 0x00000004 327183840Sraj#define SYSTEM_SOFT_RESET 0xc 328183840Sraj#define SYS_SOFT_RST 0x00000001 329183840Sraj 330183840Sraj/* 331183840Sraj * Power Control 332183840Sraj */ 333183840Sraj#define CPU_PM_CTRL 0x1C 334183840Sraj#define CPU_PM_CTRL_NONE 0 335183840Sraj 336183840Sraj#if defined(SOC_MV_KIRKWOOD) 337183840Sraj#define CPU_PM_CTRL_GE0 (1 << 0) 338183840Sraj#define CPU_PM_CTRL_PEX0_PHY (1 << 1) 339183840Sraj#define CPU_PM_CTRL_PEX0 (1 << 2) 340183840Sraj#define CPU_PM_CTRL_USB0 (1 << 3) 341183840Sraj#define CPU_PM_CTRL_SDIO (1 << 4) 342183840Sraj#define CPU_PM_CTRL_TSU (1 << 5) 343183840Sraj#define CPU_PM_CTRL_DUNIT (1 << 6) 344183840Sraj#define CPU_PM_CTRL_RUNIT (1 << 7) 345183840Sraj#define CPU_PM_CTRL_XOR0 (1 << 8) 346183840Sraj#define CPU_PM_CTRL_AUDIO (1 << 9) 347183840Sraj#define CPU_PM_CTRL_SATA0 (1 << 14) 348183840Sraj#define CPU_PM_CTRL_SATA1 (1 << 15) 349183840Sraj#define CPU_PM_CTRL_XOR1 (1 << 16) 350183840Sraj#define CPU_PM_CTRL_CRYPTO (1 << 17) 351183840Sraj#define CPU_PM_CTRL_GE1 (1 << 18) 352183840Sraj#define CPU_PM_CTRL_TDM (1 << 19) 353183840Sraj#elif defined(SOC_MV_DISCOVERY) 354183840Sraj#define CPU_PM_CTRL_GE0 (1 << 1) 355183840Sraj#define CPU_PM_CTRL_GE1 (1 << 2) 356183840Sraj#define CPU_PM_CTRL_PEX00 (1 << 5) 357183840Sraj#define CPU_PM_CTRL_PEX01 (1 << 6) 358183840Sraj#define CPU_PM_CTRL_PEX02 (1 << 7) 359183840Sraj#define CPU_PM_CTRL_PEX03 (1 << 8) 360183840Sraj#define CPU_PM_CTRL_PEX10 (1 << 9) 361183840Sraj#define CPU_PM_CTRL_PEX11 (1 << 10) 362183840Sraj#define CPU_PM_CTRL_PEX12 (1 << 11) 363183840Sraj#define CPU_PM_CTRL_PEX13 (1 << 12) 364183840Sraj#define CPU_PM_CTRL_SATA0_PHY (1 << 13) 365183840Sraj#define CPU_PM_CTRL_SATA0 (1 << 14) 366183840Sraj#define CPU_PM_CTRL_SATA1_PHY (1 << 15) 367183840Sraj#define CPU_PM_CTRL_SATA1 (1 << 16) 368183840Sraj#define CPU_PM_CTRL_USB0 (1 << 17) 369183840Sraj#define CPU_PM_CTRL_USB1 (1 << 18) 370183840Sraj#define CPU_PM_CTRL_USB2 (1 << 19) 371183840Sraj#define CPU_PM_CTRL_IDMA (1 << 20) 372183840Sraj#define CPU_PM_CTRL_XOR (1 << 21) 373183840Sraj#define CPU_PM_CTRL_CRYPTO (1 << 22) 374183840Sraj#define CPU_PM_CTRL_DEVICE (1 << 23) 375183840Sraj#endif 376183840Sraj 377183840Sraj/* 378183840Sraj * Timers 379183840Sraj */ 380183840Sraj#define CPU_TIMER_CONTROL 0x0 381183840Sraj#define CPU_TIMER0_EN 0x00000001 382183840Sraj#define CPU_TIMER0_AUTO 0x00000002 383183840Sraj#define CPU_TIMER1_EN 0x00000004 384183840Sraj#define CPU_TIMER1_AUTO 0x00000008 385183840Sraj#define CPU_TIMER_WD_EN 0x00000010 386183840Sraj#define CPU_TIMER_WD_AUTO 0x00000020 387183840Sraj#define CPU_TIMER0_REL 0x10 388183840Sraj#define CPU_TIMER0 0x14 389183840Sraj 390183840Sraj/* 391183840Sraj * GPIO 392183840Sraj */ 393183840Sraj#define GPIO_DATA_OUT 0x00 394183840Sraj#define GPIO_DATA_OUT_EN_CTRL 0x04 395183840Sraj#define GPIO_BLINK_EN 0x08 396183840Sraj#define GPIO_DATA_IN_POLAR 0x0c 397183840Sraj#define GPIO_DATA_IN 0x10 398183840Sraj#define GPIO_INT_CAUSE 0x14 399183840Sraj#define GPIO_INT_EDGE_MASK 0x18 400183840Sraj#define GPIO_INT_LEV_MASK 0x1c 401183840Sraj 402183840Sraj#define GPIO_HI_DATA_OUT 0x40 403183840Sraj#define GPIO_HI_DATA_OUT_EN_CTRL 0x44 404183840Sraj#define GPIO_HI_BLINK_EN 0x48 405183840Sraj#define GPIO_HI_DATA_IN_POLAR 0x4c 406183840Sraj#define GPIO_HI_DATA_IN 0x50 407183840Sraj#define GPIO_HI_INT_CAUSE 0x54 408183840Sraj#define GPIO_HI_INT_EDGE_MASK 0x58 409183840Sraj#define GPIO_HI_INT_LEV_MASK 0x5c 410183840Sraj 411183840Sraj#define GPIO(n) (1 << (n)) 412183840Sraj#define MV_GPIO_MAX_NPINS 64 413183840Sraj 414183840Sraj#define MV_GPIO_BLINK 0x1 415186909Sraj#define MV_GPIO_POLAR_LOW 0x2 416183840Sraj#define MV_GPIO_EDGE 0x4 417183840Sraj#define MV_GPIO_LEVEL 0x8 418183840Sraj 419183840Sraj#define IS_GPIO_IRQ(irq) ((irq) >= NIRQ && (irq) < NIRQ + MV_GPIO_MAX_NPINS) 420183840Sraj#define GPIO2IRQ(gpio) ((gpio) + NIRQ) 421183840Sraj#define IRQ2GPIO(irq) ((irq) - NIRQ) 422183840Sraj 423183840Sraj/* 424183840Sraj * MPP 425183840Sraj */ 426186899Sraj#if defined(SOC_MV_ORION) 427183840Sraj#define MPP_CONTROL0 0x00 428183840Sraj#define MPP_CONTROL1 0x04 429183840Sraj#define MPP_CONTROL2 0x50 430186899Sraj#elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) 431186899Sraj#define MPP_CONTROL0 0x00 432186899Sraj#define MPP_CONTROL1 0x04 433186899Sraj#define MPP_CONTROL2 0x08 434186899Sraj#define MPP_CONTROL3 0x0C 435186899Sraj#define MPP_CONTROL4 0x10 436186899Sraj#define MPP_CONTROL5 0x14 437186899Sraj#define MPP_CONTROL6 0x18 438186899Sraj#else 439186899Sraj#error SOC_MV_XX not defined 440186899Sraj#endif 441183840Sraj 442183840Sraj#if defined(SOC_MV_ORION) 443183840Sraj#define SAMPLE_AT_RESET 0x10 444186899Sraj#elif defined(SOC_MV_KIRKWOOD) 445183840Sraj#define SAMPLE_AT_RESET 0x30 446186899Sraj#elif defined(SOC_MV_DISCOVERY) 447186899Sraj#define SAMPLE_AT_RESET_LO 0x30 448186899Sraj#define SAMPLE_AT_RESET_HI 0x34 449183840Sraj#else 450183840Sraj#error SOC_MV_XX not defined 451183840Sraj#endif 452183840Sraj 453183840Sraj/* 454183840Sraj * Clocks 455183840Sraj */ 456186899Sraj#if defined(SOC_MV_ORION) 457186899Sraj#define TCLK_MASK 0x00000300 458186899Sraj#define TCLK_SHIFT 0x08 459186899Sraj#elif defined(SOC_MV_DISCOVERY) 460186899Sraj#define TCLK_MASK 0x00000180 461186899Sraj#define TCLK_SHIFT 0x07 462183840Sraj#endif 463183840Sraj 464183840Sraj#define TCLK_100MHZ 100000000 465183840Sraj#define TCLK_125MHZ 125000000 466183840Sraj#define TCLK_133MHZ 133333333 467183840Sraj#define TCLK_150MHZ 150000000 468183840Sraj#define TCLK_166MHZ 166666667 469183840Sraj#define TCLK_200MHZ 200000000 470183840Sraj 471183840Sraj/* 472183840Sraj * Chip ID 473183840Sraj */ 474191140Sraj#define MV_DEV_88F5181 0x5181 475191140Sraj#define MV_DEV_88F5182 0x5182 476191140Sraj#define MV_DEV_88F5281 0x5281 477191140Sraj#define MV_DEV_88F6281 0x6281 478191140Sraj#define MV_DEV_MV78100_Z0 0x6381 479191140Sraj#define MV_DEV_MV78100 0x7810 480183840Sraj 481183840Sraj/* 482183840Sraj * Decode windows definitions and macros 483183840Sraj */ 484183840Sraj#define MV_WIN_CPU_CTRL(n) (0x10 * (n) + (((n) < 8) ? 0x000 : 0x880)) 485183840Sraj#define MV_WIN_CPU_BASE(n) (0x10 * (n) + (((n) < 8) ? 0x004 : 0x884)) 486183840Sraj#define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + (((n) < 8) ? 0x008 : 0x888)) 487183840Sraj#define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + (((n) < 8) ? 0x00C : 0x88C)) 488183840Sraj#if defined(SOC_MV_DISCOVERY) 489183840Sraj#define MV_WIN_CPU_MAX 14 490183840Sraj#else 491183840Sraj#define MV_WIN_CPU_MAX 8 492183840Sraj#endif 493183840Sraj 494183840Sraj#define MV_WIN_DDR_BASE(n) (0x8 * (n) + 0x0) 495183840Sraj#define MV_WIN_DDR_SIZE(n) (0x8 * (n) + 0x4) 496183840Sraj#define MV_WIN_DDR_MAX 4 497183840Sraj 498186909Sraj#define MV_WIN_CESA_CTRL(n) (0x8 * (n) + 0xa04) 499186909Sraj#define MV_WIN_CESA_BASE(n) (0x8 * (n) + 0xa00) 500186909Sraj#define MV_WIN_CESA_MAX 4 501186909Sraj 502186909Sraj#define MV_WIN_USB_CTRL(n, m) (0x10 * (n) + (m) * 0x1000 + 0x0) 503186909Sraj#define MV_WIN_USB_BASE(n, m) (0x10 * (n) + (m) * 0x1000 + 0x4) 504183840Sraj#define MV_WIN_USB_MAX 4 505183840Sraj 506183840Sraj#define MV_WIN_ETH_BASE(n) (0x8 * (n) + 0x200) 507183840Sraj#define MV_WIN_ETH_SIZE(n) (0x8 * (n) + 0x204) 508183840Sraj#define MV_WIN_ETH_REMAP(n) (0x4 * (n) + 0x280) 509183840Sraj#define MV_WIN_ETH_MAX 6 510183840Sraj 511183840Sraj#define MV_WIN_IDMA_BASE(n) (0x8 * (n) + 0xa00) 512183840Sraj#define MV_WIN_IDMA_SIZE(n) (0x8 * (n) + 0xa04) 513183840Sraj#define MV_WIN_IDMA_REMAP(n) (0x4 * (n) + 0xa60) 514183840Sraj#define MV_WIN_IDMA_CAP(n) (0x4 * (n) + 0xa70) 515183840Sraj#define MV_WIN_IDMA_MAX 8 516183840Sraj#define MV_IDMA_CHAN_MAX 4 517183840Sraj 518186909Sraj#define MV_WIN_XOR_BASE(n, m) (0x4 * (n) + 0xa50 + (m) * 0x100) 519186909Sraj#define MV_WIN_XOR_SIZE(n, m) (0x4 * (n) + 0xa70 + (m) * 0x100) 520186909Sraj#define MV_WIN_XOR_REMAP(n, m) (0x4 * (n) + 0xa90 + (m) * 0x100) 521186909Sraj#define MV_WIN_XOR_CTRL(n, m) (0x4 * (n) + 0xa40 + (m) * 0x100) 522186909Sraj#define MV_WIN_XOR_OVERR(n, m) (0x4 * (n) + 0xaa0 + (m) * 0x100) 523186909Sraj#define MV_WIN_XOR_MAX 8 524186909Sraj#define MV_XOR_CHAN_MAX 2 525186909Sraj#define MV_XOR_NON_REMAP 4 526186909Sraj 527183840Sraj#define MV_WIN_PCIE_CTRL(n) (0x10 * (((n) < 5) ? (n) : \ 528183840Sraj (n) + 1) + 0x1820) 529183840Sraj#define MV_WIN_PCIE_BASE(n) (0x10 * (((n) < 5) ? (n) : \ 530183840Sraj (n) + 1) + 0x1824) 531183840Sraj#define MV_WIN_PCIE_REMAP(n) (0x10 * (((n) < 5) ? (n) : \ 532183840Sraj (n) + 1) + 0x182C) 533183840Sraj#define MV_WIN_PCIE_MAX 6 534183840Sraj 535183840Sraj#define MV_PCIE_BAR(n) (0x04 * (n) + 0x1804) 536183840Sraj#define MV_PCIE_BAR_MAX 3 537183840Sraj 538186909Sraj#define MV_WIN_SATA_CTRL(n) (0x10 * (n) + 0x30) 539186909Sraj#define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x34) 540186909Sraj#define MV_WIN_SATA_MAX 4 541186909Sraj 542183840Sraj#define WIN_REG_IDX_RD(pre,reg,off,base) \ 543183840Sraj static __inline uint32_t \ 544183840Sraj pre ## _ ## reg ## _read(int i) \ 545183840Sraj { \ 546183840Sraj return (bus_space_read_4(obio_tag, base, off(i))); \ 547183840Sraj } 548183840Sraj 549186909Sraj#define WIN_REG_IDX_RD2(pre,reg,off,base) \ 550186909Sraj static __inline uint32_t \ 551186909Sraj pre ## _ ## reg ## _read(int i, int j) \ 552186909Sraj { \ 553186909Sraj return (bus_space_read_4(obio_tag, base, off(i, j))); \ 554186909Sraj } \ 555186909Sraj 556183840Sraj#define WIN_REG_BASE_IDX_RD(pre,reg,off) \ 557183840Sraj static __inline uint32_t \ 558183840Sraj pre ## _ ## reg ## _read(uint32_t base, int i) \ 559183840Sraj { \ 560183840Sraj return (bus_space_read_4(obio_tag, base, off(i))); \ 561183840Sraj } 562183840Sraj 563183840Sraj#define WIN_REG_IDX_WR(pre,reg,off,base) \ 564183840Sraj static __inline void \ 565183840Sraj pre ## _ ## reg ## _write(int i, uint32_t val) \ 566183840Sraj { \ 567183840Sraj bus_space_write_4(obio_tag, base, off(i), val); \ 568183840Sraj } 569183840Sraj 570186909Sraj#define WIN_REG_IDX_WR2(pre,reg,off,base) \ 571186909Sraj static __inline void \ 572186909Sraj pre ## _ ## reg ## _write(int i, int j, uint32_t val) \ 573186909Sraj { \ 574186909Sraj bus_space_write_4(obio_tag, base, off(i, j), val); \ 575186909Sraj } 576186909Sraj 577183840Sraj#define WIN_REG_BASE_IDX_WR(pre,reg,off) \ 578183840Sraj static __inline void \ 579183840Sraj pre ## _ ## reg ## _write(uint32_t base, int i, uint32_t val) \ 580183840Sraj { \ 581183840Sraj bus_space_write_4(obio_tag, base, off(i), val); \ 582183840Sraj } 583183840Sraj 584183840Sraj#define WIN_REG_RD(pre,reg,off,base) \ 585183840Sraj static __inline uint32_t \ 586183840Sraj pre ## _ ## reg ## _read(void) \ 587183840Sraj { \ 588183840Sraj return (bus_space_read_4(obio_tag, base, off)); \ 589183840Sraj } 590183840Sraj 591183840Sraj#define WIN_REG_BASE_RD(pre,reg,off) \ 592183840Sraj static __inline uint32_t \ 593183840Sraj pre ## _ ## reg ## _read(uint32_t base) \ 594183840Sraj { \ 595183840Sraj return (bus_space_read_4(obio_tag, base, off)); \ 596183840Sraj } 597183840Sraj 598183840Sraj#define WIN_REG_WR(pre,reg,off,base) \ 599183840Sraj static __inline void \ 600183840Sraj pre ## _ ## reg ## _write(uint32_t val) \ 601183840Sraj { \ 602183840Sraj bus_space_write_4(obio_tag, base, off, val); \ 603183840Sraj } 604183840Sraj 605183840Sraj#define WIN_REG_BASE_WR(pre,reg,off) \ 606183840Sraj static __inline void \ 607183840Sraj pre ## _ ## reg ## _write(uint32_t base, uint32_t val) \ 608183840Sraj { \ 609183840Sraj bus_space_write_4(obio_tag, base, off, val); \ 610183840Sraj } 611183840Sraj 612183840Sraj#endif /* _MVREG_H_ */ 613