1183840Sraj/*- 2239277Sgonzo * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 3183840Sraj * All rights reserved. 4183840Sraj * 5183840Sraj * Developed by Semihalf. 6183840Sraj * 7183840Sraj * Redistribution and use in source and binary forms, with or without 8183840Sraj * modification, are permitted provided that the following conditions 9183840Sraj * are met: 10183840Sraj * 1. Redistributions of source code must retain the above copyright 11183840Sraj * notice, this list of conditions and the following disclaimer. 12183840Sraj * 2. Redistributions in binary form must reproduce the above copyright 13183840Sraj * notice, this list of conditions and the following disclaimer in the 14183840Sraj * documentation and/or other materials provided with the distribution. 15183840Sraj * 3. Neither the name of MARVELL nor the names of contributors 16183840Sraj * may be used to endorse or promote products derived from this software 17183840Sraj * without specific prior written permission. 18183840Sraj * 19183840Sraj * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20183840Sraj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21183840Sraj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22183840Sraj * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23183840Sraj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24183840Sraj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25183840Sraj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26183840Sraj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27183840Sraj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28183840Sraj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29183840Sraj * SUCH DAMAGE. 30183840Sraj * 31183840Sraj * $FreeBSD: releng/11.0/sys/arm/mv/mvreg.h 296825 2016-03-14 07:05:41Z wma $ 32183840Sraj */ 33183840Sraj 34183840Sraj#ifndef _MVREG_H_ 35183840Sraj#define _MVREG_H_ 36183840Sraj 37294426Szbb#include <arm/mv/mvwin.h> 38294426Szbb 39183840Sraj#if defined(SOC_MV_DISCOVERY) 40183840Sraj#define IRQ_CAUSE_ERROR 0x0 41183840Sraj#define IRQ_CAUSE 0x4 42183840Sraj#define IRQ_CAUSE_HI 0x8 43183840Sraj#define IRQ_MASK_ERROR 0xC 44183840Sraj#define IRQ_MASK 0x10 45183840Sraj#define IRQ_MASK_HI 0x14 46183840Sraj#define IRQ_CAUSE_SELECT 0x18 47183840Sraj#define FIQ_MASK_ERROR 0x1C 48183840Sraj#define FIQ_MASK 0x20 49183840Sraj#define FIQ_MASK_HI 0x24 50183840Sraj#define FIQ_CAUSE_SELECT 0x28 51239277Sgonzo#define ENDPOINT_IRQ_MASK_ERROR(n) 0x2C 52239277Sgonzo#define ENDPOINT_IRQ_MASK(n) 0x30 53239277Sgonzo#define ENDPOINT_IRQ_MASK_HI(n) 0x34 54183840Sraj#define ENDPOINT_IRQ_CAUSE_SELECT 0x38 55239277Sgonzo#elif defined (SOC_MV_LOKIPLUS) || defined (SOC_MV_FREY) 56183840Sraj#define IRQ_CAUSE 0x0 57183840Sraj#define IRQ_MASK 0x4 58183840Sraj#define FIQ_MASK 0x8 59239277Sgonzo#define ENDPOINT_IRQ_MASK(n) (0xC + (n) * 4) 60239277Sgonzo#define IRQ_CAUSE_HI (-1) /* Fake defines for unified */ 61239277Sgonzo#define IRQ_MASK_HI (-1) /* interrupt controller code */ 62239277Sgonzo#define FIQ_MASK_HI (-1) 63239277Sgonzo#define ENDPOINT_IRQ_MASK_HI(n) (-1) 64239277Sgonzo#define ENDPOINT_IRQ_MASK_ERROR(n) (-1) 65239277Sgonzo#define IRQ_CAUSE_ERROR (-1) 66239277Sgonzo#define IRQ_MASK_ERROR (-1) 67239277Sgonzo#elif defined (SOC_MV_ARMADAXP) 68239277Sgonzo#define IRQ_CAUSE 0x18 69239277Sgonzo#define IRQ_MASK 0x30 70296825Swma#elif defined (SOC_MV_ARMADA38X) 71296825Swma#define MSI_IRQ 0x3ff 72296825Swma#define ERR_IRQ 0x3ff 73296825Swma#else 74239277Sgonzo#define IRQ_CAUSE 0x0 75239277Sgonzo#define IRQ_MASK 0x4 76239277Sgonzo#define FIQ_MASK 0x8 77239277Sgonzo#define ENDPOINT_IRQ_MASK(n) 0xC 78183840Sraj#define IRQ_CAUSE_HI 0x10 79183840Sraj#define IRQ_MASK_HI 0x14 80183840Sraj#define FIQ_MASK_HI 0x18 81239277Sgonzo#define ENDPOINT_IRQ_MASK_HI(n) 0x1C 82239277Sgonzo#define ENDPOINT_IRQ_MASK_ERROR(n) (-1) 83183840Sraj#define IRQ_CAUSE_ERROR (-1) /* Fake defines for unified */ 84183840Sraj#define IRQ_MASK_ERROR (-1) /* interrupt controller code */ 85183840Sraj#endif 86183840Sraj 87239277Sgonzo#if defined(SOC_MV_FREY) 88239277Sgonzo#define BRIDGE_IRQ_CAUSE 0x118 89239277Sgonzo#define IRQ_TIMER0 0x00000002 90239277Sgonzo#define IRQ_TIMER1 0x00000004 91239277Sgonzo#define IRQ_TIMER_WD 0x00000008 92239277Sgonzo 93239277Sgonzo#define BRIDGE_IRQ_MASK 0x11c 94239277Sgonzo#define IRQ_TIMER0_MASK 0x00000002 95239277Sgonzo#define IRQ_TIMER1_MASK 0x00000004 96239277Sgonzo#define IRQ_TIMER_WD_MASK 0x00000008 97239277Sgonzo#elif defined(SOC_MV_ARMADAXP) 98239277Sgonzo#define BRIDGE_IRQ_CAUSE 0x68 99239277Sgonzo#define IRQ_TIMER0 0x00000001 100239277Sgonzo#define IRQ_TIMER1 0x00000002 101239277Sgonzo#define IRQ_TIMER_WD 0x00000004 102239277Sgonzo#else 103183840Sraj#define BRIDGE_IRQ_CAUSE 0x10 104183840Sraj#define IRQ_CPU_SELF 0x00000001 105183840Sraj#define IRQ_TIMER0 0x00000002 106183840Sraj#define IRQ_TIMER1 0x00000004 107183840Sraj#define IRQ_TIMER_WD 0x00000008 108183840Sraj 109183840Sraj#define BRIDGE_IRQ_MASK 0x14 110183840Sraj#define IRQ_CPU_MASK 0x00000001 111183840Sraj#define IRQ_TIMER0_MASK 0x00000002 112183840Sraj#define IRQ_TIMER1_MASK 0x00000004 113183840Sraj#define IRQ_TIMER_WD_MASK 0x00000008 114239277Sgonzo#endif 115183840Sraj 116239277Sgonzo#if defined(SOC_MV_LOKIPLUS) || defined(SOC_MV_FREY) 117239277Sgonzo#define IRQ_CPU_SELF_CLR IRQ_CPU_SELF 118239277Sgonzo#define IRQ_TIMER0_CLR IRQ_TIMER0 119239277Sgonzo#define IRQ_TIMER1_CLR IRQ_TIMER1 120239277Sgonzo#define IRQ_TIMER_WD_CLR IRQ_TIMER_WD 121239277Sgonzo#else 122239277Sgonzo#define IRQ_CPU_SELF_CLR (~IRQ_CPU_SELF) 123239277Sgonzo#define IRQ_TIMER0_CLR (~IRQ_TIMER0) 124239277Sgonzo#define IRQ_TIMER1_CLR (~IRQ_TIMER1) 125239277Sgonzo#define IRQ_TIMER_WD_CLR (~IRQ_TIMER_WD) 126239277Sgonzo#endif 127239277Sgonzo 128183840Sraj/* 129183840Sraj * System reset 130183840Sraj */ 131294416Szbb#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) 132240488Sgber#define RSTOUTn_MASK 0x60 133294436Szbb#define RSTOUTn_MASK_WD 0x400 134240488Sgber#define SYSTEM_SOFT_RESET 0x64 135240488Sgber#define WD_RSTOUTn_MASK 0x4 136240488Sgber#define WD_GLOBAL_MASK 0x00000100 137240488Sgber#define WD_CPU0_MASK 0x00000001 138240488Sgber#define SOFT_RST_OUT_EN 0x00000001 139240488Sgber#define SYS_SOFT_RST 0x00000001 140240488Sgber#else 141183840Sraj#define RSTOUTn_MASK 0x8 142183840Sraj#define WD_RST_OUT_EN 0x00000002 143183840Sraj#define SOFT_RST_OUT_EN 0x00000004 144183840Sraj#define SYSTEM_SOFT_RESET 0xc 145183840Sraj#define SYS_SOFT_RST 0x00000001 146240488Sgber#endif 147183840Sraj 148183840Sraj/* 149183840Sraj * Power Control 150183840Sraj */ 151256760Srrs#if defined(SOC_MV_KIRKWOOD) 152256760Srrs#define CPU_PM_CTRL 0x18 153256760Srrs#else 154183840Sraj#define CPU_PM_CTRL 0x1C 155256760Srrs#endif 156183840Sraj#define CPU_PM_CTRL_NONE 0 157196532Sraj#define CPU_PM_CTRL_ALL ~0x0 158183840Sraj 159183840Sraj#if defined(SOC_MV_KIRKWOOD) 160183840Sraj#define CPU_PM_CTRL_GE0 (1 << 0) 161183840Sraj#define CPU_PM_CTRL_PEX0_PHY (1 << 1) 162183840Sraj#define CPU_PM_CTRL_PEX0 (1 << 2) 163183840Sraj#define CPU_PM_CTRL_USB0 (1 << 3) 164183840Sraj#define CPU_PM_CTRL_SDIO (1 << 4) 165183840Sraj#define CPU_PM_CTRL_TSU (1 << 5) 166183840Sraj#define CPU_PM_CTRL_DUNIT (1 << 6) 167183840Sraj#define CPU_PM_CTRL_RUNIT (1 << 7) 168183840Sraj#define CPU_PM_CTRL_XOR0 (1 << 8) 169183840Sraj#define CPU_PM_CTRL_AUDIO (1 << 9) 170183840Sraj#define CPU_PM_CTRL_SATA0 (1 << 14) 171183840Sraj#define CPU_PM_CTRL_SATA1 (1 << 15) 172183840Sraj#define CPU_PM_CTRL_XOR1 (1 << 16) 173183840Sraj#define CPU_PM_CTRL_CRYPTO (1 << 17) 174196532Sraj#define CPU_PM_CTRL_GE1 (1 << 19) 175196532Sraj#define CPU_PM_CTRL_TDM (1 << 20) 176196532Sraj#define CPU_PM_CTRL_XOR (CPU_PM_CTRL_XOR0 | CPU_PM_CTRL_XOR1) 177196532Sraj#define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_USB0) 178196532Sraj#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1) 179209131Sraj#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \ 180209131Sraj (1 - (u))) 181209131Sraj#define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE) 182183840Sraj#elif defined(SOC_MV_DISCOVERY) 183183840Sraj#define CPU_PM_CTRL_GE0 (1 << 1) 184183840Sraj#define CPU_PM_CTRL_GE1 (1 << 2) 185183840Sraj#define CPU_PM_CTRL_PEX00 (1 << 5) 186183840Sraj#define CPU_PM_CTRL_PEX01 (1 << 6) 187183840Sraj#define CPU_PM_CTRL_PEX02 (1 << 7) 188183840Sraj#define CPU_PM_CTRL_PEX03 (1 << 8) 189183840Sraj#define CPU_PM_CTRL_PEX10 (1 << 9) 190183840Sraj#define CPU_PM_CTRL_PEX11 (1 << 10) 191183840Sraj#define CPU_PM_CTRL_PEX12 (1 << 11) 192183840Sraj#define CPU_PM_CTRL_PEX13 (1 << 12) 193183840Sraj#define CPU_PM_CTRL_SATA0_PHY (1 << 13) 194183840Sraj#define CPU_PM_CTRL_SATA0 (1 << 14) 195183840Sraj#define CPU_PM_CTRL_SATA1_PHY (1 << 15) 196183840Sraj#define CPU_PM_CTRL_SATA1 (1 << 16) 197183840Sraj#define CPU_PM_CTRL_USB0 (1 << 17) 198183840Sraj#define CPU_PM_CTRL_USB1 (1 << 18) 199183840Sraj#define CPU_PM_CTRL_USB2 (1 << 19) 200183840Sraj#define CPU_PM_CTRL_IDMA (1 << 20) 201183840Sraj#define CPU_PM_CTRL_XOR (1 << 21) 202183840Sraj#define CPU_PM_CTRL_CRYPTO (1 << 22) 203183840Sraj#define CPU_PM_CTRL_DEVICE (1 << 23) 204196532Sraj#define CPU_PM_CTRL_USB(u) (1 << (17 + (u))) 205196532Sraj#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1) 206209131Sraj#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \ 207209131Sraj (1 - (u))) 208196532Sraj#else 209196532Sraj#define CPU_PM_CTRL_CRYPTO (CPU_PM_CTRL_NONE) 210196532Sraj#define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE) 211196532Sraj#define CPU_PM_CTRL_XOR (CPU_PM_CTRL_NONE) 212196532Sraj#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_NONE) 213196532Sraj#define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_NONE) 214209131Sraj#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_NONE) 215183840Sraj#endif 216183840Sraj 217183840Sraj/* 218183840Sraj * Timers 219183840Sraj */ 220239277Sgonzo#define CPU_TIMERS_BASE 0x300 221183840Sraj#define CPU_TIMER_CONTROL 0x0 222183840Sraj#define CPU_TIMER0_EN 0x00000001 223183840Sraj#define CPU_TIMER0_AUTO 0x00000002 224183840Sraj#define CPU_TIMER1_EN 0x00000004 225183840Sraj#define CPU_TIMER1_AUTO 0x00000008 226294436Szbb#define CPU_TIMER2_EN 0x00000010 227294436Szbb#define CPU_TIMER2_AUTO 0x00000020 228294436Szbb#define CPU_TIMER_WD_EN 0x00000100 229294436Szbb#define CPU_TIMER_WD_AUTO 0x00000200 230251371Sgber/* 25MHz mode is Armada XP - specific */ 231251371Sgber#define CPU_TIMER_WD_25MHZ_EN 0x00000400 232251371Sgber#define CPU_TIMER0_25MHZ_EN 0x00000800 233251371Sgber#define CPU_TIMER1_25MHZ_EN 0x00001000 234183840Sraj#define CPU_TIMER0_REL 0x10 235183840Sraj#define CPU_TIMER0 0x14 236183840Sraj 237183840Sraj/* 238194845Sraj * SATA 239194845Sraj */ 240194845Sraj#define SATA_CHAN_NUM 2 241194845Sraj 242194845Sraj#define EDMA_REGISTERS_OFFSET 0x2000 243194845Sraj#define EDMA_REGISTERS_SIZE 0x2000 244194845Sraj#define SATA_EDMA_BASE(ch) (EDMA_REGISTERS_OFFSET + \ 245194845Sraj ((ch) * EDMA_REGISTERS_SIZE)) 246194845Sraj 247194845Sraj/* SATAHC registers */ 248194845Sraj#define SATA_CR 0x000 /* Configuration Reg. */ 249194845Sraj#define SATA_CR_NODMABS (1 << 8) 250194845Sraj#define SATA_CR_NOEDMABS (1 << 9) 251194845Sraj#define SATA_CR_NOPRDPBS (1 << 10) 252194845Sraj#define SATA_CR_COALDIS(ch) (1 << (24 + ch)) 253194845Sraj 254239277Sgonzo/* Interrupt Coalescing Threshold Reg. */ 255239277Sgonzo#define SATA_ICTR 0x00C 256239277Sgonzo#define SATA_ICTR_MAX ((1 << 8) - 1) 257239277Sgonzo 258239277Sgonzo/* Interrupt Time Threshold Reg. */ 259239277Sgonzo#define SATA_ITTR 0x010 260239277Sgonzo#define SATA_ITTR_MAX ((1 << 24) - 1) 261239277Sgonzo 262239277Sgonzo#define SATA_ICR 0x014 /* Interrupt Cause Reg. */ 263194845Sraj#define SATA_ICR_DMADONE(ch) (1 << (ch)) 264194845Sraj#define SATA_ICR_COAL (1 << 4) 265194845Sraj#define SATA_ICR_DEV(ch) (1 << (8 + ch)) 266194845Sraj 267194845Sraj#define SATA_MICR 0x020 /* Main Interrupt Cause Reg. */ 268194845Sraj#define SATA_MICR_ERR(ch) (1 << (2 * ch)) 269194845Sraj#define SATA_MICR_DONE(ch) (1 << ((2 * ch) + 1)) 270194845Sraj#define SATA_MICR_DMADONE(ch) (1 << (4 + ch)) 271194845Sraj#define SATA_MICR_COAL (1 << 8) 272194845Sraj 273194845Sraj#define SATA_MIMR 0x024 /* Main Interrupt Mask Reg. */ 274194845Sraj 275194845Sraj/* Shadow registers */ 276194845Sraj#define SATA_SHADOWR_BASE(ch) (SATA_EDMA_BASE(ch) + 0x100) 277194845Sraj#define SATA_SHADOWR_CONTROL(ch) (SATA_EDMA_BASE(ch) + 0x120) 278194845Sraj 279194845Sraj/* SATA registers */ 280194845Sraj#define SATA_SATA_SSTATUS(ch) (SATA_EDMA_BASE(ch) + 0x300) 281194845Sraj#define SATA_SATA_SERROR(ch) (SATA_EDMA_BASE(ch) + 0x304) 282194845Sraj#define SATA_SATA_SCONTROL(ch) (SATA_EDMA_BASE(ch) + 0x308) 283194845Sraj#define SATA_SATA_FISICR(ch) (SATA_EDMA_BASE(ch) + 0x364) 284194845Sraj 285194845Sraj/* EDMA registers */ 286194845Sraj#define SATA_EDMA_CFG(ch) (SATA_EDMA_BASE(ch) + 0x000) 287194845Sraj#define SATA_EDMA_CFG_QL128 (1 << 19) 288194845Sraj#define SATA_EDMA_CFG_HQCACHE (1 << 22) 289194845Sraj 290194845Sraj#define SATA_EDMA_IECR(ch) (SATA_EDMA_BASE(ch) + 0x008) 291194845Sraj 292194845Sraj#define SATA_EDMA_IEMR(ch) (SATA_EDMA_BASE(ch) + 0x00C) 293194845Sraj#define SATA_EDMA_REQBAHR(ch) (SATA_EDMA_BASE(ch) + 0x010) 294194845Sraj#define SATA_EDMA_REQIPR(ch) (SATA_EDMA_BASE(ch) + 0x014) 295194845Sraj#define SATA_EDMA_REQOPR(ch) (SATA_EDMA_BASE(ch) + 0x018) 296194845Sraj#define SATA_EDMA_RESBAHR(ch) (SATA_EDMA_BASE(ch) + 0x01C) 297194845Sraj#define SATA_EDMA_RESIPR(ch) (SATA_EDMA_BASE(ch) + 0x020) 298194845Sraj#define SATA_EDMA_RESOPR(ch) (SATA_EDMA_BASE(ch) + 0x024) 299194845Sraj 300194845Sraj#define SATA_EDMA_CMD(ch) (SATA_EDMA_BASE(ch) + 0x028) 301194845Sraj#define SATA_EDMA_CMD_ENABLE (1 << 0) 302194845Sraj#define SATA_EDMA_CMD_DISABLE (1 << 1) 303194845Sraj#define SATA_EDMA_CMD_RESET (1 << 2) 304194845Sraj 305194845Sraj#define SATA_EDMA_STATUS(ch) (SATA_EDMA_BASE(ch) + 0x030) 306194845Sraj#define SATA_EDMA_STATUS_IDLE (1 << 7) 307194845Sraj 308194845Sraj/* Offset to extract input slot from REQIPR register */ 309194845Sraj#define SATA_EDMA_REQIS_OFS 5 310194845Sraj 311194845Sraj/* Offset to extract input slot from RESOPR register */ 312194845Sraj#define SATA_EDMA_RESOS_OFS 3 313194845Sraj 314194845Sraj/* 315183840Sraj * GPIO 316183840Sraj */ 317183840Sraj#define GPIO_DATA_OUT 0x00 318183840Sraj#define GPIO_DATA_OUT_EN_CTRL 0x04 319183840Sraj#define GPIO_BLINK_EN 0x08 320183840Sraj#define GPIO_DATA_IN_POLAR 0x0c 321183840Sraj#define GPIO_DATA_IN 0x10 322183840Sraj#define GPIO_INT_CAUSE 0x14 323183840Sraj#define GPIO_INT_EDGE_MASK 0x18 324183840Sraj#define GPIO_INT_LEV_MASK 0x1c 325183840Sraj 326183840Sraj#define GPIO_HI_DATA_OUT 0x40 327183840Sraj#define GPIO_HI_DATA_OUT_EN_CTRL 0x44 328183840Sraj#define GPIO_HI_BLINK_EN 0x48 329183840Sraj#define GPIO_HI_DATA_IN_POLAR 0x4c 330183840Sraj#define GPIO_HI_DATA_IN 0x50 331183840Sraj#define GPIO_HI_INT_CAUSE 0x54 332183840Sraj#define GPIO_HI_INT_EDGE_MASK 0x58 333183840Sraj#define GPIO_HI_INT_LEV_MASK 0x5c 334183840Sraj 335183840Sraj#define GPIO(n) (1 << (n)) 336183840Sraj#define MV_GPIO_MAX_NPINS 64 337183840Sraj 338209131Sraj#define MV_GPIO_IN_NONE 0x0 339209131Sraj#define MV_GPIO_IN_POL_LOW (1 << 16) 340209131Sraj#define MV_GPIO_IN_IRQ_EDGE (2 << 16) 341209131Sraj#define MV_GPIO_IN_IRQ_LEVEL (4 << 16) 342209131Sraj#define MV_GPIO_OUT_NONE 0x0 343209131Sraj#define MV_GPIO_OUT_BLINK 0x1 344209131Sraj#define MV_GPIO_OUT_OPEN_DRAIN 0x2 345209131Sraj#define MV_GPIO_OUT_OPEN_SRC 0x4 346183840Sraj 347183840Sraj#define IS_GPIO_IRQ(irq) ((irq) >= NIRQ && (irq) < NIRQ + MV_GPIO_MAX_NPINS) 348183840Sraj#define GPIO2IRQ(gpio) ((gpio) + NIRQ) 349183840Sraj#define IRQ2GPIO(irq) ((irq) - NIRQ) 350183840Sraj 351239277Sgonzo#if defined(SOC_MV_ORION) || defined(SOC_MV_LOKIPLUS) 352183840Sraj#define SAMPLE_AT_RESET 0x10 353186899Sraj#elif defined(SOC_MV_KIRKWOOD) 354183840Sraj#define SAMPLE_AT_RESET 0x30 355243580Smarcel#elif defined(SOC_MV_FREY) 356243580Smarcel#define SAMPLE_AT_RESET 0x100 357294416Szbb#elif defined(SOC_MV_ARMADA38X) 358294416Szbb#define SAMPLE_AT_RESET 0x400 359243580Smarcel#endif 360243580Smarcel#if defined(SOC_MV_DISCOVERY) 361186899Sraj#define SAMPLE_AT_RESET_LO 0x30 362186899Sraj#define SAMPLE_AT_RESET_HI 0x34 363239277Sgonzo#elif defined(SOC_MV_DOVE) 364239277Sgonzo#define SAMPLE_AT_RESET_LO 0x14 365239277Sgonzo#define SAMPLE_AT_RESET_HI 0x18 366240488Sgber#elif defined(SOC_MV_ARMADAXP) 367240488Sgber#define SAMPLE_AT_RESET_LO 0x30 368240488Sgber#define SAMPLE_AT_RESET_HI 0x34 369183840Sraj#endif 370183840Sraj 371183840Sraj/* 372183840Sraj * Clocks 373183840Sraj */ 374186899Sraj#if defined(SOC_MV_ORION) 375186899Sraj#define TCLK_MASK 0x00000300 376186899Sraj#define TCLK_SHIFT 0x08 377186899Sraj#elif defined(SOC_MV_DISCOVERY) 378186899Sraj#define TCLK_MASK 0x00000180 379186899Sraj#define TCLK_SHIFT 0x07 380239277Sgonzo#elif defined(SOC_MV_LOKIPLUS) 381239277Sgonzo#define TCLK_MASK 0x0000F000 382239277Sgonzo#define TCLK_SHIFT 0x0C 383294416Szbb#elif defined(SOC_MV_ARMADA38X) 384294416Szbb#define TCLK_MASK 0x00008000 385294416Szbb#define TCLK_SHIFT 15 386183840Sraj#endif 387183840Sraj 388183840Sraj#define TCLK_100MHZ 100000000 389183840Sraj#define TCLK_125MHZ 125000000 390183840Sraj#define TCLK_133MHZ 133333333 391183840Sraj#define TCLK_150MHZ 150000000 392183840Sraj#define TCLK_166MHZ 166666667 393183840Sraj#define TCLK_200MHZ 200000000 394239277Sgonzo#define TCLK_250MHZ 250000000 395239277Sgonzo#define TCLK_300MHZ 300000000 396239277Sgonzo#define TCLK_667MHZ 667000000 397183840Sraj 398183840Sraj/* 399239277Sgonzo * CPU Cache Configuration 400239277Sgonzo */ 401239277Sgonzo 402239277Sgonzo#define CPU_CONFIG 0x00000000 403239277Sgonzo#define CPU_CONFIG_IC_PREF 0x00010000 404239277Sgonzo#define CPU_CONFIG_DC_PREF 0x00020000 405239277Sgonzo#define CPU_CONTROL 0x00000004 406239277Sgonzo#define CPU_CONTROL_L2_SIZE 0x00200000 /* Only on Discovery */ 407239277Sgonzo#define CPU_CONTROL_L2_MODE 0x00020000 /* Only on Discovery */ 408239277Sgonzo#define CPU_L2_CONFIG 0x00000028 /* Only on Kirkwood */ 409239277Sgonzo#define CPU_L2_CONFIG_MODE 0x00000010 /* Only on Kirkwood */ 410239277Sgonzo 411239277Sgonzo/* 412239277Sgonzo * PCI Express port control (CPU Control registers) 413239277Sgonzo */ 414239277Sgonzo#define CPU_CONTROL_PCIE_DISABLE(n) (1 << (3 * (n))) 415239277Sgonzo 416239277Sgonzo/* 417239277Sgonzo * Vendor ID 418239277Sgonzo */ 419239277Sgonzo#define PCI_VENDORID_MRVL 0x11AB 420239277Sgonzo#define PCI_VENDORID_MRVL2 0x1B4B 421239277Sgonzo 422239277Sgonzo/* 423183840Sraj * Chip ID 424183840Sraj */ 425191140Sraj#define MV_DEV_88F5181 0x5181 426191140Sraj#define MV_DEV_88F5182 0x5182 427191140Sraj#define MV_DEV_88F5281 0x5281 428191140Sraj#define MV_DEV_88F6281 0x6281 429239370Shrs#define MV_DEV_88F6282 0x6282 430239277Sgonzo#define MV_DEV_88F6781 0x6781 431294416Szbb#define MV_DEV_88F6828 0x6828 432294416Szbb#define MV_DEV_88F6820 0x6820 433294416Szbb#define MV_DEV_88F6810 0x6810 434191140Sraj#define MV_DEV_MV78100_Z0 0x6381 435191140Sraj#define MV_DEV_MV78100 0x7810 436239277Sgonzo#define MV_DEV_MV78130 0x7813 437239277Sgonzo#define MV_DEV_MV78160 0x7816 438239277Sgonzo#define MV_DEV_MV78230 0x7823 439239277Sgonzo#define MV_DEV_MV78260 0x7826 440239277Sgonzo#define MV_DEV_MV78460 0x7846 441239277Sgonzo#define MV_DEV_88RC8180 0x8180 442239277Sgonzo#define MV_DEV_88RC9480 0x9480 443239277Sgonzo#define MV_DEV_88RC9580 0x9580 444183840Sraj 445239277Sgonzo#define MV_DEV_FAMILY_MASK 0xff00 446239277Sgonzo#define MV_DEV_DISCOVERY 0x7800 447294430Szbb#define MV_DEV_ARMADA38X 0x6800 448239277Sgonzo 449239277Sgonzo/* 450239277Sgonzo * Doorbell register control 451239277Sgonzo */ 452239277Sgonzo#define MV_DRBL_PCIE_TO_CPU 0 453239277Sgonzo#define MV_DRBL_CPU_TO_PCIE 1 454239277Sgonzo 455239277Sgonzo#if defined(SOC_MV_FREY) 456239277Sgonzo#define MV_DRBL_CAUSE(d,u) (0x60 + 0x20 * (d) + 0x8 * (u)) 457239277Sgonzo#define MV_DRBL_MASK(d,u) (0x60 + 0x20 * (d) + 0x8 * (u) + 0x4) 458239277Sgonzo#define MV_DRBL_MSG(m,d,u) (0x8 * (u) + 0x20 * (d) + 0x4 * (m)) 459239277Sgonzo#else 460239277Sgonzo#define MV_DRBL_CAUSE(d,u) (0x10 * (u) + 0x8 * (d)) 461239277Sgonzo#define MV_DRBL_MASK(d,u) (0x10 * (u) + 0x8 * (d) + 0x4) 462239277Sgonzo#define MV_DRBL_MSG(m,d,u) (0x10 * (u) + 0x8 * (d) + 0x4 * (m) + 0x30) 463239277Sgonzo#endif 464294426Szbb 465294426Szbb/* 466294426Szbb * SCU 467294426Szbb */ 468294426Szbb#if defined(SOC_MV_ARMADA38X) 469294426Szbb#define MV_SCU_BASE (MV_BASE + 0xc000) 470294426Szbb#define MV_SCU_REGS_LEN 0x100 471294439Szbb#define MV_SCU_REG_CTRL 0x00 472294439Szbb#define MV_SCU_REG_CONFIG 0x04 473294426Szbb#define MV_SCU_ENABLE 1 474294441Szbb#define SCU_CFG_REG_NCPU_MASK 0x3 475294426Szbb#endif 476294426Szbb 477294439Szbb/* 478294439Szbb * PMSU 479294439Szbb */ 480294439Szbb#if defined(SOC_MV_ARMADA38X) 481294439Szbb#define MV_PMSU_BASE (MV_BASE + 0x22000) 482294439Szbb#define MV_PMSU_REGS_LEN 0x1000 483294439Szbb#define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) (((cpu) * 0x100) + 0x124) 484294439Szbb#endif 485294439Szbb 486294439Szbb/* 487294439Szbb * CPU RESET 488294439Szbb */ 489294439Szbb#if defined(SOC_MV_ARMADA38X) 490294439Szbb#define MV_CPU_RESET_BASE (MV_BASE + 0x20800) 491294439Szbb#define MV_CPU_RESET_REGS_LEN 0x8 492294439Szbb#define CPU_RESET_OFFSET(cpu) ((cpu) * 0x8) 493294439Szbb#define CPU_RESET_ASSERT 0x1 494294439Szbb#endif 495294439Szbb 496183840Sraj#endif /* _MVREG_H_ */ 497