mv_machdep.c revision 300533
1/*- 2 * Copyright (c) 1994-1998 Mark Brinicombe. 3 * Copyright (c) 1994 Brini. 4 * All rights reserved. 5 * 6 * This code is derived from software written for Brini by Mark Brinicombe 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45 36 */ 37 38#include "opt_ddb.h" 39#include "opt_platform.h" 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: head/sys/arm/mv/mv_machdep.c 300533 2016-05-23 20:07:17Z ian $"); 43 44#define _ARM32_BUS_DMA_PRIVATE 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/bus.h> 48#include <sys/devmap.h> 49 50#include <vm/vm.h> 51#include <vm/pmap.h> 52 53#include <machine/acle-compat.h> 54#include <machine/bus.h> 55#include <machine/fdt.h> 56#include <machine/machdep.h> 57#include <machine/platform.h> 58 59#if __ARM_ARCH < 6 60#include <machine/cpu-v4.h> 61#else 62#include <machine/cpu-v6.h> 63#endif 64 65#include <arm/mv/mvreg.h> /* XXX */ 66#include <arm/mv/mvvar.h> /* XXX eventually this should be eliminated */ 67#include <arm/mv/mvwin.h> 68 69#include <dev/fdt/fdt_common.h> 70 71static int platform_mpp_init(void); 72#if defined(SOC_MV_ARMADAXP) 73void armadaxp_init_coher_fabric(void); 74void armadaxp_l2_init(void); 75#endif 76#if defined(SOC_MV_ARMADA38X) 77int armada38x_win_set_iosync_barrier(void); 78int armada38x_scu_enable(void); 79int armada38x_open_bootrom_win(void); 80#endif 81 82#define MPP_PIN_MAX 68 83#define MPP_PIN_CELLS 2 84#define MPP_PINS_PER_REG 8 85#define MPP_SEL(pin,func) (((func) & 0xf) << \ 86 (((pin) % MPP_PINS_PER_REG) * 4)) 87 88static int 89platform_mpp_init(void) 90{ 91 pcell_t pinmap[MPP_PIN_MAX * MPP_PIN_CELLS]; 92 int mpp[MPP_PIN_MAX]; 93 uint32_t ctrl_val, ctrl_offset; 94 pcell_t reg[4]; 95 u_long start, size; 96 phandle_t node; 97 pcell_t pin_cells, *pinmap_ptr, pin_count; 98 ssize_t len; 99 int par_addr_cells, par_size_cells; 100 int tuple_size, tuples, rv, pins, i, j; 101 int mpp_pin, mpp_function; 102 103 /* 104 * Try to access the MPP node directly i.e. through /aliases/mpp. 105 */ 106 if ((node = OF_finddevice("mpp")) != -1) 107 if (fdt_is_compatible(node, "mrvl,mpp")) 108 goto moveon; 109 /* 110 * Find the node the long way. 111 */ 112 if ((node = OF_finddevice("/")) == -1) 113 return (ENXIO); 114 115 if ((node = fdt_find_compatible(node, "simple-bus", 0)) == 0) 116 return (ENXIO); 117 118 if ((node = fdt_find_compatible(node, "mrvl,mpp", 0)) == 0) 119 /* 120 * No MPP node. Fall back to how MPP got set by the 121 * first-stage loader and try to continue booting. 122 */ 123 return (0); 124moveon: 125 /* 126 * Process 'reg' prop. 127 */ 128 if ((rv = fdt_addrsize_cells(OF_parent(node), &par_addr_cells, 129 &par_size_cells)) != 0) 130 return(ENXIO); 131 132 tuple_size = sizeof(pcell_t) * (par_addr_cells + par_size_cells); 133 len = OF_getprop(node, "reg", reg, sizeof(reg)); 134 tuples = len / tuple_size; 135 if (tuple_size <= 0) 136 return (EINVAL); 137 138 /* 139 * Get address/size. XXX we assume only the first 'reg' tuple is used. 140 */ 141 rv = fdt_data_to_res(reg, par_addr_cells, par_size_cells, 142 &start, &size); 143 if (rv != 0) 144 return (rv); 145 start += fdt_immr_va; 146 147 /* 148 * Process 'pin-count' and 'pin-map' props. 149 */ 150 if (OF_getprop(node, "pin-count", &pin_count, sizeof(pin_count)) <= 0) 151 return (ENXIO); 152 pin_count = fdt32_to_cpu(pin_count); 153 if (pin_count > MPP_PIN_MAX) 154 return (ERANGE); 155 156 if (OF_getprop(node, "#pin-cells", &pin_cells, sizeof(pin_cells)) <= 0) 157 pin_cells = MPP_PIN_CELLS; 158 pin_cells = fdt32_to_cpu(pin_cells); 159 if (pin_cells > MPP_PIN_CELLS) 160 return (ERANGE); 161 tuple_size = sizeof(pcell_t) * pin_cells; 162 163 bzero(pinmap, sizeof(pinmap)); 164 len = OF_getprop(node, "pin-map", pinmap, sizeof(pinmap)); 165 if (len <= 0) 166 return (ERANGE); 167 if (len % tuple_size) 168 return (ERANGE); 169 pins = len / tuple_size; 170 if (pins > pin_count) 171 return (ERANGE); 172 /* 173 * Fill out a "mpp[pin] => function" table. All pins unspecified in 174 * the 'pin-map' property are defaulted to 0 function i.e. GPIO. 175 */ 176 bzero(mpp, sizeof(mpp)); 177 pinmap_ptr = pinmap; 178 for (i = 0; i < pins; i++) { 179 mpp_pin = fdt32_to_cpu(*pinmap_ptr); 180 mpp_function = fdt32_to_cpu(*(pinmap_ptr + 1)); 181 mpp[mpp_pin] = mpp_function; 182 pinmap_ptr += pin_cells; 183 } 184 185 /* 186 * Prepare and program MPP control register values. 187 */ 188 ctrl_offset = 0; 189 for (i = 0; i < pin_count;) { 190 ctrl_val = 0; 191 192 for (j = 0; j < MPP_PINS_PER_REG; j++) { 193 if (i + j == pin_count - 1) 194 break; 195 ctrl_val |= MPP_SEL(i + j, mpp[i + j]); 196 } 197 i += MPP_PINS_PER_REG; 198 bus_space_write_4(fdtbus_bs_tag, start, ctrl_offset, 199 ctrl_val); 200 201#if defined(SOC_MV_ORION) 202 /* 203 * Third MPP reg on Orion SoC is placed 204 * non-linearly (with different offset). 205 */ 206 if (i == (2 * MPP_PINS_PER_REG)) 207 ctrl_offset = 0x50; 208 else 209#endif 210 ctrl_offset += 4; 211 } 212 213 return (0); 214} 215 216vm_offset_t 217platform_lastaddr(void) 218{ 219 220 return (fdt_immr_va); 221} 222 223void 224platform_probe_and_attach(void) 225{ 226 227 if (fdt_immr_addr(MV_BASE) != 0) 228 while (1); 229} 230 231void 232platform_gpio_init(void) 233{ 234 235 /* 236 * Re-initialise MPP. It is important to call this prior to using 237 * console as the physical connection can be routed via MPP. 238 */ 239 if (platform_mpp_init() != 0) 240 while (1); 241} 242 243void 244platform_late_init(void) 245{ 246 /* 247 * Re-initialise decode windows 248 */ 249#if !defined(SOC_MV_FREY) 250 if (soc_decode_win() != 0) 251 printf("WARNING: could not re-initialise decode windows! " 252 "Running with existing settings...\n"); 253#else 254 /* Disable watchdog and timers */ 255 write_cpu_ctrl(CPU_TIMERS_BASE + CPU_TIMER_CONTROL, 0); 256#endif 257#if defined(SOC_MV_ARMADAXP) 258#if !defined(SMP) 259 /* For SMP case it should be initialized after APs are booted */ 260 armadaxp_init_coher_fabric(); 261#endif 262 armadaxp_l2_init(); 263#endif 264 265#if defined(SOC_MV_ARMADA38X) 266 /* Set IO Sync Barrier bit for all Mbus devices */ 267 if (armada38x_win_set_iosync_barrier() != 0) 268 printf("WARNING: could not map CPU Subsystem registers\n"); 269 if (armada38x_scu_enable() != 0) 270 printf("WARNING: could not enable SCU\n"); 271#ifdef SMP 272 /* Open window to bootROM memory - needed for SMP */ 273 if (armada38x_open_bootrom_win() != 0) 274 printf("WARNING: could not open window to bootROM\n"); 275#endif 276#endif 277} 278 279#define FDT_DEVMAP_MAX (MV_WIN_CPU_MAX + 2) 280static struct devmap_entry fdt_devmap[FDT_DEVMAP_MAX] = { 281 { 0, 0, 0, } 282}; 283 284static int 285platform_sram_devmap(struct devmap_entry *map) 286{ 287#if !defined(SOC_MV_ARMADAXP) 288 phandle_t child, root; 289 u_long base, size; 290 /* 291 * SRAM range. 292 */ 293 if ((child = OF_finddevice("/sram")) != 0) 294 if (fdt_is_compatible(child, "mrvl,cesa-sram") || 295 fdt_is_compatible(child, "mrvl,scratchpad")) 296 goto moveon; 297 298 if ((root = OF_finddevice("/")) == 0) 299 return (ENXIO); 300 301 if ((child = fdt_find_compatible(root, "mrvl,cesa-sram", 0)) == 0 && 302 (child = fdt_find_compatible(root, "mrvl,scratchpad", 0)) == 0) 303 goto out; 304 305moveon: 306 if (fdt_regsize(child, &base, &size) != 0) 307 return (EINVAL); 308 309 map->pd_va = MV_CESA_SRAM_BASE; /* XXX */ 310 map->pd_pa = base; 311 map->pd_size = size; 312 313 return (0); 314out: 315#endif 316 return (ENOENT); 317 318} 319 320/* 321 * Supply a default do-nothing implementation of mv_pci_devmap() via a weak 322 * alias. Many Marvell platforms don't support a PCI interface, but to support 323 * those that do, we end up with a reference to this function below, in 324 * platform_devmap_init(). If "device pci" appears in the kernel config, the 325 * real implementation of this function in arm/mv/mv_pci.c overrides the weak 326 * alias defined here. 327 */ 328int mv_default_fdt_pci_devmap(phandle_t node, struct devmap_entry *devmap, 329 vm_offset_t io_va, vm_offset_t mem_va); 330int 331mv_default_fdt_pci_devmap(phandle_t node, struct devmap_entry *devmap, 332 vm_offset_t io_va, vm_offset_t mem_va) 333{ 334 335 return (0); 336} 337__weak_reference(mv_default_fdt_pci_devmap, mv_pci_devmap); 338 339/* 340 * XXX: When device entry in devmap has pd_size smaller than section size, 341 * system will freeze during initialization 342 */ 343 344/* 345 * Construct devmap table with DT-derived config data. 346 */ 347int 348platform_devmap_init(void) 349{ 350 phandle_t root, child; 351 pcell_t bank_count; 352 int i, num_mapped; 353 354 i = 0; 355 devmap_register_table(&fdt_devmap[0]); 356 357#ifdef SOC_MV_ARMADAXP 358 vm_paddr_t cur_immr_pa; 359 360 /* 361 * Acquire SoC registers' base passed by u-boot and fill devmap 362 * accordingly. DTB is going to be modified basing on this data 363 * later. 364 */ 365 __asm __volatile("mrc p15, 4, %0, c15, c0, 0" : "=r" (cur_immr_pa)); 366 cur_immr_pa = (cur_immr_pa << 13) & 0xff000000; 367 if (cur_immr_pa != 0) 368 fdt_immr_pa = cur_immr_pa; 369#endif 370 /* 371 * IMMR range. 372 */ 373 fdt_devmap[i].pd_va = fdt_immr_va; 374 fdt_devmap[i].pd_pa = fdt_immr_pa; 375 fdt_devmap[i].pd_size = fdt_immr_size; 376 i++; 377 378 /* 379 * SRAM range. 380 */ 381 if (i < FDT_DEVMAP_MAX) 382 if (platform_sram_devmap(&fdt_devmap[i]) == 0) 383 i++; 384 385 /* 386 * PCI range(s). 387 * PCI range(s) and localbus. 388 */ 389 if ((root = OF_finddevice("/")) == -1) 390 return (ENXIO); 391 for (child = OF_child(root); child != 0; child = OF_peer(child)) { 392 if (fdt_is_type(child, "pci") || fdt_is_type(child, "pciep")) { 393 /* 394 * Check space: each PCI node will consume 2 devmap 395 * entries. 396 */ 397 if (i + 1 >= FDT_DEVMAP_MAX) 398 return (ENOMEM); 399 400 /* 401 * XXX this should account for PCI and multiple ranges 402 * of a given kind. 403 */ 404 if (mv_pci_devmap(child, &fdt_devmap[i], MV_PCI_VA_IO_BASE, 405 MV_PCI_VA_MEM_BASE) != 0) 406 return (ENXIO); 407 i += 2; 408 } 409 410 if (fdt_is_compatible(child, "mrvl,lbc")) { 411 /* Check available space */ 412 if (OF_getprop(child, "bank-count", (void *)&bank_count, 413 sizeof(bank_count)) <= 0) 414 /* If no property, use default value */ 415 bank_count = 1; 416 else 417 bank_count = fdt32_to_cpu(bank_count); 418 419 if ((i + bank_count) >= FDT_DEVMAP_MAX) 420 return (ENOMEM); 421 422 /* Add all localbus ranges to device map */ 423 num_mapped = 0; 424 425 if (fdt_localbus_devmap(child, &fdt_devmap[i], 426 (int)bank_count, &num_mapped) != 0) 427 return (ENXIO); 428 429 i += num_mapped; 430 } 431 } 432 433 return (0); 434} 435 436struct arm32_dma_range * 437bus_dma_get_range(void) 438{ 439 440 return (NULL); 441} 442 443int 444bus_dma_get_range_nb(void) 445{ 446 447 return (0); 448} 449 450#if defined(CPU_MV_PJ4B) 451#ifdef DDB 452#include <ddb/ddb.h> 453 454DB_SHOW_COMMAND(cp15, db_show_cp15) 455{ 456 u_int reg; 457 458 __asm __volatile("mrc p15, 0, %0, c0, c0, 0" : "=r" (reg)); 459 db_printf("Cpu ID: 0x%08x\n", reg); 460 __asm __volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (reg)); 461 db_printf("Current Cache Lvl ID: 0x%08x\n",reg); 462 463 reg = cp15_sctlr_get(); 464 db_printf("Ctrl: 0x%08x\n",reg); 465 reg = cp15_actlr_get(); 466 db_printf("Aux Ctrl: 0x%08x\n",reg); 467 468 __asm __volatile("mrc p15, 0, %0, c0, c1, 0" : "=r" (reg)); 469 db_printf("Processor Feat 0: 0x%08x\n", reg); 470 __asm __volatile("mrc p15, 0, %0, c0, c1, 1" : "=r" (reg)); 471 db_printf("Processor Feat 1: 0x%08x\n", reg); 472 __asm __volatile("mrc p15, 0, %0, c0, c1, 2" : "=r" (reg)); 473 db_printf("Debug Feat 0: 0x%08x\n", reg); 474 __asm __volatile("mrc p15, 0, %0, c0, c1, 3" : "=r" (reg)); 475 db_printf("Auxiliary Feat 0: 0x%08x\n", reg); 476 __asm __volatile("mrc p15, 0, %0, c0, c1, 4" : "=r" (reg)); 477 db_printf("Memory Model Feat 0: 0x%08x\n", reg); 478 __asm __volatile("mrc p15, 0, %0, c0, c1, 5" : "=r" (reg)); 479 db_printf("Memory Model Feat 1: 0x%08x\n", reg); 480 __asm __volatile("mrc p15, 0, %0, c0, c1, 6" : "=r" (reg)); 481 db_printf("Memory Model Feat 2: 0x%08x\n", reg); 482 __asm __volatile("mrc p15, 0, %0, c0, c1, 7" : "=r" (reg)); 483 db_printf("Memory Model Feat 3: 0x%08x\n", reg); 484 485 __asm __volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (reg)); 486 db_printf("Aux Func Modes Ctrl 0: 0x%08x\n",reg); 487 __asm __volatile("mrc p15, 1, %0, c15, c2, 1" : "=r" (reg)); 488 db_printf("Aux Func Modes Ctrl 1: 0x%08x\n",reg); 489 490 __asm __volatile("mrc p15, 1, %0, c15, c12, 0" : "=r" (reg)); 491 db_printf("CPU ID code extension: 0x%08x\n",reg); 492} 493 494DB_SHOW_COMMAND(vtop, db_show_vtop) 495{ 496 u_int reg; 497 498 if (have_addr) { 499 __asm __volatile("mcr p15, 0, %0, c7, c8, 0" : : "r" (addr)); 500 __asm __volatile("mrc p15, 0, %0, c7, c4, 0" : "=r" (reg)); 501 db_printf("Physical address reg: 0x%08x\n",reg); 502 } else 503 db_printf("show vtop <virt_addr>\n"); 504} 505#endif /* DDB */ 506#endif /* CPU_MV_PJ4B */ 507 508