mv_machdep.c revision 295143
1/*- 2 * Copyright (c) 1994-1998 Mark Brinicombe. 3 * Copyright (c) 1994 Brini. 4 * All rights reserved. 5 * 6 * This code is derived from software written for Brini by Mark Brinicombe 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45 36 */ 37 38#include "opt_ddb.h" 39#include "opt_platform.h" 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: head/sys/arm/mv/mv_machdep.c 295143 2016-02-02 10:32:45Z skra $"); 43 44#define _ARM32_BUS_DMA_PRIVATE 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/bus.h> 48 49#include <vm/vm.h> 50#include <vm/pmap.h> 51 52#include <machine/bus.h> 53#include <machine/devmap.h> 54#include <machine/fdt.h> 55#include <machine/machdep.h> 56#include <machine/platform.h> 57 58#include <arm/mv/mvreg.h> /* XXX */ 59#include <arm/mv/mvvar.h> /* XXX eventually this should be eliminated */ 60#include <arm/mv/mvwin.h> 61 62#include <dev/fdt/fdt_common.h> 63 64static int platform_mpp_init(void); 65#if defined(SOC_MV_ARMADAXP) 66void armadaxp_init_coher_fabric(void); 67void armadaxp_l2_init(void); 68#endif 69#if defined(SOC_MV_ARMADA38X) 70int armada38x_win_set_iosync_barrier(void); 71int armada38x_scu_enable(void); 72int armada38x_open_bootrom_win(void); 73#endif 74 75#define MPP_PIN_MAX 68 76#define MPP_PIN_CELLS 2 77#define MPP_PINS_PER_REG 8 78#define MPP_SEL(pin,func) (((func) & 0xf) << \ 79 (((pin) % MPP_PINS_PER_REG) * 4)) 80 81static int 82platform_mpp_init(void) 83{ 84 pcell_t pinmap[MPP_PIN_MAX * MPP_PIN_CELLS]; 85 int mpp[MPP_PIN_MAX]; 86 uint32_t ctrl_val, ctrl_offset; 87 pcell_t reg[4]; 88 u_long start, size; 89 phandle_t node; 90 pcell_t pin_cells, *pinmap_ptr, pin_count; 91 ssize_t len; 92 int par_addr_cells, par_size_cells; 93 int tuple_size, tuples, rv, pins, i, j; 94 int mpp_pin, mpp_function; 95 96 /* 97 * Try to access the MPP node directly i.e. through /aliases/mpp. 98 */ 99 if ((node = OF_finddevice("mpp")) != -1) 100 if (fdt_is_compatible(node, "mrvl,mpp")) 101 goto moveon; 102 /* 103 * Find the node the long way. 104 */ 105 if ((node = OF_finddevice("/")) == -1) 106 return (ENXIO); 107 108 if ((node = fdt_find_compatible(node, "simple-bus", 0)) == 0) 109 return (ENXIO); 110 111 if ((node = fdt_find_compatible(node, "mrvl,mpp", 0)) == 0) 112 /* 113 * No MPP node. Fall back to how MPP got set by the 114 * first-stage loader and try to continue booting. 115 */ 116 return (0); 117moveon: 118 /* 119 * Process 'reg' prop. 120 */ 121 if ((rv = fdt_addrsize_cells(OF_parent(node), &par_addr_cells, 122 &par_size_cells)) != 0) 123 return(ENXIO); 124 125 tuple_size = sizeof(pcell_t) * (par_addr_cells + par_size_cells); 126 len = OF_getprop(node, "reg", reg, sizeof(reg)); 127 tuples = len / tuple_size; 128 if (tuple_size <= 0) 129 return (EINVAL); 130 131 /* 132 * Get address/size. XXX we assume only the first 'reg' tuple is used. 133 */ 134 rv = fdt_data_to_res(reg, par_addr_cells, par_size_cells, 135 &start, &size); 136 if (rv != 0) 137 return (rv); 138 start += fdt_immr_va; 139 140 /* 141 * Process 'pin-count' and 'pin-map' props. 142 */ 143 if (OF_getprop(node, "pin-count", &pin_count, sizeof(pin_count)) <= 0) 144 return (ENXIO); 145 pin_count = fdt32_to_cpu(pin_count); 146 if (pin_count > MPP_PIN_MAX) 147 return (ERANGE); 148 149 if (OF_getprop(node, "#pin-cells", &pin_cells, sizeof(pin_cells)) <= 0) 150 pin_cells = MPP_PIN_CELLS; 151 pin_cells = fdt32_to_cpu(pin_cells); 152 if (pin_cells > MPP_PIN_CELLS) 153 return (ERANGE); 154 tuple_size = sizeof(pcell_t) * pin_cells; 155 156 bzero(pinmap, sizeof(pinmap)); 157 len = OF_getprop(node, "pin-map", pinmap, sizeof(pinmap)); 158 if (len <= 0) 159 return (ERANGE); 160 if (len % tuple_size) 161 return (ERANGE); 162 pins = len / tuple_size; 163 if (pins > pin_count) 164 return (ERANGE); 165 /* 166 * Fill out a "mpp[pin] => function" table. All pins unspecified in 167 * the 'pin-map' property are defaulted to 0 function i.e. GPIO. 168 */ 169 bzero(mpp, sizeof(mpp)); 170 pinmap_ptr = pinmap; 171 for (i = 0; i < pins; i++) { 172 mpp_pin = fdt32_to_cpu(*pinmap_ptr); 173 mpp_function = fdt32_to_cpu(*(pinmap_ptr + 1)); 174 mpp[mpp_pin] = mpp_function; 175 pinmap_ptr += pin_cells; 176 } 177 178 /* 179 * Prepare and program MPP control register values. 180 */ 181 ctrl_offset = 0; 182 for (i = 0; i < pin_count;) { 183 ctrl_val = 0; 184 185 for (j = 0; j < MPP_PINS_PER_REG; j++) { 186 if (i + j == pin_count - 1) 187 break; 188 ctrl_val |= MPP_SEL(i + j, mpp[i + j]); 189 } 190 i += MPP_PINS_PER_REG; 191 bus_space_write_4(fdtbus_bs_tag, start, ctrl_offset, 192 ctrl_val); 193 194#if defined(SOC_MV_ORION) 195 /* 196 * Third MPP reg on Orion SoC is placed 197 * non-linearly (with different offset). 198 */ 199 if (i == (2 * MPP_PINS_PER_REG)) 200 ctrl_offset = 0x50; 201 else 202#endif 203 ctrl_offset += 4; 204 } 205 206 return (0); 207} 208 209vm_offset_t 210platform_lastaddr(void) 211{ 212 213 return (fdt_immr_va); 214} 215 216void 217platform_probe_and_attach(void) 218{ 219 220 if (fdt_immr_addr(MV_BASE) != 0) 221 while (1); 222} 223 224void 225platform_gpio_init(void) 226{ 227 228 /* 229 * Re-initialise MPP. It is important to call this prior to using 230 * console as the physical connection can be routed via MPP. 231 */ 232 if (platform_mpp_init() != 0) 233 while (1); 234} 235 236void 237platform_late_init(void) 238{ 239 /* 240 * Re-initialise decode windows 241 */ 242#if !defined(SOC_MV_FREY) 243 if (soc_decode_win() != 0) 244 printf("WARNING: could not re-initialise decode windows! " 245 "Running with existing settings...\n"); 246#else 247 /* Disable watchdog and timers */ 248 write_cpu_ctrl(CPU_TIMERS_BASE + CPU_TIMER_CONTROL, 0); 249#endif 250#if defined(SOC_MV_ARMADAXP) 251#if !defined(SMP) 252 /* For SMP case it should be initialized after APs are booted */ 253 armadaxp_init_coher_fabric(); 254#endif 255 armadaxp_l2_init(); 256#endif 257 258#if defined(SOC_MV_ARMADA38X) 259 /* Set IO Sync Barrier bit for all Mbus devices */ 260 if (armada38x_win_set_iosync_barrier() != 0) 261 printf("WARNING: could not map CPU Subsystem registers\n"); 262 if (armada38x_scu_enable() != 0) 263 printf("WARNING: could not enable SCU\n"); 264#ifdef SMP 265 /* Open window to bootROM memory - needed for SMP */ 266 if (armada38x_open_bootrom_win() != 0) 267 printf("WARNING: could not open window to bootROM\n"); 268#endif 269#endif 270} 271 272#define FDT_DEVMAP_MAX (MV_WIN_CPU_MAX + 2) 273static struct arm_devmap_entry fdt_devmap[FDT_DEVMAP_MAX] = { 274 { 0, 0, 0, 0, 0, } 275}; 276 277static int 278platform_sram_devmap(struct arm_devmap_entry *map) 279{ 280#if !defined(SOC_MV_ARMADAXP) 281 phandle_t child, root; 282 u_long base, size; 283 /* 284 * SRAM range. 285 */ 286 if ((child = OF_finddevice("/sram")) != 0) 287 if (fdt_is_compatible(child, "mrvl,cesa-sram") || 288 fdt_is_compatible(child, "mrvl,scratchpad")) 289 goto moveon; 290 291 if ((root = OF_finddevice("/")) == 0) 292 return (ENXIO); 293 294 if ((child = fdt_find_compatible(root, "mrvl,cesa-sram", 0)) == 0 && 295 (child = fdt_find_compatible(root, "mrvl,scratchpad", 0)) == 0) 296 goto out; 297 298moveon: 299 if (fdt_regsize(child, &base, &size) != 0) 300 return (EINVAL); 301 302 map->pd_va = MV_CESA_SRAM_BASE; /* XXX */ 303 map->pd_pa = base; 304 map->pd_size = size; 305 map->pd_prot = VM_PROT_READ | VM_PROT_WRITE; 306 map->pd_cache = PTE_DEVICE; 307 308 return (0); 309out: 310#endif 311 return (ENOENT); 312 313} 314 315/* 316 * Supply a default do-nothing implementation of mv_pci_devmap() via a weak 317 * alias. Many Marvell platforms don't support a PCI interface, but to support 318 * those that do, we end up with a reference to this function below, in 319 * platform_devmap_init(). If "device pci" appears in the kernel config, the 320 * real implementation of this function in arm/mv/mv_pci.c overrides the weak 321 * alias defined here. 322 */ 323int mv_default_fdt_pci_devmap(phandle_t node, struct arm_devmap_entry *devmap, 324 vm_offset_t io_va, vm_offset_t mem_va); 325int 326mv_default_fdt_pci_devmap(phandle_t node, struct arm_devmap_entry *devmap, 327 vm_offset_t io_va, vm_offset_t mem_va) 328{ 329 330 return (0); 331} 332__weak_reference(mv_default_fdt_pci_devmap, mv_pci_devmap); 333 334/* 335 * XXX: When device entry in devmap has pd_size smaller than section size, 336 * system will freeze during initialization 337 */ 338 339/* 340 * Construct devmap table with DT-derived config data. 341 */ 342int 343platform_devmap_init(void) 344{ 345 phandle_t root, child; 346 pcell_t bank_count; 347 int i, num_mapped; 348 349 i = 0; 350 arm_devmap_register_table(&fdt_devmap[0]); 351 352#ifdef SOC_MV_ARMADAXP 353 vm_paddr_t cur_immr_pa; 354 355 /* 356 * Acquire SoC registers' base passed by u-boot and fill devmap 357 * accordingly. DTB is going to be modified basing on this data 358 * later. 359 */ 360 __asm __volatile("mrc p15, 4, %0, c15, c0, 0" : "=r" (cur_immr_pa)); 361 cur_immr_pa = (cur_immr_pa << 13) & 0xff000000; 362 if (cur_immr_pa != 0) 363 fdt_immr_pa = cur_immr_pa; 364#endif 365 /* 366 * IMMR range. 367 */ 368 fdt_devmap[i].pd_va = fdt_immr_va; 369 fdt_devmap[i].pd_pa = fdt_immr_pa; 370 fdt_devmap[i].pd_size = fdt_immr_size; 371 fdt_devmap[i].pd_prot = VM_PROT_READ | VM_PROT_WRITE; 372 fdt_devmap[i].pd_cache = PTE_DEVICE; 373 i++; 374 375 /* 376 * SRAM range. 377 */ 378 if (i < FDT_DEVMAP_MAX) 379 if (platform_sram_devmap(&fdt_devmap[i]) == 0) 380 i++; 381 382 /* 383 * PCI range(s). 384 * PCI range(s) and localbus. 385 */ 386 if ((root = OF_finddevice("/")) == -1) 387 return (ENXIO); 388 for (child = OF_child(root); child != 0; child = OF_peer(child)) { 389 if (fdt_is_type(child, "pci") || fdt_is_type(child, "pciep")) { 390 /* 391 * Check space: each PCI node will consume 2 devmap 392 * entries. 393 */ 394 if (i + 1 >= FDT_DEVMAP_MAX) 395 return (ENOMEM); 396 397 /* 398 * XXX this should account for PCI and multiple ranges 399 * of a given kind. 400 */ 401 if (mv_pci_devmap(child, &fdt_devmap[i], MV_PCI_VA_IO_BASE, 402 MV_PCI_VA_MEM_BASE) != 0) 403 return (ENXIO); 404 i += 2; 405 } 406 407 if (fdt_is_compatible(child, "mrvl,lbc")) { 408 /* Check available space */ 409 if (OF_getprop(child, "bank-count", (void *)&bank_count, 410 sizeof(bank_count)) <= 0) 411 /* If no property, use default value */ 412 bank_count = 1; 413 else 414 bank_count = fdt32_to_cpu(bank_count); 415 416 if ((i + bank_count) >= FDT_DEVMAP_MAX) 417 return (ENOMEM); 418 419 /* Add all localbus ranges to device map */ 420 num_mapped = 0; 421 422 if (fdt_localbus_devmap(child, &fdt_devmap[i], 423 (int)bank_count, &num_mapped) != 0) 424 return (ENXIO); 425 426 i += num_mapped; 427 } 428 } 429 430 return (0); 431} 432 433struct arm32_dma_range * 434bus_dma_get_range(void) 435{ 436 437 return (NULL); 438} 439 440int 441bus_dma_get_range_nb(void) 442{ 443 444 return (0); 445} 446 447#if defined(CPU_MV_PJ4B) 448#ifdef DDB 449#include <ddb/ddb.h> 450 451DB_SHOW_COMMAND(cp15, db_show_cp15) 452{ 453 u_int reg; 454 455 __asm __volatile("mrc p15, 0, %0, c0, c0, 0" : "=r" (reg)); 456 db_printf("Cpu ID: 0x%08x\n", reg); 457 __asm __volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (reg)); 458 db_printf("Current Cache Lvl ID: 0x%08x\n",reg); 459 460 __asm __volatile("mrc p15, 0, %0, c1, c0, 0" : "=r" (reg)); 461 db_printf("Ctrl: 0x%08x\n",reg); 462 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (reg)); 463 db_printf("Aux Ctrl: 0x%08x\n",reg); 464 465 __asm __volatile("mrc p15, 0, %0, c0, c1, 0" : "=r" (reg)); 466 db_printf("Processor Feat 0: 0x%08x\n", reg); 467 __asm __volatile("mrc p15, 0, %0, c0, c1, 1" : "=r" (reg)); 468 db_printf("Processor Feat 1: 0x%08x\n", reg); 469 __asm __volatile("mrc p15, 0, %0, c0, c1, 2" : "=r" (reg)); 470 db_printf("Debug Feat 0: 0x%08x\n", reg); 471 __asm __volatile("mrc p15, 0, %0, c0, c1, 3" : "=r" (reg)); 472 db_printf("Auxiliary Feat 0: 0x%08x\n", reg); 473 __asm __volatile("mrc p15, 0, %0, c0, c1, 4" : "=r" (reg)); 474 db_printf("Memory Model Feat 0: 0x%08x\n", reg); 475 __asm __volatile("mrc p15, 0, %0, c0, c1, 5" : "=r" (reg)); 476 db_printf("Memory Model Feat 1: 0x%08x\n", reg); 477 __asm __volatile("mrc p15, 0, %0, c0, c1, 6" : "=r" (reg)); 478 db_printf("Memory Model Feat 2: 0x%08x\n", reg); 479 __asm __volatile("mrc p15, 0, %0, c0, c1, 7" : "=r" (reg)); 480 db_printf("Memory Model Feat 3: 0x%08x\n", reg); 481 482 __asm __volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (reg)); 483 db_printf("Aux Func Modes Ctrl 0: 0x%08x\n",reg); 484 __asm __volatile("mrc p15, 1, %0, c15, c2, 1" : "=r" (reg)); 485 db_printf("Aux Func Modes Ctrl 1: 0x%08x\n",reg); 486 487 __asm __volatile("mrc p15, 1, %0, c15, c12, 0" : "=r" (reg)); 488 db_printf("CPU ID code extension: 0x%08x\n",reg); 489} 490 491DB_SHOW_COMMAND(vtop, db_show_vtop) 492{ 493 u_int reg; 494 495 if (have_addr) { 496 __asm __volatile("mcr p15, 0, %0, c7, c8, 0" : : "r" (addr)); 497 __asm __volatile("mrc p15, 0, %0, c7, c4, 0" : "=r" (reg)); 498 db_printf("Physical address reg: 0x%08x\n",reg); 499 } else 500 db_printf("show vtop <virt_addr>\n"); 501} 502#endif /* DDB */ 503#endif /* CPU_MV_PJ4B */ 504 505