mv_machdep.c revision 294425
1/*- 2 * Copyright (c) 1994-1998 Mark Brinicombe. 3 * Copyright (c) 1994 Brini. 4 * All rights reserved. 5 * 6 * This code is derived from software written for Brini by Mark Brinicombe 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45 36 */ 37 38#include "opt_ddb.h" 39#include "opt_platform.h" 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: head/sys/arm/mv/mv_machdep.c 294425 2016-01-20 13:53:33Z zbb $"); 43 44#define _ARM32_BUS_DMA_PRIVATE 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/bus.h> 48 49#include <vm/vm.h> 50#include <vm/pmap.h> 51 52#include <machine/bus.h> 53#include <machine/devmap.h> 54#include <machine/fdt.h> 55#include <machine/machdep.h> 56#include <machine/platform.h> 57 58#include <arm/mv/mvreg.h> /* XXX */ 59#include <arm/mv/mvvar.h> /* XXX eventually this should be eliminated */ 60#include <arm/mv/mvwin.h> 61 62#include <dev/fdt/fdt_common.h> 63 64static int platform_mpp_init(void); 65#if defined(SOC_MV_ARMADAXP) 66void armadaxp_init_coher_fabric(void); 67void armadaxp_l2_init(void); 68#endif 69#if defined(SOC_MV_ARMADA38X) 70int armada38x_win_set_iosync_barrier(void); 71#endif 72 73#define MPP_PIN_MAX 68 74#define MPP_PIN_CELLS 2 75#define MPP_PINS_PER_REG 8 76#define MPP_SEL(pin,func) (((func) & 0xf) << \ 77 (((pin) % MPP_PINS_PER_REG) * 4)) 78 79static int 80platform_mpp_init(void) 81{ 82 pcell_t pinmap[MPP_PIN_MAX * MPP_PIN_CELLS]; 83 int mpp[MPP_PIN_MAX]; 84 uint32_t ctrl_val, ctrl_offset; 85 pcell_t reg[4]; 86 u_long start, size; 87 phandle_t node; 88 pcell_t pin_cells, *pinmap_ptr, pin_count; 89 ssize_t len; 90 int par_addr_cells, par_size_cells; 91 int tuple_size, tuples, rv, pins, i, j; 92 int mpp_pin, mpp_function; 93 94 /* 95 * Try to access the MPP node directly i.e. through /aliases/mpp. 96 */ 97 if ((node = OF_finddevice("mpp")) != -1) 98 if (fdt_is_compatible(node, "mrvl,mpp")) 99 goto moveon; 100 /* 101 * Find the node the long way. 102 */ 103 if ((node = OF_finddevice("/")) == -1) 104 return (ENXIO); 105 106 if ((node = fdt_find_compatible(node, "simple-bus", 0)) == 0) 107 return (ENXIO); 108 109 if ((node = fdt_find_compatible(node, "mrvl,mpp", 0)) == 0) 110 /* 111 * No MPP node. Fall back to how MPP got set by the 112 * first-stage loader and try to continue booting. 113 */ 114 return (0); 115moveon: 116 /* 117 * Process 'reg' prop. 118 */ 119 if ((rv = fdt_addrsize_cells(OF_parent(node), &par_addr_cells, 120 &par_size_cells)) != 0) 121 return(ENXIO); 122 123 tuple_size = sizeof(pcell_t) * (par_addr_cells + par_size_cells); 124 len = OF_getprop(node, "reg", reg, sizeof(reg)); 125 tuples = len / tuple_size; 126 if (tuple_size <= 0) 127 return (EINVAL); 128 129 /* 130 * Get address/size. XXX we assume only the first 'reg' tuple is used. 131 */ 132 rv = fdt_data_to_res(reg, par_addr_cells, par_size_cells, 133 &start, &size); 134 if (rv != 0) 135 return (rv); 136 start += fdt_immr_va; 137 138 /* 139 * Process 'pin-count' and 'pin-map' props. 140 */ 141 if (OF_getprop(node, "pin-count", &pin_count, sizeof(pin_count)) <= 0) 142 return (ENXIO); 143 pin_count = fdt32_to_cpu(pin_count); 144 if (pin_count > MPP_PIN_MAX) 145 return (ERANGE); 146 147 if (OF_getprop(node, "#pin-cells", &pin_cells, sizeof(pin_cells)) <= 0) 148 pin_cells = MPP_PIN_CELLS; 149 pin_cells = fdt32_to_cpu(pin_cells); 150 if (pin_cells > MPP_PIN_CELLS) 151 return (ERANGE); 152 tuple_size = sizeof(pcell_t) * pin_cells; 153 154 bzero(pinmap, sizeof(pinmap)); 155 len = OF_getprop(node, "pin-map", pinmap, sizeof(pinmap)); 156 if (len <= 0) 157 return (ERANGE); 158 if (len % tuple_size) 159 return (ERANGE); 160 pins = len / tuple_size; 161 if (pins > pin_count) 162 return (ERANGE); 163 /* 164 * Fill out a "mpp[pin] => function" table. All pins unspecified in 165 * the 'pin-map' property are defaulted to 0 function i.e. GPIO. 166 */ 167 bzero(mpp, sizeof(mpp)); 168 pinmap_ptr = pinmap; 169 for (i = 0; i < pins; i++) { 170 mpp_pin = fdt32_to_cpu(*pinmap_ptr); 171 mpp_function = fdt32_to_cpu(*(pinmap_ptr + 1)); 172 mpp[mpp_pin] = mpp_function; 173 pinmap_ptr += pin_cells; 174 } 175 176 /* 177 * Prepare and program MPP control register values. 178 */ 179 ctrl_offset = 0; 180 for (i = 0; i < pin_count;) { 181 ctrl_val = 0; 182 183 for (j = 0; j < MPP_PINS_PER_REG; j++) { 184 if (i + j == pin_count - 1) 185 break; 186 ctrl_val |= MPP_SEL(i + j, mpp[i + j]); 187 } 188 i += MPP_PINS_PER_REG; 189 bus_space_write_4(fdtbus_bs_tag, start, ctrl_offset, 190 ctrl_val); 191 192#if defined(SOC_MV_ORION) 193 /* 194 * Third MPP reg on Orion SoC is placed 195 * non-linearly (with different offset). 196 */ 197 if (i == (2 * MPP_PINS_PER_REG)) 198 ctrl_offset = 0x50; 199 else 200#endif 201 ctrl_offset += 4; 202 } 203 204 return (0); 205} 206 207vm_offset_t 208platform_lastaddr(void) 209{ 210 211 return (fdt_immr_va); 212} 213 214void 215platform_probe_and_attach(void) 216{ 217 218 if (fdt_immr_addr(MV_BASE) != 0) 219 while (1); 220} 221 222void 223platform_gpio_init(void) 224{ 225 226 /* 227 * Re-initialise MPP. It is important to call this prior to using 228 * console as the physical connection can be routed via MPP. 229 */ 230 if (platform_mpp_init() != 0) 231 while (1); 232} 233 234void 235platform_late_init(void) 236{ 237 /* 238 * Re-initialise decode windows 239 */ 240#if !defined(SOC_MV_FREY) 241 if (soc_decode_win() != 0) 242 printf("WARNING: could not re-initialise decode windows! " 243 "Running with existing settings...\n"); 244#else 245 /* Disable watchdog and timers */ 246 write_cpu_ctrl(CPU_TIMERS_BASE + CPU_TIMER_CONTROL, 0); 247#endif 248#if defined(SOC_MV_ARMADAXP) 249#if !defined(SMP) 250 /* For SMP case it should be initialized after APs are booted */ 251 armadaxp_init_coher_fabric(); 252#endif 253 armadaxp_l2_init(); 254#endif 255 256#if defined(SOC_MV_ARMADA38X) 257 /* Set IO Sync Barrier bit for all Mbus devices */ 258 if (armada38x_win_set_iosync_barrier() != 0) 259 printf("WARNING: could not map CPU Subsystem registers\n"); 260#endif 261} 262 263#define FDT_DEVMAP_MAX (MV_WIN_CPU_MAX + 2) 264static struct arm_devmap_entry fdt_devmap[FDT_DEVMAP_MAX] = { 265 { 0, 0, 0, 0, 0, } 266}; 267 268static int 269platform_sram_devmap(struct arm_devmap_entry *map) 270{ 271#if !defined(SOC_MV_ARMADAXP) 272 phandle_t child, root; 273 u_long base, size; 274 /* 275 * SRAM range. 276 */ 277 if ((child = OF_finddevice("/sram")) != 0) 278 if (fdt_is_compatible(child, "mrvl,cesa-sram") || 279 fdt_is_compatible(child, "mrvl,scratchpad")) 280 goto moveon; 281 282 if ((root = OF_finddevice("/")) == 0) 283 return (ENXIO); 284 285 if ((child = fdt_find_compatible(root, "mrvl,cesa-sram", 0)) == 0 && 286 (child = fdt_find_compatible(root, "mrvl,scratchpad", 0)) == 0) 287 goto out; 288 289moveon: 290 if (fdt_regsize(child, &base, &size) != 0) 291 return (EINVAL); 292 293 map->pd_va = MV_CESA_SRAM_BASE; /* XXX */ 294 map->pd_pa = base; 295 map->pd_size = size; 296 map->pd_prot = VM_PROT_READ | VM_PROT_WRITE; 297 map->pd_cache = PTE_DEVICE; 298 299 return (0); 300out: 301#endif 302 return (ENOENT); 303 304} 305 306/* 307 * Supply a default do-nothing implementation of mv_pci_devmap() via a weak 308 * alias. Many Marvell platforms don't support a PCI interface, but to support 309 * those that do, we end up with a reference to this function below, in 310 * platform_devmap_init(). If "device pci" appears in the kernel config, the 311 * real implementation of this function in arm/mv/mv_pci.c overrides the weak 312 * alias defined here. 313 */ 314int mv_default_fdt_pci_devmap(phandle_t node, struct arm_devmap_entry *devmap, 315 vm_offset_t io_va, vm_offset_t mem_va); 316int 317mv_default_fdt_pci_devmap(phandle_t node, struct arm_devmap_entry *devmap, 318 vm_offset_t io_va, vm_offset_t mem_va) 319{ 320 321 return (0); 322} 323__weak_reference(mv_default_fdt_pci_devmap, mv_pci_devmap); 324 325/* 326 * XXX: When device entry in devmap has pd_size smaller than section size, 327 * system will freeze during initialization 328 */ 329 330/* 331 * Construct pmap_devmap[] with DT-derived config data. 332 */ 333int 334platform_devmap_init(void) 335{ 336 phandle_t root, child; 337 pcell_t bank_count; 338 int i, num_mapped; 339 340 i = 0; 341 arm_devmap_register_table(&fdt_devmap[0]); 342 343#ifdef SOC_MV_ARMADAXP 344 vm_paddr_t cur_immr_pa; 345 346 /* 347 * Acquire SoC registers' base passed by u-boot and fill devmap 348 * accordingly. DTB is going to be modified basing on this data 349 * later. 350 */ 351 __asm __volatile("mrc p15, 4, %0, c15, c0, 0" : "=r" (cur_immr_pa)); 352 cur_immr_pa = (cur_immr_pa << 13) & 0xff000000; 353 if (cur_immr_pa != 0) 354 fdt_immr_pa = cur_immr_pa; 355#endif 356 /* 357 * IMMR range. 358 */ 359 fdt_devmap[i].pd_va = fdt_immr_va; 360 fdt_devmap[i].pd_pa = fdt_immr_pa; 361 fdt_devmap[i].pd_size = fdt_immr_size; 362 fdt_devmap[i].pd_prot = VM_PROT_READ | VM_PROT_WRITE; 363 fdt_devmap[i].pd_cache = PTE_DEVICE; 364 i++; 365 366 /* 367 * SRAM range. 368 */ 369 if (i < FDT_DEVMAP_MAX) 370 if (platform_sram_devmap(&fdt_devmap[i]) == 0) 371 i++; 372 373 /* 374 * PCI range(s). 375 * PCI range(s) and localbus. 376 */ 377 if ((root = OF_finddevice("/")) == -1) 378 return (ENXIO); 379 for (child = OF_child(root); child != 0; child = OF_peer(child)) { 380 if (fdt_is_type(child, "pci") || fdt_is_type(child, "pciep")) { 381 /* 382 * Check space: each PCI node will consume 2 devmap 383 * entries. 384 */ 385 if (i + 1 >= FDT_DEVMAP_MAX) 386 return (ENOMEM); 387 388 /* 389 * XXX this should account for PCI and multiple ranges 390 * of a given kind. 391 */ 392 if (mv_pci_devmap(child, &fdt_devmap[i], MV_PCI_VA_IO_BASE, 393 MV_PCI_VA_MEM_BASE) != 0) 394 return (ENXIO); 395 i += 2; 396 } 397 398 if (fdt_is_compatible(child, "mrvl,lbc")) { 399 /* Check available space */ 400 if (OF_getprop(child, "bank-count", (void *)&bank_count, 401 sizeof(bank_count)) <= 0) 402 /* If no property, use default value */ 403 bank_count = 1; 404 else 405 bank_count = fdt32_to_cpu(bank_count); 406 407 if ((i + bank_count) >= FDT_DEVMAP_MAX) 408 return (ENOMEM); 409 410 /* Add all localbus ranges to device map */ 411 num_mapped = 0; 412 413 if (fdt_localbus_devmap(child, &fdt_devmap[i], 414 (int)bank_count, &num_mapped) != 0) 415 return (ENXIO); 416 417 i += num_mapped; 418 } 419 } 420 421 return (0); 422} 423 424struct arm32_dma_range * 425bus_dma_get_range(void) 426{ 427 428 return (NULL); 429} 430 431int 432bus_dma_get_range_nb(void) 433{ 434 435 return (0); 436} 437 438#if defined(CPU_MV_PJ4B) 439#ifdef DDB 440#include <ddb/ddb.h> 441 442DB_SHOW_COMMAND(cp15, db_show_cp15) 443{ 444 u_int reg; 445 446 __asm __volatile("mrc p15, 0, %0, c0, c0, 0" : "=r" (reg)); 447 db_printf("Cpu ID: 0x%08x\n", reg); 448 __asm __volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (reg)); 449 db_printf("Current Cache Lvl ID: 0x%08x\n",reg); 450 451 __asm __volatile("mrc p15, 0, %0, c1, c0, 0" : "=r" (reg)); 452 db_printf("Ctrl: 0x%08x\n",reg); 453 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (reg)); 454 db_printf("Aux Ctrl: 0x%08x\n",reg); 455 456 __asm __volatile("mrc p15, 0, %0, c0, c1, 0" : "=r" (reg)); 457 db_printf("Processor Feat 0: 0x%08x\n", reg); 458 __asm __volatile("mrc p15, 0, %0, c0, c1, 1" : "=r" (reg)); 459 db_printf("Processor Feat 1: 0x%08x\n", reg); 460 __asm __volatile("mrc p15, 0, %0, c0, c1, 2" : "=r" (reg)); 461 db_printf("Debug Feat 0: 0x%08x\n", reg); 462 __asm __volatile("mrc p15, 0, %0, c0, c1, 3" : "=r" (reg)); 463 db_printf("Auxiliary Feat 0: 0x%08x\n", reg); 464 __asm __volatile("mrc p15, 0, %0, c0, c1, 4" : "=r" (reg)); 465 db_printf("Memory Model Feat 0: 0x%08x\n", reg); 466 __asm __volatile("mrc p15, 0, %0, c0, c1, 5" : "=r" (reg)); 467 db_printf("Memory Model Feat 1: 0x%08x\n", reg); 468 __asm __volatile("mrc p15, 0, %0, c0, c1, 6" : "=r" (reg)); 469 db_printf("Memory Model Feat 2: 0x%08x\n", reg); 470 __asm __volatile("mrc p15, 0, %0, c0, c1, 7" : "=r" (reg)); 471 db_printf("Memory Model Feat 3: 0x%08x\n", reg); 472 473 __asm __volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (reg)); 474 db_printf("Aux Func Modes Ctrl 0: 0x%08x\n",reg); 475 __asm __volatile("mrc p15, 1, %0, c15, c2, 1" : "=r" (reg)); 476 db_printf("Aux Func Modes Ctrl 1: 0x%08x\n",reg); 477 478 __asm __volatile("mrc p15, 1, %0, c15, c12, 0" : "=r" (reg)); 479 db_printf("CPU ID code extension: 0x%08x\n",reg); 480} 481 482DB_SHOW_COMMAND(vtop, db_show_vtop) 483{ 484 u_int reg; 485 486 if (have_addr) { 487 __asm __volatile("mcr p15, 0, %0, c7, c8, 0" : : "r" (addr)); 488 __asm __volatile("mrc p15, 0, %0, c7, c4, 0" : "=r" (reg)); 489 db_printf("Physical address reg: 0x%08x\n",reg); 490 } else 491 db_printf("show vtop <virt_addr>\n"); 492} 493#endif /* DDB */ 494#endif /* CPU_MV_PJ4B */ 495 496