mv_machdep.c revision 266301
1/*- 2 * Copyright (c) 1994-1998 Mark Brinicombe. 3 * Copyright (c) 1994 Brini. 4 * All rights reserved. 5 * 6 * This code is derived from software written for Brini by Mark Brinicombe 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45 36 */ 37 38#include "opt_ddb.h" 39#include "opt_platform.h" 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: head/sys/arm/mv/mv_machdep.c 266301 2014-05-17 11:27:36Z andrew $"); 43 44#define _ARM32_BUS_DMA_PRIVATE 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/bus.h> 48 49#include <vm/vm.h> 50#include <vm/pmap.h> 51 52#include <machine/bus.h> 53#include <machine/devmap.h> 54#include <machine/fdt.h> 55#include <machine/machdep.h> 56#include <machine/platform.h> 57 58#include <arm/mv/mvreg.h> /* XXX */ 59#include <arm/mv/mvvar.h> /* XXX eventually this should be eliminated */ 60#include <arm/mv/mvwin.h> 61 62#include <dev/fdt/fdt_common.h> 63 64static int platform_mpp_init(void); 65#if defined(SOC_MV_ARMADAXP) 66void armadaxp_init_coher_fabric(void); 67void armadaxp_l2_init(void); 68#endif 69 70#define MPP_PIN_MAX 68 71#define MPP_PIN_CELLS 2 72#define MPP_PINS_PER_REG 8 73#define MPP_SEL(pin,func) (((func) & 0xf) << \ 74 (((pin) % MPP_PINS_PER_REG) * 4)) 75 76static int 77platform_mpp_init(void) 78{ 79 pcell_t pinmap[MPP_PIN_MAX * MPP_PIN_CELLS]; 80 int mpp[MPP_PIN_MAX]; 81 uint32_t ctrl_val, ctrl_offset; 82 pcell_t reg[4]; 83 u_long start, size; 84 phandle_t node; 85 pcell_t pin_cells, *pinmap_ptr, pin_count; 86 ssize_t len; 87 int par_addr_cells, par_size_cells; 88 int tuple_size, tuples, rv, pins, i, j; 89 int mpp_pin, mpp_function; 90 91 /* 92 * Try to access the MPP node directly i.e. through /aliases/mpp. 93 */ 94 if ((node = OF_finddevice("mpp")) != -1) 95 if (fdt_is_compatible(node, "mrvl,mpp")) 96 goto moveon; 97 /* 98 * Find the node the long way. 99 */ 100 if ((node = OF_finddevice("/")) == -1) 101 return (ENXIO); 102 103 if ((node = fdt_find_compatible(node, "simple-bus", 0)) == 0) 104 return (ENXIO); 105 106 if ((node = fdt_find_compatible(node, "mrvl,mpp", 0)) == 0) 107 /* 108 * No MPP node. Fall back to how MPP got set by the 109 * first-stage loader and try to continue booting. 110 */ 111 return (0); 112moveon: 113 /* 114 * Process 'reg' prop. 115 */ 116 if ((rv = fdt_addrsize_cells(OF_parent(node), &par_addr_cells, 117 &par_size_cells)) != 0) 118 return(ENXIO); 119 120 tuple_size = sizeof(pcell_t) * (par_addr_cells + par_size_cells); 121 len = OF_getprop(node, "reg", reg, sizeof(reg)); 122 tuples = len / tuple_size; 123 if (tuple_size <= 0) 124 return (EINVAL); 125 126 /* 127 * Get address/size. XXX we assume only the first 'reg' tuple is used. 128 */ 129 rv = fdt_data_to_res(reg, par_addr_cells, par_size_cells, 130 &start, &size); 131 if (rv != 0) 132 return (rv); 133 start += fdt_immr_va; 134 135 /* 136 * Process 'pin-count' and 'pin-map' props. 137 */ 138 if (OF_getprop(node, "pin-count", &pin_count, sizeof(pin_count)) <= 0) 139 return (ENXIO); 140 pin_count = fdt32_to_cpu(pin_count); 141 if (pin_count > MPP_PIN_MAX) 142 return (ERANGE); 143 144 if (OF_getprop(node, "#pin-cells", &pin_cells, sizeof(pin_cells)) <= 0) 145 pin_cells = MPP_PIN_CELLS; 146 pin_cells = fdt32_to_cpu(pin_cells); 147 if (pin_cells > MPP_PIN_CELLS) 148 return (ERANGE); 149 tuple_size = sizeof(pcell_t) * pin_cells; 150 151 bzero(pinmap, sizeof(pinmap)); 152 len = OF_getprop(node, "pin-map", pinmap, sizeof(pinmap)); 153 if (len <= 0) 154 return (ERANGE); 155 if (len % tuple_size) 156 return (ERANGE); 157 pins = len / tuple_size; 158 if (pins > pin_count) 159 return (ERANGE); 160 /* 161 * Fill out a "mpp[pin] => function" table. All pins unspecified in 162 * the 'pin-map' property are defaulted to 0 function i.e. GPIO. 163 */ 164 bzero(mpp, sizeof(mpp)); 165 pinmap_ptr = pinmap; 166 for (i = 0; i < pins; i++) { 167 mpp_pin = fdt32_to_cpu(*pinmap_ptr); 168 mpp_function = fdt32_to_cpu(*(pinmap_ptr + 1)); 169 mpp[mpp_pin] = mpp_function; 170 pinmap_ptr += pin_cells; 171 } 172 173 /* 174 * Prepare and program MPP control register values. 175 */ 176 ctrl_offset = 0; 177 for (i = 0; i < pin_count;) { 178 ctrl_val = 0; 179 180 for (j = 0; j < MPP_PINS_PER_REG; j++) { 181 if (i + j == pin_count - 1) 182 break; 183 ctrl_val |= MPP_SEL(i + j, mpp[i + j]); 184 } 185 i += MPP_PINS_PER_REG; 186 bus_space_write_4(fdtbus_bs_tag, start, ctrl_offset, 187 ctrl_val); 188 189#if defined(SOC_MV_ORION) 190 /* 191 * Third MPP reg on Orion SoC is placed 192 * non-linearly (with different offset). 193 */ 194 if (i == (2 * MPP_PINS_PER_REG)) 195 ctrl_offset = 0x50; 196 else 197#endif 198 ctrl_offset += 4; 199 } 200 201 return (0); 202} 203 204vm_offset_t 205platform_lastaddr(void) 206{ 207 208 return (fdt_immr_va); 209} 210 211void 212platform_probe_and_attach(void) 213{ 214 215 if (fdt_immr_addr(MV_BASE) != 0) 216 while (1); 217} 218 219void 220platform_gpio_init(void) 221{ 222 223 /* 224 * Re-initialise MPP. It is important to call this prior to using 225 * console as the physical connection can be routed via MPP. 226 */ 227 if (platform_mpp_init() != 0) 228 while (1); 229} 230 231void 232platform_late_init(void) 233{ 234 /* 235 * Re-initialise decode windows 236 */ 237#if !defined(SOC_MV_FREY) 238 if (soc_decode_win() != 0) 239 printf("WARNING: could not re-initialise decode windows! " 240 "Running with existing settings...\n"); 241#else 242 /* Disable watchdog and timers */ 243 write_cpu_ctrl(CPU_TIMERS_BASE + CPU_TIMER_CONTROL, 0); 244#endif 245#if defined(SOC_MV_ARMADAXP) 246#if !defined(SMP) 247 /* For SMP case it should be initialized after APs are booted */ 248 armadaxp_init_coher_fabric(); 249#endif 250 armadaxp_l2_init(); 251#endif 252} 253 254#define FDT_DEVMAP_MAX (MV_WIN_CPU_MAX + 2) 255static struct arm_devmap_entry fdt_devmap[FDT_DEVMAP_MAX] = { 256 { 0, 0, 0, 0, 0, } 257}; 258 259static int 260platform_sram_devmap(struct arm_devmap_entry *map) 261{ 262#if !defined(SOC_MV_ARMADAXP) 263 phandle_t child, root; 264 u_long base, size; 265 /* 266 * SRAM range. 267 */ 268 if ((child = OF_finddevice("/sram")) != 0) 269 if (fdt_is_compatible(child, "mrvl,cesa-sram") || 270 fdt_is_compatible(child, "mrvl,scratchpad")) 271 goto moveon; 272 273 if ((root = OF_finddevice("/")) == 0) 274 return (ENXIO); 275 276 if ((child = fdt_find_compatible(root, "mrvl,cesa-sram", 0)) == 0 && 277 (child = fdt_find_compatible(root, "mrvl,scratchpad", 0)) == 0) 278 goto out; 279 280moveon: 281 if (fdt_regsize(child, &base, &size) != 0) 282 return (EINVAL); 283 284 map->pd_va = MV_CESA_SRAM_BASE; /* XXX */ 285 map->pd_pa = base; 286 map->pd_size = size; 287 map->pd_prot = VM_PROT_READ | VM_PROT_WRITE; 288 map->pd_cache = PTE_DEVICE; 289 290 return (0); 291out: 292#endif 293 return (ENOENT); 294 295} 296 297/* 298 * Supply a default do-nothing implementation of mv_pci_devmap() via a weak 299 * alias. Many Marvell platforms don't support a PCI interface, but to support 300 * those that do, we end up with a reference to this function below, in 301 * platform_devmap_init(). If "device pci" appears in the kernel config, the 302 * real implementation of this function in arm/mv/mv_pci.c overrides the weak 303 * alias defined here. 304 */ 305int mv_default_fdt_pci_devmap(phandle_t node, struct arm_devmap_entry *devmap, 306 vm_offset_t io_va, vm_offset_t mem_va); 307int 308mv_default_fdt_pci_devmap(phandle_t node, struct arm_devmap_entry *devmap, 309 vm_offset_t io_va, vm_offset_t mem_va) 310{ 311 312 return (0); 313} 314__weak_reference(mv_default_fdt_pci_devmap, mv_pci_devmap); 315 316/* 317 * XXX: When device entry in devmap has pd_size smaller than section size, 318 * system will freeze during initialization 319 */ 320 321/* 322 * Construct pmap_devmap[] with DT-derived config data. 323 */ 324int 325platform_devmap_init(void) 326{ 327 phandle_t root, child; 328 pcell_t bank_count; 329 int i, num_mapped; 330 331 i = 0; 332 arm_devmap_register_table(&fdt_devmap[0]); 333 334#ifdef SOC_MV_ARMADAXP 335 vm_paddr_t cur_immr_pa; 336 337 /* 338 * Acquire SoC registers' base passed by u-boot and fill devmap 339 * accordingly. DTB is going to be modified basing on this data 340 * later. 341 */ 342 __asm __volatile("mrc p15, 4, %0, c15, c0, 0" : "=r" (cur_immr_pa)); 343 cur_immr_pa = (cur_immr_pa << 13) & 0xff000000; 344 if (cur_immr_pa != 0) 345 fdt_immr_pa = cur_immr_pa; 346#endif 347 /* 348 * IMMR range. 349 */ 350 fdt_devmap[i].pd_va = fdt_immr_va; 351 fdt_devmap[i].pd_pa = fdt_immr_pa; 352 fdt_devmap[i].pd_size = fdt_immr_size; 353 fdt_devmap[i].pd_prot = VM_PROT_READ | VM_PROT_WRITE; 354 fdt_devmap[i].pd_cache = PTE_DEVICE; 355 i++; 356 357 /* 358 * SRAM range. 359 */ 360 if (i < FDT_DEVMAP_MAX) 361 if (platform_sram_devmap(&fdt_devmap[i]) == 0) 362 i++; 363 364 /* 365 * PCI range(s). 366 * PCI range(s) and localbus. 367 */ 368 if ((root = OF_finddevice("/")) == -1) 369 return (ENXIO); 370 for (child = OF_child(root); child != 0; child = OF_peer(child)) { 371 if (fdt_is_type(child, "pci") || fdt_is_type(child, "pciep")) { 372 /* 373 * Check space: each PCI node will consume 2 devmap 374 * entries. 375 */ 376 if (i + 1 >= FDT_DEVMAP_MAX) 377 return (ENOMEM); 378 379 /* 380 * XXX this should account for PCI and multiple ranges 381 * of a given kind. 382 */ 383 if (mv_pci_devmap(child, &fdt_devmap[i], MV_PCI_VA_IO_BASE, 384 MV_PCI_VA_MEM_BASE) != 0) 385 return (ENXIO); 386 i += 2; 387 } 388 389 if (fdt_is_compatible(child, "mrvl,lbc")) { 390 /* Check available space */ 391 if (OF_getprop(child, "bank-count", (void *)&bank_count, 392 sizeof(bank_count)) <= 0) 393 /* If no property, use default value */ 394 bank_count = 1; 395 else 396 bank_count = fdt32_to_cpu(bank_count); 397 398 if ((i + bank_count) >= FDT_DEVMAP_MAX) 399 return (ENOMEM); 400 401 /* Add all localbus ranges to device map */ 402 num_mapped = 0; 403 404 if (fdt_localbus_devmap(child, &fdt_devmap[i], 405 (int)bank_count, &num_mapped) != 0) 406 return (ENXIO); 407 408 i += num_mapped; 409 } 410 } 411 412 return (0); 413} 414 415struct arm32_dma_range * 416bus_dma_get_range(void) 417{ 418 419 return (NULL); 420} 421 422int 423bus_dma_get_range_nb(void) 424{ 425 426 return (0); 427} 428 429#if defined(CPU_MV_PJ4B) 430#ifdef DDB 431#include <ddb/ddb.h> 432 433DB_SHOW_COMMAND(cp15, db_show_cp15) 434{ 435 u_int reg; 436 437 __asm __volatile("mrc p15, 0, %0, c0, c0, 0" : "=r" (reg)); 438 db_printf("Cpu ID: 0x%08x\n", reg); 439 __asm __volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (reg)); 440 db_printf("Current Cache Lvl ID: 0x%08x\n",reg); 441 442 __asm __volatile("mrc p15, 0, %0, c1, c0, 0" : "=r" (reg)); 443 db_printf("Ctrl: 0x%08x\n",reg); 444 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (reg)); 445 db_printf("Aux Ctrl: 0x%08x\n",reg); 446 447 __asm __volatile("mrc p15, 0, %0, c0, c1, 0" : "=r" (reg)); 448 db_printf("Processor Feat 0: 0x%08x\n", reg); 449 __asm __volatile("mrc p15, 0, %0, c0, c1, 1" : "=r" (reg)); 450 db_printf("Processor Feat 1: 0x%08x\n", reg); 451 __asm __volatile("mrc p15, 0, %0, c0, c1, 2" : "=r" (reg)); 452 db_printf("Debug Feat 0: 0x%08x\n", reg); 453 __asm __volatile("mrc p15, 0, %0, c0, c1, 3" : "=r" (reg)); 454 db_printf("Auxiliary Feat 0: 0x%08x\n", reg); 455 __asm __volatile("mrc p15, 0, %0, c0, c1, 4" : "=r" (reg)); 456 db_printf("Memory Model Feat 0: 0x%08x\n", reg); 457 __asm __volatile("mrc p15, 0, %0, c0, c1, 5" : "=r" (reg)); 458 db_printf("Memory Model Feat 1: 0x%08x\n", reg); 459 __asm __volatile("mrc p15, 0, %0, c0, c1, 6" : "=r" (reg)); 460 db_printf("Memory Model Feat 2: 0x%08x\n", reg); 461 __asm __volatile("mrc p15, 0, %0, c0, c1, 7" : "=r" (reg)); 462 db_printf("Memory Model Feat 3: 0x%08x\n", reg); 463 464 __asm __volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (reg)); 465 db_printf("Aux Func Modes Ctrl 0: 0x%08x\n",reg); 466 __asm __volatile("mrc p15, 1, %0, c15, c2, 1" : "=r" (reg)); 467 db_printf("Aux Func Modes Ctrl 1: 0x%08x\n",reg); 468 469 __asm __volatile("mrc p15, 1, %0, c15, c12, 0" : "=r" (reg)); 470 db_printf("CPU ID code extension: 0x%08x\n",reg); 471} 472 473DB_SHOW_COMMAND(vtop, db_show_vtop) 474{ 475 u_int reg; 476 477 if (have_addr) { 478 __asm __volatile("mcr p15, 0, %0, c7, c8, 0" : : "r" (addr)); 479 __asm __volatile("mrc p15, 0, %0, c7, c4, 0" : "=r" (reg)); 480 db_printf("Physical address reg: 0x%08x\n",reg); 481 } else 482 db_printf("show vtop <virt_addr>\n"); 483} 484#endif /* DDB */ 485#endif /* CPU_MV_PJ4B */ 486 487