mv_machdep.c revision 257200
1/*- 2 * Copyright (c) 1994-1998 Mark Brinicombe. 3 * Copyright (c) 1994 Brini. 4 * All rights reserved. 5 * 6 * This code is derived from software written for Brini by Mark Brinicombe 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45 36 */ 37 38#include "opt_ddb.h" 39#include "opt_platform.h" 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: head/sys/arm/mv/mv_machdep.c 257200 2013-10-27 01:34:10Z ian $"); 43 44#define _ARM32_BUS_DMA_PRIVATE 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/bus.h> 48 49#include <vm/vm.h> 50#include <vm/pmap.h> 51 52#include <machine/bus.h> 53#include <machine/machdep.h> 54 55#include <arm/mv/mvreg.h> /* XXX */ 56#include <arm/mv/mvvar.h> /* XXX eventually this should be eliminated */ 57#include <arm/mv/mvwin.h> 58 59#include <dev/fdt/fdt_common.h> 60 61static int platform_mpp_init(void); 62#if defined(SOC_MV_ARMADAXP) 63void armadaxp_init_coher_fabric(void); 64void armadaxp_l2_init(void); 65#endif 66 67#define MPP_PIN_MAX 68 68#define MPP_PIN_CELLS 2 69#define MPP_PINS_PER_REG 8 70#define MPP_SEL(pin,func) (((func) & 0xf) << \ 71 (((pin) % MPP_PINS_PER_REG) * 4)) 72 73static int 74platform_mpp_init(void) 75{ 76 pcell_t pinmap[MPP_PIN_MAX * MPP_PIN_CELLS]; 77 int mpp[MPP_PIN_MAX]; 78 uint32_t ctrl_val, ctrl_offset; 79 pcell_t reg[4]; 80 u_long start, size; 81 phandle_t node; 82 pcell_t pin_cells, *pinmap_ptr, pin_count; 83 ssize_t len; 84 int par_addr_cells, par_size_cells; 85 int tuple_size, tuples, rv, pins, i, j; 86 int mpp_pin, mpp_function; 87 88 /* 89 * Try to access the MPP node directly i.e. through /aliases/mpp. 90 */ 91 if ((node = OF_finddevice("mpp")) != -1) 92 if (fdt_is_compatible(node, "mrvl,mpp")) 93 goto moveon; 94 /* 95 * Find the node the long way. 96 */ 97 if ((node = OF_finddevice("/")) == -1) 98 return (ENXIO); 99 100 if ((node = fdt_find_compatible(node, "simple-bus", 0)) == 0) 101 return (ENXIO); 102 103 if ((node = fdt_find_compatible(node, "mrvl,mpp", 0)) == 0) 104 /* 105 * No MPP node. Fall back to how MPP got set by the 106 * first-stage loader and try to continue booting. 107 */ 108 return (0); 109moveon: 110 /* 111 * Process 'reg' prop. 112 */ 113 if ((rv = fdt_addrsize_cells(OF_parent(node), &par_addr_cells, 114 &par_size_cells)) != 0) 115 return(ENXIO); 116 117 tuple_size = sizeof(pcell_t) * (par_addr_cells + par_size_cells); 118 len = OF_getprop(node, "reg", reg, sizeof(reg)); 119 tuples = len / tuple_size; 120 if (tuple_size <= 0) 121 return (EINVAL); 122 123 /* 124 * Get address/size. XXX we assume only the first 'reg' tuple is used. 125 */ 126 rv = fdt_data_to_res(reg, par_addr_cells, par_size_cells, 127 &start, &size); 128 if (rv != 0) 129 return (rv); 130 start += fdt_immr_va; 131 132 /* 133 * Process 'pin-count' and 'pin-map' props. 134 */ 135 if (OF_getprop(node, "pin-count", &pin_count, sizeof(pin_count)) <= 0) 136 return (ENXIO); 137 pin_count = fdt32_to_cpu(pin_count); 138 if (pin_count > MPP_PIN_MAX) 139 return (ERANGE); 140 141 if (OF_getprop(node, "#pin-cells", &pin_cells, sizeof(pin_cells)) <= 0) 142 pin_cells = MPP_PIN_CELLS; 143 pin_cells = fdt32_to_cpu(pin_cells); 144 if (pin_cells > MPP_PIN_CELLS) 145 return (ERANGE); 146 tuple_size = sizeof(pcell_t) * pin_cells; 147 148 bzero(pinmap, sizeof(pinmap)); 149 len = OF_getprop(node, "pin-map", pinmap, sizeof(pinmap)); 150 if (len <= 0) 151 return (ERANGE); 152 if (len % tuple_size) 153 return (ERANGE); 154 pins = len / tuple_size; 155 if (pins > pin_count) 156 return (ERANGE); 157 /* 158 * Fill out a "mpp[pin] => function" table. All pins unspecified in 159 * the 'pin-map' property are defaulted to 0 function i.e. GPIO. 160 */ 161 bzero(mpp, sizeof(mpp)); 162 pinmap_ptr = pinmap; 163 for (i = 0; i < pins; i++) { 164 mpp_pin = fdt32_to_cpu(*pinmap_ptr); 165 mpp_function = fdt32_to_cpu(*(pinmap_ptr + 1)); 166 mpp[mpp_pin] = mpp_function; 167 pinmap_ptr += pin_cells; 168 } 169 170 /* 171 * Prepare and program MPP control register values. 172 */ 173 ctrl_offset = 0; 174 for (i = 0; i < pin_count;) { 175 ctrl_val = 0; 176 177 for (j = 0; j < MPP_PINS_PER_REG; j++) { 178 if (i + j == pin_count - 1) 179 break; 180 ctrl_val |= MPP_SEL(i + j, mpp[i + j]); 181 } 182 i += MPP_PINS_PER_REG; 183 bus_space_write_4(fdtbus_bs_tag, start, ctrl_offset, 184 ctrl_val); 185 186#if defined(SOC_MV_ORION) 187 /* 188 * Third MPP reg on Orion SoC is placed 189 * non-linearly (with different offset). 190 */ 191 if (i == (2 * MPP_PINS_PER_REG)) 192 ctrl_offset = 0x50; 193 else 194#endif 195 ctrl_offset += 4; 196 } 197 198 return (0); 199} 200 201vm_offset_t 202initarm_lastaddr(void) 203{ 204 205 if (fdt_immr_addr(MV_BASE) != 0) 206 while (1); 207 208 /* Platform-specific initialisation */ 209 return (fdt_immr_va - ARM_NOCACHE_KVA_SIZE); 210} 211 212void 213initarm_gpio_init(void) 214{ 215 216 /* 217 * Re-initialise MPP. It is important to call this prior to using 218 * console as the physical connection can be routed via MPP. 219 */ 220 if (platform_mpp_init() != 0) 221 while (1); 222} 223 224void 225initarm_late_init(void) 226{ 227 /* 228 * Re-initialise decode windows 229 */ 230#if !defined(SOC_MV_FREY) 231 if (soc_decode_win() != 0) 232 printf("WARNING: could not re-initialise decode windows! " 233 "Running with existing settings...\n"); 234#else 235 /* Disable watchdog and timers */ 236 write_cpu_ctrl(CPU_TIMERS_BASE + CPU_TIMER_CONTROL, 0); 237#endif 238#if defined(SOC_MV_ARMADAXP) 239#if !defined(SMP) 240 /* For SMP case it should be initialized after APs are booted */ 241 armadaxp_init_coher_fabric(); 242#endif 243 armadaxp_l2_init(); 244#endif 245} 246 247#define FDT_DEVMAP_MAX (MV_WIN_CPU_MAX + 2) 248static struct pmap_devmap fdt_devmap[FDT_DEVMAP_MAX] = { 249 { 0, 0, 0, 0, 0, } 250}; 251 252static int 253platform_sram_devmap(struct pmap_devmap *map) 254{ 255#if !defined(SOC_MV_ARMADAXP) 256 phandle_t child, root; 257 u_long base, size; 258 /* 259 * SRAM range. 260 */ 261 if ((child = OF_finddevice("/sram")) != 0) 262 if (fdt_is_compatible(child, "mrvl,cesa-sram") || 263 fdt_is_compatible(child, "mrvl,scratchpad")) 264 goto moveon; 265 266 if ((root = OF_finddevice("/")) == 0) 267 return (ENXIO); 268 269 if ((child = fdt_find_compatible(root, "mrvl,cesa-sram", 0)) == 0 && 270 (child = fdt_find_compatible(root, "mrvl,scratchpad", 0)) == 0) 271 goto out; 272 273moveon: 274 if (fdt_regsize(child, &base, &size) != 0) 275 return (EINVAL); 276 277 map->pd_va = MV_CESA_SRAM_BASE; /* XXX */ 278 map->pd_pa = base; 279 map->pd_size = size; 280 map->pd_prot = VM_PROT_READ | VM_PROT_WRITE; 281 map->pd_cache = PTE_NOCACHE; 282 283 return (0); 284out: 285#endif 286 return (ENOENT); 287 288} 289 290/* 291 * Supply a default do-nothing implementation of fdt_pci_devmap() via a weak 292 * alias. Many Marvell platforms don't support a PCI interface, but to support 293 * those that do, we end up with a reference to this function below, in 294 * platform_devmap_init(). If "device pci" appears in the kernel config, the 295 * real implementation of this function in dev/fdt/fdt_pci.c overrides the weak 296 * alias defined here. 297 */ 298int mv_default_fdt_pci_devmap(phandle_t node, struct pmap_devmap *devmap, 299 vm_offset_t io_va, vm_offset_t mem_va); 300int 301mv_default_fdt_pci_devmap(phandle_t node, struct pmap_devmap *devmap, 302 vm_offset_t io_va, vm_offset_t mem_va) 303{ 304 305 return (0); 306} 307__weak_reference(mv_default_fdt_pci_devmap, fdt_pci_devmap); 308 309/* 310 * XXX: When device entry in devmap has pd_size smaller than section size, 311 * system will freeze during initialization 312 */ 313 314/* 315 * Construct pmap_devmap[] with DT-derived config data. 316 */ 317int 318platform_devmap_init(void) 319{ 320 phandle_t root, child; 321 pcell_t bank_count; 322 int i, num_mapped; 323 324 i = 0; 325 pmap_devmap_bootstrap_table = &fdt_devmap[0]; 326 327 /* 328 * IMMR range. 329 */ 330 fdt_devmap[i].pd_va = fdt_immr_va; 331 fdt_devmap[i].pd_pa = fdt_immr_pa; 332 fdt_devmap[i].pd_size = fdt_immr_size; 333 fdt_devmap[i].pd_prot = VM_PROT_READ | VM_PROT_WRITE; 334 fdt_devmap[i].pd_cache = PTE_NOCACHE; 335 i++; 336 337 /* 338 * SRAM range. 339 */ 340 if (i < FDT_DEVMAP_MAX) 341 if (platform_sram_devmap(&fdt_devmap[i]) == 0) 342 i++; 343 344 /* 345 * PCI range(s). 346 * PCI range(s) and localbus. 347 */ 348 if ((root = OF_finddevice("/")) == -1) 349 return (ENXIO); 350 for (child = OF_child(root); child != 0; child = OF_peer(child)) { 351 if (fdt_is_type(child, "pci") || fdt_is_type(child, "pciep")) { 352 /* 353 * Check space: each PCI node will consume 2 devmap 354 * entries. 355 */ 356 if (i + 1 >= FDT_DEVMAP_MAX) 357 return (ENOMEM); 358 359 /* 360 * XXX this should account for PCI and multiple ranges 361 * of a given kind. 362 */ 363 if (fdt_pci_devmap(child, &fdt_devmap[i], MV_PCI_VA_IO_BASE, 364 MV_PCI_VA_MEM_BASE) != 0) 365 return (ENXIO); 366 i += 2; 367 } 368 369 if (fdt_is_compatible(child, "mrvl,lbc")) { 370 /* Check available space */ 371 if (OF_getprop(child, "bank-count", (void *)&bank_count, 372 sizeof(bank_count)) <= 0) 373 /* If no property, use default value */ 374 bank_count = 1; 375 else 376 bank_count = fdt32_to_cpu(bank_count); 377 378 if ((i + bank_count) >= FDT_DEVMAP_MAX) 379 return (ENOMEM); 380 381 /* Add all localbus ranges to device map */ 382 num_mapped = 0; 383 384 if (fdt_localbus_devmap(child, &fdt_devmap[i], 385 (int)bank_count, &num_mapped) != 0) 386 return (ENXIO); 387 388 i += num_mapped; 389 } 390 } 391 392 return (0); 393} 394 395struct arm32_dma_range * 396bus_dma_get_range(void) 397{ 398 399 return (NULL); 400} 401 402int 403bus_dma_get_range_nb(void) 404{ 405 406 return (0); 407} 408 409#if defined(CPU_MV_PJ4B) 410#ifdef DDB 411#include <ddb/ddb.h> 412 413DB_SHOW_COMMAND(cp15, db_show_cp15) 414{ 415 u_int reg; 416 417 __asm __volatile("mrc p15, 0, %0, c0, c0, 0" : "=r" (reg)); 418 db_printf("Cpu ID: 0x%08x\n", reg); 419 __asm __volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (reg)); 420 db_printf("Current Cache Lvl ID: 0x%08x\n",reg); 421 422 __asm __volatile("mrc p15, 0, %0, c1, c0, 0" : "=r" (reg)); 423 db_printf("Ctrl: 0x%08x\n",reg); 424 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (reg)); 425 db_printf("Aux Ctrl: 0x%08x\n",reg); 426 427 __asm __volatile("mrc p15, 0, %0, c0, c1, 0" : "=r" (reg)); 428 db_printf("Processor Feat 0: 0x%08x\n", reg); 429 __asm __volatile("mrc p15, 0, %0, c0, c1, 1" : "=r" (reg)); 430 db_printf("Processor Feat 1: 0x%08x\n", reg); 431 __asm __volatile("mrc p15, 0, %0, c0, c1, 2" : "=r" (reg)); 432 db_printf("Debug Feat 0: 0x%08x\n", reg); 433 __asm __volatile("mrc p15, 0, %0, c0, c1, 3" : "=r" (reg)); 434 db_printf("Auxiliary Feat 0: 0x%08x\n", reg); 435 __asm __volatile("mrc p15, 0, %0, c0, c1, 4" : "=r" (reg)); 436 db_printf("Memory Model Feat 0: 0x%08x\n", reg); 437 __asm __volatile("mrc p15, 0, %0, c0, c1, 5" : "=r" (reg)); 438 db_printf("Memory Model Feat 1: 0x%08x\n", reg); 439 __asm __volatile("mrc p15, 0, %0, c0, c1, 6" : "=r" (reg)); 440 db_printf("Memory Model Feat 2: 0x%08x\n", reg); 441 __asm __volatile("mrc p15, 0, %0, c0, c1, 7" : "=r" (reg)); 442 db_printf("Memory Model Feat 3: 0x%08x\n", reg); 443 444 __asm __volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (reg)); 445 db_printf("Aux Func Modes Ctrl 0: 0x%08x\n",reg); 446 __asm __volatile("mrc p15, 1, %0, c15, c2, 1" : "=r" (reg)); 447 db_printf("Aux Func Modes Ctrl 1: 0x%08x\n",reg); 448 449 __asm __volatile("mrc p15, 1, %0, c15, c12, 0" : "=r" (reg)); 450 db_printf("CPU ID code extension: 0x%08x\n",reg); 451} 452 453DB_SHOW_COMMAND(vtop, db_show_vtop) 454{ 455 u_int reg; 456 457 if (have_addr) { 458 __asm __volatile("mcr p15, 0, %0, c7, c8, 0" : : "r" (addr)); 459 __asm __volatile("mrc p15, 0, %0, c7, c4, 0" : "=r" (reg)); 460 db_printf("Physical address reg: 0x%08x\n",reg); 461 } else 462 db_printf("show vtop <virt_addr>\n"); 463} 464#endif /* DDB */ 465#endif /* CPU_MV_PJ4B */ 466 467