mv_machdep.c revision 239277
1/*- 2 * Copyright (c) 1994-1998 Mark Brinicombe. 3 * Copyright (c) 1994 Brini. 4 * All rights reserved. 5 * 6 * This code is derived from software written for Brini by Mark Brinicombe 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45 36 */ 37 38#include "opt_ddb.h" 39#include "opt_platform.h" 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: head/sys/arm/mv/mv_machdep.c 239277 2012-08-15 05:15:49Z gonzo $"); 43 44#define _ARM32_BUS_DMA_PRIVATE 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/sysproto.h> 48#include <sys/signalvar.h> 49#include <sys/imgact.h> 50#include <sys/kernel.h> 51#include <sys/ktr.h> 52#include <sys/linker.h> 53#include <sys/lock.h> 54#include <sys/malloc.h> 55#include <sys/mutex.h> 56#include <sys/pcpu.h> 57#include <sys/proc.h> 58#include <sys/ptrace.h> 59#include <sys/cons.h> 60#include <sys/bio.h> 61#include <sys/bus.h> 62#include <sys/buf.h> 63#include <sys/exec.h> 64#include <sys/kdb.h> 65#include <sys/msgbuf.h> 66#include <machine/reg.h> 67#include <machine/cpu.h> 68#include <machine/fdt.h> 69 70#include <dev/fdt/fdt_common.h> 71#include <dev/ofw/openfirm.h> 72 73#include <vm/vm.h> 74#include <vm/pmap.h> 75#include <vm/vm_object.h> 76#include <vm/vm_page.h> 77#include <vm/vm_pager.h> 78#include <vm/vm_map.h> 79#include <machine/pte.h> 80#include <machine/pmap.h> 81#include <machine/vmparam.h> 82#include <machine/pcb.h> 83#include <machine/undefined.h> 84#include <machine/machdep.h> 85#include <machine/metadata.h> 86#include <machine/armreg.h> 87#include <machine/bus.h> 88#include <sys/reboot.h> 89 90#include <arm/mv/mvreg.h> /* XXX */ 91#include <arm/mv/mvvar.h> /* XXX eventually this should be eliminated */ 92#include <arm/mv/mvwin.h> 93 94#ifdef DEBUG 95#define debugf(fmt, args...) printf(fmt, ##args) 96#else 97#define debugf(fmt, args...) 98#endif 99 100/* 101 * This is the number of L2 page tables required for covering max 102 * (hypothetical) memsize of 4GB and all kernel mappings (vectors, msgbuf, 103 * stacks etc.), uprounded to be divisible by 4. 104 */ 105#define KERNEL_PT_MAX 78 106 107/* Define various stack sizes in pages */ 108#define IRQ_STACK_SIZE 1 109#define ABT_STACK_SIZE 1 110#define UND_STACK_SIZE 1 111 112extern unsigned char kernbase[]; 113extern unsigned char _etext[]; 114extern unsigned char _edata[]; 115extern unsigned char __bss_start[]; 116extern unsigned char _end[]; 117 118extern u_int data_abort_handler_address; 119extern u_int prefetch_abort_handler_address; 120extern u_int undefined_handler_address; 121 122extern vm_offset_t pmap_bootstrap_lastaddr; 123 124struct pv_addr kernel_pt_table[KERNEL_PT_MAX]; 125 126/* Physical and virtual addresses for some global pages */ 127vm_paddr_t phys_avail[10]; 128vm_paddr_t dump_avail[4]; 129vm_offset_t pmap_bootstrap_lastaddr; 130vm_paddr_t pmap_pa; 131 132const struct pmap_devmap *pmap_devmap_bootstrap_table; 133struct pv_addr systempage; 134struct pv_addr msgbufpv; 135struct pv_addr irqstack; 136struct pv_addr undstack; 137struct pv_addr abtstack; 138struct pv_addr kernelstack; 139 140void set_stackptrs(int cpu); 141 142static struct mem_region availmem_regions[FDT_MEM_REGIONS]; 143static int availmem_regions_sz; 144 145static void print_kenv(void); 146static void print_kernel_section_addr(void); 147 148static void physmap_init(void); 149static int platform_devmap_init(void); 150static int platform_mpp_init(void); 151 152static char * 153kenv_next(char *cp) 154{ 155 156 if (cp != NULL) { 157 while (*cp != 0) 158 cp++; 159 cp++; 160 if (*cp == 0) 161 cp = NULL; 162 } 163 return (cp); 164} 165 166static void 167print_kenv(void) 168{ 169 int len; 170 char *cp; 171 172 debugf("loader passed (static) kenv:\n"); 173 if (kern_envp == NULL) { 174 debugf(" no env, null ptr\n"); 175 return; 176 } 177 debugf(" kern_envp = 0x%08x\n", (uint32_t)kern_envp); 178 179 len = 0; 180 for (cp = kern_envp; cp != NULL; cp = kenv_next(cp)) 181 debugf(" %x %s\n", (uint32_t)cp, cp); 182} 183 184static void 185print_kernel_section_addr(void) 186{ 187 188 debugf("kernel image addresses:\n"); 189 debugf(" kernbase = 0x%08x\n", (uint32_t)kernbase); 190 debugf(" _etext (sdata) = 0x%08x\n", (uint32_t)_etext); 191 debugf(" _edata = 0x%08x\n", (uint32_t)_edata); 192 debugf(" __bss_start = 0x%08x\n", (uint32_t)__bss_start); 193 debugf(" _end = 0x%08x\n", (uint32_t)_end); 194} 195 196static void 197physmap_init(void) 198{ 199 int i, j, cnt; 200 vm_offset_t phys_kernelend, kernload; 201 uint32_t s, e, sz; 202 struct mem_region *mp, *mp1; 203 204 phys_kernelend = KERNPHYSADDR + (virtual_avail - KERNVIRTADDR); 205 kernload = KERNPHYSADDR; 206 207 /* 208 * Remove kernel physical address range from avail 209 * regions list. Page align all regions. 210 * Non-page aligned memory isn't very interesting to us. 211 * Also, sort the entries for ascending addresses. 212 */ 213 sz = 0; 214 cnt = availmem_regions_sz; 215 debugf("processing avail regions:\n"); 216 for (mp = availmem_regions; mp->mr_size; mp++) { 217 s = mp->mr_start; 218 e = mp->mr_start + mp->mr_size; 219 debugf(" %08x-%08x -> ", s, e); 220 /* Check whether this region holds all of the kernel. */ 221 if (s < kernload && e > phys_kernelend) { 222 availmem_regions[cnt].mr_start = phys_kernelend; 223 availmem_regions[cnt++].mr_size = e - phys_kernelend; 224 e = kernload; 225 } 226 /* Look whether this regions starts within the kernel. */ 227 if (s >= kernload && s < phys_kernelend) { 228 if (e <= phys_kernelend) 229 goto empty; 230 s = phys_kernelend; 231 } 232 /* Now look whether this region ends within the kernel. */ 233 if (e > kernload && e <= phys_kernelend) { 234 if (s >= kernload) { 235 goto empty; 236 } 237 e = kernload; 238 } 239 /* Now page align the start and size of the region. */ 240 s = round_page(s); 241 e = trunc_page(e); 242 if (e < s) 243 e = s; 244 sz = e - s; 245 debugf("%08x-%08x = %x\n", s, e, sz); 246 247 /* Check whether some memory is left here. */ 248 if (sz == 0) { 249 empty: 250 printf("skipping\n"); 251 bcopy(mp + 1, mp, 252 (cnt - (mp - availmem_regions)) * sizeof(*mp)); 253 cnt--; 254 mp--; 255 continue; 256 } 257 258 /* Do an insertion sort. */ 259 for (mp1 = availmem_regions; mp1 < mp; mp1++) 260 if (s < mp1->mr_start) 261 break; 262 if (mp1 < mp) { 263 bcopy(mp1, mp1 + 1, (char *)mp - (char *)mp1); 264 mp1->mr_start = s; 265 mp1->mr_size = sz; 266 } else { 267 mp->mr_start = s; 268 mp->mr_size = sz; 269 } 270 } 271 availmem_regions_sz = cnt; 272 273 /* Fill in phys_avail table, based on availmem_regions */ 274 debugf("fill in phys_avail:\n"); 275 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 276 277 debugf(" region: 0x%08x - 0x%08x (0x%08x)\n", 278 availmem_regions[i].mr_start, 279 availmem_regions[i].mr_start + availmem_regions[i].mr_size, 280 availmem_regions[i].mr_size); 281 282 /* 283 * We should not map the page at PA 0x0000000, the VM can't 284 * handle it, as pmap_extract() == 0 means failure. 285 */ 286 if (availmem_regions[i].mr_start > 0 || 287 availmem_regions[i].mr_size > PAGE_SIZE) { 288 phys_avail[j] = availmem_regions[i].mr_start; 289 if (phys_avail[j] == 0) 290 phys_avail[j] += PAGE_SIZE; 291 phys_avail[j + 1] = availmem_regions[i].mr_start + 292 availmem_regions[i].mr_size; 293 } else 294 j -= 2; 295 } 296 phys_avail[j] = 0; 297 phys_avail[j + 1] = 0; 298} 299 300void * 301initarm(struct arm_boot_params *abp) 302{ 303 struct pv_addr kernel_l1pt; 304 struct pv_addr dpcpu; 305 vm_offset_t dtbp, freemempos, l2_start, lastaddr; 306 uint32_t memsize, l2size; 307 void *kmdp; 308 u_int l1pagetable; 309 int i = 0, j = 0, err_devmap = 0; 310 311 lastaddr = parse_boot_param(abp); 312 memsize = 0; 313 set_cpufuncs(); 314 315 /* 316 * Find the dtb passed in by the boot loader. 317 */ 318 kmdp = preload_search_by_type("elf kernel"); 319 if (kmdp != NULL) 320 dtbp = MD_FETCH(kmdp, MODINFOMD_DTBP, vm_offset_t); 321 else 322 dtbp = (vm_offset_t)NULL; 323 324 325#if defined(FDT_DTB_STATIC) 326 /* 327 * In case the device tree blob was not retrieved (from metadata) try 328 * to use the statically embedded one. 329 */ 330 if (dtbp == (vm_offset_t)NULL) 331 dtbp = (vm_offset_t)&fdt_static_dtb; 332#endif 333 334 if (OF_install(OFW_FDT, 0) == FALSE) 335 while (1); 336 337 if (OF_init((void *)dtbp) != 0) 338 while (1); 339 340 /* Grab physical memory regions information from device tree. */ 341 if (fdt_get_mem_regions(availmem_regions, &availmem_regions_sz, 342 &memsize) != 0) 343 while(1); 344 345 if (fdt_immr_addr(MV_BASE) != 0) 346 while (1); 347 348 /* Platform-specific initialisation */ 349 pmap_bootstrap_lastaddr = fdt_immr_va - ARM_NOCACHE_KVA_SIZE; 350 351 pcpu0_init(); 352 353 /* Calculate number of L2 tables needed for mapping vm_page_array */ 354 l2size = (memsize / PAGE_SIZE) * sizeof(struct vm_page); 355 l2size = (l2size >> L1_S_SHIFT) + 1; 356 357 /* 358 * Add one table for end of kernel map, one for stacks, msgbuf and 359 * L1 and L2 tables map and one for vectors map. 360 */ 361 l2size += 3; 362 363 /* Make it divisible by 4 */ 364 l2size = (l2size + 3) & ~3; 365 366#define KERNEL_TEXT_BASE (KERNBASE) 367 freemempos = (lastaddr + PAGE_MASK) & ~PAGE_MASK; 368 369 /* Define a macro to simplify memory allocation */ 370#define valloc_pages(var, np) \ 371 alloc_pages((var).pv_va, (np)); \ 372 (var).pv_pa = (var).pv_va + (KERNPHYSADDR - KERNVIRTADDR); 373 374#define alloc_pages(var, np) \ 375 (var) = freemempos; \ 376 freemempos += (np * PAGE_SIZE); \ 377 memset((char *)(var), 0, ((np) * PAGE_SIZE)); 378 379 while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0) 380 freemempos += PAGE_SIZE; 381 valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE); 382 383 for (i = 0; i < l2size; ++i) { 384 if (!(i % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) { 385 valloc_pages(kernel_pt_table[i], 386 L2_TABLE_SIZE / PAGE_SIZE); 387 j = i; 388 } else { 389 kernel_pt_table[i].pv_va = kernel_pt_table[j].pv_va + 390 L2_TABLE_SIZE_REAL * (i - j); 391 kernel_pt_table[i].pv_pa = 392 kernel_pt_table[i].pv_va - KERNVIRTADDR + 393 KERNPHYSADDR; 394 395 } 396 } 397 /* 398 * Allocate a page for the system page mapped to 0x00000000 399 * or 0xffff0000. This page will just contain the system vectors 400 * and can be shared by all processes. 401 */ 402 valloc_pages(systempage, 1); 403 404 /* Allocate dynamic per-cpu area. */ 405 valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE); 406 dpcpu_init((void *)dpcpu.pv_va, 0); 407 408 /* Allocate stacks for all modes */ 409 valloc_pages(irqstack, (IRQ_STACK_SIZE * MAXCPU)); 410 valloc_pages(abtstack, (ABT_STACK_SIZE * MAXCPU)); 411 valloc_pages(undstack, (UND_STACK_SIZE * MAXCPU)); 412 valloc_pages(kernelstack, (KSTACK_PAGES * MAXCPU)); 413 414 init_param1(); 415 416 valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE); 417 418 /* 419 * Now we start construction of the L1 page table 420 * We start by mapping the L2 page tables into the L1. 421 * This means that we can replace L1 mappings later on if necessary 422 */ 423 l1pagetable = kernel_l1pt.pv_va; 424 425 /* 426 * Try to map as much as possible of kernel text and data using 427 * 1MB section mapping and for the rest of initial kernel address 428 * space use L2 coarse tables. 429 * 430 * Link L2 tables for mapping remainder of kernel (modulo 1MB) 431 * and kernel structures 432 */ 433 l2_start = lastaddr & ~(L1_S_OFFSET); 434 for (i = 0 ; i < l2size - 1; i++) 435 pmap_link_l2pt(l1pagetable, l2_start + i * L1_S_SIZE, 436 &kernel_pt_table[i]); 437 438 pmap_curmaxkvaddr = l2_start + (l2size - 1) * L1_S_SIZE; 439 440 /* Map kernel code and data */ 441 pmap_map_chunk(l1pagetable, KERNVIRTADDR, KERNPHYSADDR, 442 (((uint32_t)(lastaddr) - KERNVIRTADDR) + PAGE_MASK) & ~PAGE_MASK, 443 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 444 445 446 /* Map L1 directory and allocated L2 page tables */ 447 pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa, 448 L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); 449 450 pmap_map_chunk(l1pagetable, kernel_pt_table[0].pv_va, 451 kernel_pt_table[0].pv_pa, 452 L2_TABLE_SIZE_REAL * l2size, 453 VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); 454 455 /* Map allocated DPCPU, stacks and msgbuf */ 456 pmap_map_chunk(l1pagetable, dpcpu.pv_va, dpcpu.pv_pa, 457 freemempos - dpcpu.pv_va, 458 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 459 460 /* Link and map the vector page */ 461 pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH, 462 &kernel_pt_table[l2size - 1]); 463 pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa, 464 VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE, PTE_CACHE); 465 466 /* Map pmap_devmap[] entries */ 467 err_devmap = platform_devmap_init(); 468 pmap_devmap_bootstrap(l1pagetable, pmap_devmap_bootstrap_table); 469 470 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 471 DOMAIN_CLIENT); 472 pmap_pa = kernel_l1pt.pv_pa; 473 setttb(kernel_l1pt.pv_pa); 474 cpu_tlb_flushID(); 475 cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)); 476 477 /* 478 * Only after the SOC registers block is mapped we can perform device 479 * tree fixups, as they may attempt to read parameters from hardware. 480 */ 481 OF_interpret("perform-fixup", 0); 482 483 /* 484 * Re-initialise MPP. It is important to call this prior to using 485 * console as the physical connection can be routed via MPP. 486 */ 487 if (platform_mpp_init() != 0) 488 while (1); 489 490 cninit(); 491 492 physmem = memsize / PAGE_SIZE; 493 494 debugf("initarm: console initialized\n"); 495 debugf(" arg1 kmdp = 0x%08x\n", (uint32_t)kmdp); 496 debugf(" boothowto = 0x%08x\n", boothowto); 497 debugf(" dtbp = 0x%08x\n", (uint32_t)dtbp); 498 print_kernel_section_addr(); 499 print_kenv(); 500 501 if (err_devmap != 0) 502 printf("WARNING: could not fully configure devmap, error=%d\n", 503 err_devmap); 504 505 /* 506 * Re-initialise decode windows 507 */ 508#if !defined(SOC_MV_FREY) 509 if (soc_decode_win() != 0) 510 printf("WARNING: could not re-initialise decode windows! " 511 "Running with existing settings...\n"); 512#else 513 /* Disable watchdog and timers */ 514 write_cpu_ctrl(CPU_TIMERS_BASE + CPU_TIMER_CONTROL, 0); 515#endif 516 517 /* 518 * Pages were allocated during the secondary bootstrap for the 519 * stacks for different CPU modes. 520 * We must now set the r13 registers in the different CPU modes to 521 * point to these stacks. 522 * Since the ARM stacks use STMFD etc. we must set r13 to the top end 523 * of the stack memory. 524 */ 525 cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE); 526 527 set_stackptrs(0); 528 529 /* 530 * We must now clean the cache again.... 531 * Cleaning may be done by reading new data to displace any 532 * dirty data in the cache. This will have happened in setttb() 533 * but since we are boot strapping the addresses used for the read 534 * may have just been remapped and thus the cache could be out 535 * of sync. A re-clean after the switch will cure this. 536 * After booting there are no gross relocations of the kernel thus 537 * this problem will not occur after initarm(). 538 */ 539 cpu_idcache_wbinv_all(); 540 541 /* Set stack for exception handlers */ 542 data_abort_handler_address = (u_int)data_abort_handler; 543 prefetch_abort_handler_address = (u_int)prefetch_abort_handler; 544 undefined_handler_address = (u_int)undefinedinstruction_bounce; 545 undefined_init(); 546 547 init_proc0(kernelstack.pv_va); 548 549 arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL); 550 arm_dump_avail_init(memsize, sizeof(dump_avail) / sizeof(dump_avail[0])); 551 pmap_bootstrap(freemempos, pmap_bootstrap_lastaddr, &kernel_l1pt); 552 msgbufp = (void *)msgbufpv.pv_va; 553 msgbufinit(msgbufp, msgbufsize); 554 mutex_init(); 555 556 /* 557 * Prepare map of physical memory regions available to vm subsystem. 558 */ 559 physmap_init(); 560 561 /* Do basic tuning, hz etc */ 562 init_param2(physmem); 563 kdb_init(); 564 return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP - 565 sizeof(struct pcb))); 566} 567 568void 569set_stackptrs(int cpu) 570{ 571 572 set_stackptr(PSR_IRQ32_MODE, 573 irqstack.pv_va + ((IRQ_STACK_SIZE * PAGE_SIZE) * (cpu + 1))); 574 set_stackptr(PSR_ABT32_MODE, 575 abtstack.pv_va + ((ABT_STACK_SIZE * PAGE_SIZE) * (cpu + 1))); 576 set_stackptr(PSR_UND32_MODE, 577 undstack.pv_va + ((UND_STACK_SIZE * PAGE_SIZE) * (cpu + 1))); 578} 579 580#define MPP_PIN_MAX 68 581#define MPP_PIN_CELLS 2 582#define MPP_PINS_PER_REG 8 583#define MPP_SEL(pin,func) (((func) & 0xf) << \ 584 (((pin) % MPP_PINS_PER_REG) * 4)) 585 586static int 587platform_mpp_init(void) 588{ 589 pcell_t pinmap[MPP_PIN_MAX * MPP_PIN_CELLS]; 590 int mpp[MPP_PIN_MAX]; 591 uint32_t ctrl_val, ctrl_offset; 592 pcell_t reg[4]; 593 u_long start, size; 594 phandle_t node; 595 pcell_t pin_cells, *pinmap_ptr, pin_count; 596 ssize_t len; 597 int par_addr_cells, par_size_cells; 598 int tuple_size, tuples, rv, pins, i, j; 599 int mpp_pin, mpp_function; 600 601 /* 602 * Try to access the MPP node directly i.e. through /aliases/mpp. 603 */ 604 if ((node = OF_finddevice("mpp")) != -1) 605 if (fdt_is_compatible(node, "mrvl,mpp")) 606 goto moveon; 607 /* 608 * Find the node the long way. 609 */ 610 if ((node = OF_finddevice("/")) == -1) 611 return (ENXIO); 612 613 if ((node = fdt_find_compatible(node, "simple-bus", 0)) == 0) 614 return (ENXIO); 615 616 if ((node = fdt_find_compatible(node, "mrvl,mpp", 0)) == 0) 617 /* 618 * No MPP node. Fall back to how MPP got set by the 619 * first-stage loader and try to continue booting. 620 */ 621 return (0); 622moveon: 623 /* 624 * Process 'reg' prop. 625 */ 626 if ((rv = fdt_addrsize_cells(OF_parent(node), &par_addr_cells, 627 &par_size_cells)) != 0) 628 return(ENXIO); 629 630 tuple_size = sizeof(pcell_t) * (par_addr_cells + par_size_cells); 631 len = OF_getprop(node, "reg", reg, sizeof(reg)); 632 tuples = len / tuple_size; 633 if (tuple_size <= 0) 634 return (EINVAL); 635 636 /* 637 * Get address/size. XXX we assume only the first 'reg' tuple is used. 638 */ 639 rv = fdt_data_to_res(reg, par_addr_cells, par_size_cells, 640 &start, &size); 641 if (rv != 0) 642 return (rv); 643 start += fdt_immr_va; 644 645 /* 646 * Process 'pin-count' and 'pin-map' props. 647 */ 648 if (OF_getprop(node, "pin-count", &pin_count, sizeof(pin_count)) <= 0) 649 return (ENXIO); 650 pin_count = fdt32_to_cpu(pin_count); 651 if (pin_count > MPP_PIN_MAX) 652 return (ERANGE); 653 654 if (OF_getprop(node, "#pin-cells", &pin_cells, sizeof(pin_cells)) <= 0) 655 pin_cells = MPP_PIN_CELLS; 656 pin_cells = fdt32_to_cpu(pin_cells); 657 if (pin_cells > MPP_PIN_CELLS) 658 return (ERANGE); 659 tuple_size = sizeof(pcell_t) * pin_cells; 660 661 bzero(pinmap, sizeof(pinmap)); 662 len = OF_getprop(node, "pin-map", pinmap, sizeof(pinmap)); 663 if (len <= 0) 664 return (ERANGE); 665 if (len % tuple_size) 666 return (ERANGE); 667 pins = len / tuple_size; 668 if (pins > pin_count) 669 return (ERANGE); 670 /* 671 * Fill out a "mpp[pin] => function" table. All pins unspecified in 672 * the 'pin-map' property are defaulted to 0 function i.e. GPIO. 673 */ 674 bzero(mpp, sizeof(mpp)); 675 pinmap_ptr = pinmap; 676 for (i = 0; i < pins; i++) { 677 mpp_pin = fdt32_to_cpu(*pinmap_ptr); 678 mpp_function = fdt32_to_cpu(*(pinmap_ptr + 1)); 679 mpp[mpp_pin] = mpp_function; 680 pinmap_ptr += pin_cells; 681 } 682 683 /* 684 * Prepare and program MPP control register values. 685 */ 686 ctrl_offset = 0; 687 for (i = 0; i < pin_count;) { 688 ctrl_val = 0; 689 690 for (j = 0; j < MPP_PINS_PER_REG; j++) { 691 if (i + j == pin_count - 1) 692 break; 693 ctrl_val |= MPP_SEL(i + j, mpp[i + j]); 694 } 695 i += MPP_PINS_PER_REG; 696 bus_space_write_4(fdtbus_bs_tag, start, ctrl_offset, 697 ctrl_val); 698 699#if defined(SOC_MV_ORION) 700 /* 701 * Third MPP reg on Orion SoC is placed 702 * non-linearly (with different offset). 703 */ 704 if (i == (2 * MPP_PINS_PER_REG)) 705 ctrl_offset = 0x50; 706 else 707#endif 708 ctrl_offset += 4; 709 } 710 711 return (0); 712} 713 714#define FDT_DEVMAP_MAX (MV_WIN_CPU_MAX + 2) 715static struct pmap_devmap fdt_devmap[FDT_DEVMAP_MAX] = { 716 { 0, 0, 0, 0, 0, } 717}; 718 719static int 720platform_sram_devmap(struct pmap_devmap *map) 721{ 722#if !defined(SOC_MV_ARMADAXP) 723 phandle_t child, root; 724 u_long base, size; 725 /* 726 * SRAM range. 727 */ 728 if ((child = OF_finddevice("/sram")) != 0) 729 if (fdt_is_compatible(child, "mrvl,cesa-sram") || 730 fdt_is_compatible(child, "mrvl,scratchpad")) 731 goto moveon; 732 733 if ((root = OF_finddevice("/")) == 0) 734 return (ENXIO); 735 736 if ((child = fdt_find_compatible(root, "mrvl,cesa-sram", 0)) == 0 && 737 (child = fdt_find_compatible(root, "mrvl,scratchpad", 0)) == 0) 738 goto out; 739 740moveon: 741 if (fdt_regsize(child, &base, &size) != 0) 742 return (EINVAL); 743 744 map->pd_va = MV_CESA_SRAM_BASE; /* XXX */ 745 map->pd_pa = base; 746 map->pd_size = size; 747 map->pd_prot = VM_PROT_READ | VM_PROT_WRITE; 748 map->pd_cache = PTE_NOCACHE; 749 750 return (0); 751out: 752#endif 753 return (ENOENT); 754 755} 756 757/* 758 * XXX: When device entry in devmap has pd_size smaller than section size, 759 * system will freeze during initialization 760 */ 761 762/* 763 * Construct pmap_devmap[] with DT-derived config data. 764 */ 765 766static int 767platform_devmap_init(void) 768{ 769 phandle_t root, child; 770 pcell_t bank_count; 771 u_long base, size; 772 int i, num_mapped; 773 774 i = 0; 775 pmap_devmap_bootstrap_table = &fdt_devmap[0]; 776 777 /* 778 * IMMR range. 779 */ 780 fdt_devmap[i].pd_va = fdt_immr_va; 781 fdt_devmap[i].pd_pa = fdt_immr_pa; 782 fdt_devmap[i].pd_size = fdt_immr_size; 783 fdt_devmap[i].pd_prot = VM_PROT_READ | VM_PROT_WRITE; 784 fdt_devmap[i].pd_cache = PTE_NOCACHE; 785 i++; 786 787 /* 788 * SRAM range. 789 */ 790 if (i < FDT_DEVMAP_MAX) 791 if (platform_sram_devmap(&fdt_devmap[i]) == 0) 792 i++; 793 794 /* 795 * PCI range(s). 796 * PCI range(s) and localbus. 797 */ 798 if ((root = OF_finddevice("/")) == -1) 799 return (ENXIO); 800 for (child = OF_child(root); child != 0; child = OF_peer(child)) { 801 if (fdt_is_type(child, "pci") || fdt_is_type(child, "pciep")) { 802 /* 803 * Check space: each PCI node will consume 2 devmap 804 * entries. 805 */ 806 if (i + 1 >= FDT_DEVMAP_MAX) 807 return (ENOMEM); 808 809 /* 810 * XXX this should account for PCI and multiple ranges 811 * of a given kind. 812 */ 813 if (fdt_pci_devmap(child, &fdt_devmap[i], MV_PCI_VA_IO_BASE, 814 MV_PCI_VA_MEM_BASE) != 0) 815 return (ENXIO); 816 i += 2; 817 } 818 819 if (fdt_is_compatible(child, "mrvl,lbc")) { 820 /* Check available space */ 821 if (OF_getprop(child, "bank-count", (void *)&bank_count, 822 sizeof(bank_count)) <= 0) 823 /* If no property, use default value */ 824 bank_count = 1; 825 else 826 bank_count = fdt32_to_cpu(bank_count); 827 828 if ((i + bank_count) >= FDT_DEVMAP_MAX) 829 return (ENOMEM); 830 831 /* Add all localbus ranges to device map */ 832 num_mapped = 0; 833 834 if (fdt_localbus_devmap(child, &fdt_devmap[i], 835 (int)bank_count, &num_mapped) != 0) 836 return (ENXIO); 837 838 i += num_mapped; 839 } 840 } 841 842 /* 843 * CESA SRAM range. 844 */ 845 if ((child = OF_finddevice("sram")) != -1) 846 if (fdt_is_compatible(child, "mrvl,cesa-sram")) 847 goto moveon; 848 849 if ((child = fdt_find_compatible(root, "mrvl,cesa-sram", 0)) == 0) 850 /* No CESA SRAM node. */ 851 return (0); 852moveon: 853 if (i >= FDT_DEVMAP_MAX) 854 return (ENOMEM); 855 856 if (fdt_regsize(child, &base, &size) != 0) 857 return (EINVAL); 858 859 fdt_devmap[i].pd_va = MV_CESA_SRAM_BASE; /* XXX */ 860 fdt_devmap[i].pd_pa = base; 861 fdt_devmap[i].pd_size = size; 862 fdt_devmap[i].pd_prot = VM_PROT_READ | VM_PROT_WRITE; 863 fdt_devmap[i].pd_cache = PTE_NOCACHE; 864 865 return (0); 866} 867 868struct arm32_dma_range * 869bus_dma_get_range(void) 870{ 871 872 return (NULL); 873} 874 875int 876bus_dma_get_range_nb(void) 877{ 878 879 return (0); 880} 881 882#if defined(CPU_MV_PJ4B) 883#ifdef DDB 884#include <ddb/ddb.h> 885 886DB_SHOW_COMMAND(cp15, db_show_cp15) 887{ 888 u_int reg; 889 890 __asm __volatile("mrc p15, 0, %0, c0, c0, 0" : "=r" (reg)); 891 db_printf("Cpu ID: 0x%08x\n", reg); 892 __asm __volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (reg)); 893 db_printf("Current Cache Lvl ID: 0x%08x\n",reg); 894 895 __asm __volatile("mrc p15, 0, %0, c1, c0, 0" : "=r" (reg)); 896 db_printf("Ctrl: 0x%08x\n",reg); 897 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (reg)); 898 db_printf("Aux Ctrl: 0x%08x\n",reg); 899 900 __asm __volatile("mrc p15, 0, %0, c0, c1, 0" : "=r" (reg)); 901 db_printf("Processor Feat 0: 0x%08x\n", reg); 902 __asm __volatile("mrc p15, 0, %0, c0, c1, 1" : "=r" (reg)); 903 db_printf("Processor Feat 1: 0x%08x\n", reg); 904 __asm __volatile("mrc p15, 0, %0, c0, c1, 2" : "=r" (reg)); 905 db_printf("Debug Feat 0: 0x%08x\n", reg); 906 __asm __volatile("mrc p15, 0, %0, c0, c1, 3" : "=r" (reg)); 907 db_printf("Auxiliary Feat 0: 0x%08x\n", reg); 908 __asm __volatile("mrc p15, 0, %0, c0, c1, 4" : "=r" (reg)); 909 db_printf("Memory Model Feat 0: 0x%08x\n", reg); 910 __asm __volatile("mrc p15, 0, %0, c0, c1, 5" : "=r" (reg)); 911 db_printf("Memory Model Feat 1: 0x%08x\n", reg); 912 __asm __volatile("mrc p15, 0, %0, c0, c1, 6" : "=r" (reg)); 913 db_printf("Memory Model Feat 2: 0x%08x\n", reg); 914 __asm __volatile("mrc p15, 0, %0, c0, c1, 7" : "=r" (reg)); 915 db_printf("Memory Model Feat 3: 0x%08x\n", reg); 916 917 __asm __volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (reg)); 918 db_printf("Aux Func Modes Ctrl 0: 0x%08x\n",reg); 919 __asm __volatile("mrc p15, 1, %0, c15, c2, 1" : "=r" (reg)); 920 db_printf("Aux Func Modes Ctrl 1: 0x%08x\n",reg); 921 922 __asm __volatile("mrc p15, 1, %0, c15, c12, 0" : "=r" (reg)); 923 db_printf("CPU ID code extension: 0x%08x\n",reg); 924} 925 926DB_SHOW_COMMAND(vtop, db_show_vtop) 927{ 928 u_int reg; 929 930 if (have_addr) { 931 __asm __volatile("mcr p15, 0, %0, c7, c8, 0" : : "r" (addr)); 932 __asm __volatile("mrc p15, 0, %0, c7, c4, 0" : "=r" (reg)); 933 db_printf("Physical address reg: 0x%08x\n",reg); 934 } else 935 db_printf("show vtop <virt_addr>\n"); 936} 937#endif /* DDB */ 938#endif /* CPU_MV_PJ4B */ 939 940