mv_machdep.c revision 225991
147857Sbrian/*- 247857Sbrian * Copyright (c) 1994-1998 Mark Brinicombe. 347857Sbrian * Copyright (c) 1994 Brini. 447857Sbrian * All rights reserved. 547857Sbrian * 647857Sbrian * This code is derived from software written for Brini by Mark Brinicombe 747857Sbrian * 847857Sbrian * Redistribution and use in source and binary forms, with or without 947857Sbrian * modification, are permitted provided that the following conditions 1047857Sbrian * are met: 1147857Sbrian * 1. Redistributions of source code must retain the above copyright 1247857Sbrian * notice, this list of conditions and the following disclaimer. 1347857Sbrian * 2. Redistributions in binary form must reproduce the above copyright 1447857Sbrian * notice, this list of conditions and the following disclaimer in the 1547857Sbrian * documentation and/or other materials provided with the distribution. 1647857Sbrian * 3. All advertising materials mentioning features or use of this software 1747857Sbrian * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45 36 */ 37 38#include "opt_ddb.h" 39#include "opt_platform.h" 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: head/sys/arm/mv/mv_machdep.c 225991 2011-10-04 16:58:20Z marcel $"); 43 44#define _ARM32_BUS_DMA_PRIVATE 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/sysproto.h> 48#include <sys/signalvar.h> 49#include <sys/imgact.h> 50#include <sys/kernel.h> 51#include <sys/ktr.h> 52#include <sys/linker.h> 53#include <sys/lock.h> 54#include <sys/malloc.h> 55#include <sys/mutex.h> 56#include <sys/pcpu.h> 57#include <sys/proc.h> 58#include <sys/ptrace.h> 59#include <sys/cons.h> 60#include <sys/bio.h> 61#include <sys/bus.h> 62#include <sys/buf.h> 63#include <sys/exec.h> 64#include <sys/kdb.h> 65#include <sys/msgbuf.h> 66#include <machine/reg.h> 67#include <machine/cpu.h> 68#include <machine/fdt.h> 69 70#include <dev/fdt/fdt_common.h> 71#include <dev/ofw/openfirm.h> 72 73#include <vm/vm.h> 74#include <vm/pmap.h> 75#include <vm/vm_object.h> 76#include <vm/vm_page.h> 77#include <vm/vm_pager.h> 78#include <vm/vm_map.h> 79#include <machine/pte.h> 80#include <machine/pmap.h> 81#include <machine/vmparam.h> 82#include <machine/pcb.h> 83#include <machine/undefined.h> 84#include <machine/machdep.h> 85#include <machine/metadata.h> 86#include <machine/armreg.h> 87#include <machine/bus.h> 88#include <sys/reboot.h> 89 90#include <arm/mv/mvreg.h> /* XXX */ 91#include <arm/mv/mvvar.h> /* XXX eventually this should be eliminated */ 92#include <arm/mv/mvwin.h> 93 94#ifdef DEBUG 95#define debugf(fmt, args...) printf(fmt, ##args) 96#else 97#define debugf(fmt, args...) 98#endif 99 100/* 101 * This is the number of L2 page tables required for covering max 102 * (hypothetical) memsize of 4GB and all kernel mappings (vectors, msgbuf, 103 * stacks etc.), uprounded to be divisible by 4. 104 */ 105#define KERNEL_PT_MAX 78 106 107/* Define various stack sizes in pages */ 108#define IRQ_STACK_SIZE 1 109#define ABT_STACK_SIZE 1 110#define UND_STACK_SIZE 1 111 112extern unsigned char kernbase[]; 113extern unsigned char _etext[]; 114extern unsigned char _edata[]; 115extern unsigned char __bss_start[]; 116extern unsigned char _end[]; 117 118#ifdef DDB 119extern vm_offset_t ksym_start, ksym_end; 120#endif 121 122extern u_int data_abort_handler_address; 123extern u_int prefetch_abort_handler_address; 124extern u_int undefined_handler_address; 125 126extern vm_offset_t pmap_bootstrap_lastaddr; 127extern int *end; 128 129struct pv_addr kernel_pt_table[KERNEL_PT_MAX]; 130struct pcpu __pcpu; 131struct pcpu *pcpup = &__pcpu; 132 133/* Physical and virtual addresses for some global pages */ 134 135vm_paddr_t phys_avail[10]; 136vm_paddr_t dump_avail[4]; 137vm_offset_t physical_pages; 138vm_offset_t pmap_bootstrap_lastaddr; 139 140const struct pmap_devmap *pmap_devmap_bootstrap_table; 141struct pv_addr systempage; 142struct pv_addr msgbufpv; 143struct pv_addr irqstack; 144struct pv_addr undstack; 145struct pv_addr abtstack; 146struct pv_addr kernelstack; 147 148static struct trapframe proc0_tf; 149 150static struct mem_region availmem_regions[FDT_MEM_REGIONS]; 151static int availmem_regions_sz; 152 153static void print_kenv(void); 154static void print_kernel_section_addr(void); 155 156static void physmap_init(void); 157static int platform_devmap_init(void); 158static int platform_mpp_init(void); 159 160static char * 161kenv_next(char *cp) 162{ 163 164 if (cp != NULL) { 165 while (*cp != 0) 166 cp++; 167 cp++; 168 if (*cp == 0) 169 cp = NULL; 170 } 171 return (cp); 172} 173 174static void 175print_kenv(void) 176{ 177 int len; 178 char *cp; 179 180 debugf("loader passed (static) kenv:\n"); 181 if (kern_envp == NULL) { 182 debugf(" no env, null ptr\n"); 183 return; 184 } 185 debugf(" kern_envp = 0x%08x\n", (uint32_t)kern_envp); 186 187 len = 0; 188 for (cp = kern_envp; cp != NULL; cp = kenv_next(cp)) 189 debugf(" %x %s\n", (uint32_t)cp, cp); 190} 191 192static void 193print_kernel_section_addr(void) 194{ 195 196 debugf("kernel image addresses:\n"); 197 debugf(" kernbase = 0x%08x\n", (uint32_t)kernbase); 198 debugf(" _etext (sdata) = 0x%08x\n", (uint32_t)_etext); 199 debugf(" _edata = 0x%08x\n", (uint32_t)_edata); 200 debugf(" __bss_start = 0x%08x\n", (uint32_t)__bss_start); 201 debugf(" _end = 0x%08x\n", (uint32_t)_end); 202} 203 204static void 205physmap_init(void) 206{ 207 int i, j, cnt; 208 vm_offset_t phys_kernelend, kernload; 209 uint32_t s, e, sz; 210 struct mem_region *mp, *mp1; 211 212 phys_kernelend = KERNPHYSADDR + (virtual_avail - KERNVIRTADDR); 213 kernload = KERNPHYSADDR; 214 215 /* 216 * Remove kernel physical address range from avail 217 * regions list. Page align all regions. 218 * Non-page aligned memory isn't very interesting to us. 219 * Also, sort the entries for ascending addresses. 220 */ 221 sz = 0; 222 cnt = availmem_regions_sz; 223 debugf("processing avail regions:\n"); 224 for (mp = availmem_regions; mp->mr_size; mp++) { 225 s = mp->mr_start; 226 e = mp->mr_start + mp->mr_size; 227 debugf(" %08x-%08x -> ", s, e); 228 /* Check whether this region holds all of the kernel. */ 229 if (s < kernload && e > phys_kernelend) { 230 availmem_regions[cnt].mr_start = phys_kernelend; 231 availmem_regions[cnt++].mr_size = e - phys_kernelend; 232 e = kernload; 233 } 234 /* Look whether this regions starts within the kernel. */ 235 if (s >= kernload && s < phys_kernelend) { 236 if (e <= phys_kernelend) 237 goto empty; 238 s = phys_kernelend; 239 } 240 /* Now look whether this region ends within the kernel. */ 241 if (e > kernload && e <= phys_kernelend) { 242 if (s >= kernload) { 243 goto empty; 244 } 245 e = kernload; 246 } 247 /* Now page align the start and size of the region. */ 248 s = round_page(s); 249 e = trunc_page(e); 250 if (e < s) 251 e = s; 252 sz = e - s; 253 debugf("%08x-%08x = %x\n", s, e, sz); 254 255 /* Check whether some memory is left here. */ 256 if (sz == 0) { 257 empty: 258 printf("skipping\n"); 259 bcopy(mp + 1, mp, 260 (cnt - (mp - availmem_regions)) * sizeof(*mp)); 261 cnt--; 262 mp--; 263 continue; 264 } 265 266 /* Do an insertion sort. */ 267 for (mp1 = availmem_regions; mp1 < mp; mp1++) 268 if (s < mp1->mr_start) 269 break; 270 if (mp1 < mp) { 271 bcopy(mp1, mp1 + 1, (char *)mp - (char *)mp1); 272 mp1->mr_start = s; 273 mp1->mr_size = sz; 274 } else { 275 mp->mr_start = s; 276 mp->mr_size = sz; 277 } 278 } 279 availmem_regions_sz = cnt; 280 281 /* Fill in phys_avail table, based on availmem_regions */ 282 debugf("fill in phys_avail:\n"); 283 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 284 285 debugf(" region: 0x%08x - 0x%08x (0x%08x)\n", 286 availmem_regions[i].mr_start, 287 availmem_regions[i].mr_start + availmem_regions[i].mr_size, 288 availmem_regions[i].mr_size); 289 290 phys_avail[j] = availmem_regions[i].mr_start; 291 phys_avail[j + 1] = availmem_regions[i].mr_start + 292 availmem_regions[i].mr_size; 293 } 294 phys_avail[j] = 0; 295 phys_avail[j + 1] = 0; 296} 297 298void * 299initarm(void *mdp, void *unused __unused) 300{ 301 struct pv_addr kernel_l1pt; 302 struct pv_addr dpcpu; 303 vm_offset_t dtbp, freemempos, l2_start, lastaddr; 304 uint32_t memsize, l2size; 305 void *kmdp; 306 u_int l1pagetable; 307 int i = 0, j = 0; 308 309 kmdp = NULL; 310 lastaddr = 0; 311 memsize = 0; 312 dtbp = (vm_offset_t)NULL; 313 314 set_cpufuncs(); 315 316 /* 317 * Mask metadata pointer: it is supposed to be on page boundary. If 318 * the first argument (mdp) doesn't point to a valid address the 319 * bootloader must have passed us something else than the metadata 320 * ptr... In this case we want to fall back to some built-in settings. 321 */ 322 mdp = (void *)((uint32_t)mdp & ~PAGE_MASK); 323 324 /* Parse metadata and fetch parameters */ 325 if (mdp != NULL) { 326 preload_metadata = mdp; 327 kmdp = preload_search_by_type("elf kernel"); 328 if (kmdp != NULL) { 329 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 330 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *); 331 dtbp = MD_FETCH(kmdp, MODINFOMD_DTBP, vm_offset_t); 332 lastaddr = MD_FETCH(kmdp, MODINFOMD_KERNEND, 333 vm_offset_t); 334#ifdef DDB 335 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 336 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 337#endif 338 } 339 340 preload_addr_relocate = KERNVIRTADDR - KERNPHYSADDR; 341 } else { 342 /* Fall back to hardcoded metadata. */ 343 lastaddr = fake_preload_metadata(); 344 } 345 346#if defined(FDT_DTB_STATIC) 347 /* 348 * In case the device tree blob was not retrieved (from metadata) try 349 * to use the statically embedded one. 350 */ 351 if (dtbp == (vm_offset_t)NULL) 352 dtbp = (vm_offset_t)&fdt_static_dtb; 353#endif 354 355 if (OF_install(OFW_FDT, 0) == FALSE) 356 while (1); 357 358 if (OF_init((void *)dtbp) != 0) 359 while (1); 360 361 /* Grab physical memory regions information from device tree. */ 362 if (fdt_get_mem_regions(availmem_regions, &availmem_regions_sz, 363 &memsize) != 0) 364 while(1); 365 366 if (fdt_immr_addr(MV_BASE) != 0) 367 while (1); 368 369 /* Platform-specific initialisation */ 370 pmap_bootstrap_lastaddr = fdt_immr_va - ARM_NOCACHE_KVA_SIZE; 371 372 pcpu_init(pcpup, 0, sizeof(struct pcpu)); 373 PCPU_SET(curthread, &thread0); 374 375 /* Calculate number of L2 tables needed for mapping vm_page_array */ 376 l2size = (memsize / PAGE_SIZE) * sizeof(struct vm_page); 377 l2size = (l2size >> L1_S_SHIFT) + 1; 378 379 /* 380 * Add one table for end of kernel map, one for stacks, msgbuf and 381 * L1 and L2 tables map and one for vectors map. 382 */ 383 l2size += 3; 384 385 /* Make it divisible by 4 */ 386 l2size = (l2size + 3) & ~3; 387 388#define KERNEL_TEXT_BASE (KERNBASE) 389 freemempos = (lastaddr + PAGE_MASK) & ~PAGE_MASK; 390 391 /* Define a macro to simplify memory allocation */ 392#define valloc_pages(var, np) \ 393 alloc_pages((var).pv_va, (np)); \ 394 (var).pv_pa = (var).pv_va + (KERNPHYSADDR - KERNVIRTADDR); 395 396#define alloc_pages(var, np) \ 397 (var) = freemempos; \ 398 freemempos += (np * PAGE_SIZE); \ 399 memset((char *)(var), 0, ((np) * PAGE_SIZE)); 400 401 while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0) 402 freemempos += PAGE_SIZE; 403 valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE); 404 405 for (i = 0; i < l2size; ++i) { 406 if (!(i % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) { 407 valloc_pages(kernel_pt_table[i], 408 L2_TABLE_SIZE / PAGE_SIZE); 409 j = i; 410 } else { 411 kernel_pt_table[i].pv_va = kernel_pt_table[j].pv_va + 412 L2_TABLE_SIZE_REAL * (i - j); 413 kernel_pt_table[i].pv_pa = 414 kernel_pt_table[i].pv_va - KERNVIRTADDR + 415 KERNPHYSADDR; 416 417 } 418 } 419 /* 420 * Allocate a page for the system page mapped to 0x00000000 421 * or 0xffff0000. This page will just contain the system vectors 422 * and can be shared by all processes. 423 */ 424 valloc_pages(systempage, 1); 425 426 /* Allocate dynamic per-cpu area. */ 427 valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE); 428 dpcpu_init((void *)dpcpu.pv_va, 0); 429 430 /* Allocate stacks for all modes */ 431 valloc_pages(irqstack, IRQ_STACK_SIZE); 432 valloc_pages(abtstack, ABT_STACK_SIZE); 433 valloc_pages(undstack, UND_STACK_SIZE); 434 valloc_pages(kernelstack, KSTACK_PAGES); 435 436 init_param1(); 437 438 valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE); 439 440 /* 441 * Now we start construction of the L1 page table 442 * We start by mapping the L2 page tables into the L1. 443 * This means that we can replace L1 mappings later on if necessary 444 */ 445 l1pagetable = kernel_l1pt.pv_va; 446 447 /* 448 * Try to map as much as possible of kernel text and data using 449 * 1MB section mapping and for the rest of initial kernel address 450 * space use L2 coarse tables. 451 * 452 * Link L2 tables for mapping remainder of kernel (modulo 1MB) 453 * and kernel structures 454 */ 455 l2_start = lastaddr & ~(L1_S_OFFSET); 456 for (i = 0 ; i < l2size - 1; i++) 457 pmap_link_l2pt(l1pagetable, l2_start + i * L1_S_SIZE, 458 &kernel_pt_table[i]); 459 460 pmap_curmaxkvaddr = l2_start + (l2size - 1) * L1_S_SIZE; 461 462 /* Map kernel code and data */ 463 pmap_map_chunk(l1pagetable, KERNVIRTADDR, KERNPHYSADDR, 464 (((uint32_t)(lastaddr) - KERNVIRTADDR) + PAGE_MASK) & ~PAGE_MASK, 465 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 466 467 468 /* Map L1 directory and allocated L2 page tables */ 469 pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa, 470 L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); 471 472 pmap_map_chunk(l1pagetable, kernel_pt_table[0].pv_va, 473 kernel_pt_table[0].pv_pa, 474 L2_TABLE_SIZE_REAL * l2size, 475 VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); 476 477 /* Map allocated DPCPU, stacks and msgbuf */ 478 pmap_map_chunk(l1pagetable, dpcpu.pv_va, dpcpu.pv_pa, 479 freemempos - dpcpu.pv_va, 480 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 481 482 /* Link and map the vector page */ 483 pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH, 484 &kernel_pt_table[l2size - 1]); 485 pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa, 486 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 487 488 /* Map pmap_devmap[] entries */ 489 if (platform_devmap_init() != 0) 490 while (1); 491 pmap_devmap_bootstrap(l1pagetable, pmap_devmap_bootstrap_table); 492 493 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 494 DOMAIN_CLIENT); 495 setttb(kernel_l1pt.pv_pa); 496 cpu_tlb_flushID(); 497 cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)); 498 499 /* 500 * Only after the SOC registers block is mapped we can perform device 501 * tree fixups, as they may attempt to read parameters from hardware. 502 */ 503 OF_interpret("perform-fixup", 0); 504 505 /* 506 * Re-initialise MPP. It is important to call this prior to using 507 * console as the physical connection can be routed via MPP. 508 */ 509 if (platform_mpp_init() != 0) 510 while (1); 511 512 cninit(); 513 514 physmem = memsize / PAGE_SIZE; 515 516 debugf("initarm: console initialized\n"); 517 debugf(" arg1 mdp = 0x%08x\n", (uint32_t)mdp); 518 debugf(" boothowto = 0x%08x\n", boothowto); 519 printf(" dtbp = 0x%08x\n", (uint32_t)dtbp); 520 print_kernel_section_addr(); 521 print_kenv(); 522 523 /* 524 * Re-initialise decode windows 525 */ 526 if (soc_decode_win() != 0) 527 printf("WARNING: could not re-initialise decode windows! " 528 "Running with existing settings...\n"); 529 /* 530 * Pages were allocated during the secondary bootstrap for the 531 * stacks for different CPU modes. 532 * We must now set the r13 registers in the different CPU modes to 533 * point to these stacks. 534 * Since the ARM stacks use STMFD etc. we must set r13 to the top end 535 * of the stack memory. 536 */ 537 cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE); 538 set_stackptr(PSR_IRQ32_MODE, 539 irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE); 540 set_stackptr(PSR_ABT32_MODE, 541 abtstack.pv_va + ABT_STACK_SIZE * PAGE_SIZE); 542 set_stackptr(PSR_UND32_MODE, 543 undstack.pv_va + UND_STACK_SIZE * PAGE_SIZE); 544 545 /* 546 * We must now clean the cache again.... 547 * Cleaning may be done by reading new data to displace any 548 * dirty data in the cache. This will have happened in setttb() 549 * but since we are boot strapping the addresses used for the read 550 * may have just been remapped and thus the cache could be out 551 * of sync. A re-clean after the switch will cure this. 552 * After booting there are no gross relocations of the kernel thus 553 * this problem will not occur after initarm(). 554 */ 555 cpu_idcache_wbinv_all(); 556 557 /* Set stack for exception handlers */ 558 data_abort_handler_address = (u_int)data_abort_handler; 559 prefetch_abort_handler_address = (u_int)prefetch_abort_handler; 560 undefined_handler_address = (u_int)undefinedinstruction_bounce; 561 undefined_init(); 562 563 proc_linkup0(&proc0, &thread0); 564 thread0.td_kstack = kernelstack.pv_va; 565 thread0.td_kstack_pages = KSTACK_PAGES; 566 thread0.td_pcb = (struct pcb *) 567 (thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1; 568 thread0.td_pcb->pcb_flags = 0; 569 thread0.td_frame = &proc0_tf; 570 pcpup->pc_curpcb = thread0.td_pcb; 571 572 arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL); 573 574 dump_avail[0] = 0; 575 dump_avail[1] = memsize; 576 dump_avail[2] = 0; 577 dump_avail[3] = 0; 578 579 pmap_bootstrap(freemempos, pmap_bootstrap_lastaddr, &kernel_l1pt); 580 msgbufp = (void *)msgbufpv.pv_va; 581 msgbufinit(msgbufp, msgbufsize); 582 mutex_init(); 583 584 /* 585 * Prepare map of physical memory regions available to vm subsystem. 586 */ 587 physmap_init(); 588 589 /* Do basic tuning, hz etc */ 590 init_param2(physmem); 591 kdb_init(); 592 return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP - 593 sizeof(struct pcb))); 594} 595 596#define MPP_PIN_MAX 50 597#define MPP_PIN_CELLS 2 598#define MPP_PINS_PER_REG 8 599#define MPP_SEL(pin,func) (((func) & 0xf) << \ 600 (((pin) % MPP_PINS_PER_REG) * 4)) 601 602static int 603platform_mpp_init(void) 604{ 605 pcell_t pinmap[MPP_PIN_MAX * MPP_PIN_CELLS]; 606 int mpp[MPP_PIN_MAX]; 607 uint32_t ctrl_val, ctrl_offset; 608 pcell_t reg[4]; 609 u_long start, size; 610 phandle_t node; 611 pcell_t pin_cells, *pinmap_ptr, pin_count; 612 ssize_t len; 613 int par_addr_cells, par_size_cells; 614 int tuple_size, tuples, rv, pins, i, j; 615 int mpp_pin, mpp_function; 616 617 /* 618 * Try to access the MPP node directly i.e. through /aliases/mpp. 619 */ 620 if ((node = OF_finddevice("mpp")) != 0) 621 if (fdt_is_compatible(node, "mrvl,mpp")) 622 goto moveon; 623 /* 624 * Find the node the long way. 625 */ 626 if ((node = OF_finddevice("/")) == 0) 627 return (ENXIO); 628 629 if ((node = fdt_find_compatible(node, "simple-bus", 0)) == 0) 630 return (ENXIO); 631 632 if ((node = fdt_find_compatible(node, "mrvl,mpp", 0)) == 0) 633 return (ENXIO); 634moveon: 635 /* 636 * Process 'reg' prop. 637 */ 638 if ((rv = fdt_addrsize_cells(OF_parent(node), &par_addr_cells, 639 &par_size_cells)) != 0) 640 return(ENXIO); 641 642 tuple_size = sizeof(pcell_t) * (par_addr_cells + par_size_cells); 643 len = OF_getprop(node, "reg", reg, sizeof(reg)); 644 tuples = len / tuple_size; 645 if (tuple_size <= 0) 646 return (EINVAL); 647 648 /* 649 * Get address/size. XXX we assume only the first 'reg' tuple is used. 650 */ 651 rv = fdt_data_to_res(reg, par_addr_cells, par_size_cells, 652 &start, &size); 653 if (rv != 0) 654 return (rv); 655 start += fdt_immr_va; 656 657 /* 658 * Process 'pin-count' and 'pin-map' props. 659 */ 660 if (OF_getprop(node, "pin-count", &pin_count, sizeof(pin_count)) <= 0) 661 return (ENXIO); 662 pin_count = fdt32_to_cpu(pin_count); 663 if (pin_count > MPP_PIN_MAX) 664 return (ERANGE); 665 666 if (OF_getprop(node, "#pin-cells", &pin_cells, sizeof(pin_cells)) <= 0) 667 pin_cells = MPP_PIN_CELLS; 668 pin_cells = fdt32_to_cpu(pin_cells); 669 if (pin_cells > MPP_PIN_CELLS) 670 return (ERANGE); 671 tuple_size = sizeof(pcell_t) * pin_cells; 672 673 bzero(pinmap, sizeof(pinmap)); 674 len = OF_getprop(node, "pin-map", pinmap, sizeof(pinmap)); 675 if (len <= 0) 676 return (ERANGE); 677 if (len % tuple_size) 678 return (ERANGE); 679 pins = len / tuple_size; 680 if (pins > pin_count) 681 return (ERANGE); 682 /* 683 * Fill out a "mpp[pin] => function" table. All pins unspecified in 684 * the 'pin-map' property are defaulted to 0 function i.e. GPIO. 685 */ 686 bzero(mpp, sizeof(mpp)); 687 pinmap_ptr = pinmap; 688 for (i = 0; i < pins; i++) { 689 mpp_pin = fdt32_to_cpu(*pinmap_ptr); 690 mpp_function = fdt32_to_cpu(*(pinmap_ptr + 1)); 691 mpp[mpp_pin] = mpp_function; 692 pinmap_ptr += pin_cells; 693 } 694 695 /* 696 * Prepare and program MPP control register values. 697 */ 698 ctrl_offset = 0; 699 for (i = 0; i < pin_count;) { 700 ctrl_val = 0; 701 702 for (j = 0; j < MPP_PINS_PER_REG; j++) { 703 if (i + j == pin_count - 1) 704 break; 705 ctrl_val |= MPP_SEL(i + j, mpp[i + j]); 706 } 707 i += MPP_PINS_PER_REG; 708 bus_space_write_4(fdtbus_bs_tag, start, ctrl_offset, 709 ctrl_val); 710 711#if defined(SOC_MV_ORION) 712 /* 713 * Third MPP reg on Orion SoC is placed 714 * non-linearly (with different offset). 715 */ 716 if (i == (2 * MPP_PINS_PER_REG)) 717 ctrl_offset = 0x50; 718 else 719#endif 720 ctrl_offset += 4; 721 } 722 723 return (0); 724} 725 726#define FDT_DEVMAP_MAX (1 + 2 + 1 + 1) 727static struct pmap_devmap fdt_devmap[FDT_DEVMAP_MAX] = { 728 { 0, 0, 0, 0, 0, } 729}; 730 731/* 732 * Construct pmap_devmap[] with DT-derived config data. 733 */ 734static int 735platform_devmap_init(void) 736{ 737 phandle_t root, child; 738 u_long base, size; 739 int i; 740 741 /* 742 * IMMR range. 743 */ 744 i = 0; 745 fdt_devmap[i].pd_va = fdt_immr_va; 746 fdt_devmap[i].pd_pa = fdt_immr_pa; 747 fdt_devmap[i].pd_size = fdt_immr_size; 748 fdt_devmap[i].pd_prot = VM_PROT_READ | VM_PROT_WRITE; 749 fdt_devmap[i].pd_cache = PTE_NOCACHE; 750 i++; 751 752 /* 753 * PCI range(s). 754 */ 755 if ((root = OF_finddevice("/")) == 0) 756 return (ENXIO); 757 758 for (child = OF_child(root); child != 0; child = OF_peer(child)) 759 if (fdt_is_type(child, "pci")) { 760 /* 761 * Check space: each PCI node will consume 2 devmap 762 * entries. 763 */ 764 if (i + 1 >= FDT_DEVMAP_MAX) { 765 return (ENOMEM); 766 break; 767 } 768 769 /* 770 * XXX this should account for PCI and multiple ranges 771 * of a given kind. 772 */ 773 if (fdt_pci_devmap(child, &fdt_devmap[i], 774 MV_PCIE_IO_BASE, MV_PCIE_MEM_BASE) != 0) 775 return (ENXIO); 776 i += 2; 777 } 778 779 /* 780 * CESA SRAM range. 781 */ 782 if ((child = OF_finddevice("sram")) != 0) 783 if (fdt_is_compatible(child, "mrvl,cesa-sram")) 784 goto moveon; 785 786 if ((child = fdt_find_compatible(root, "mrvl,cesa-sram", 0)) == 0) 787 /* No CESA SRAM node. */ 788 goto out; 789moveon: 790 if (i >= FDT_DEVMAP_MAX) 791 return (ENOMEM); 792 793 if (fdt_regsize(child, &base, &size) != 0) 794 return (EINVAL); 795 796 fdt_devmap[i].pd_va = MV_CESA_SRAM_BASE; /* XXX */ 797 fdt_devmap[i].pd_pa = base; 798 fdt_devmap[i].pd_size = size; 799 fdt_devmap[i].pd_prot = VM_PROT_READ | VM_PROT_WRITE; 800 fdt_devmap[i].pd_cache = PTE_NOCACHE; 801 802out: 803 pmap_devmap_bootstrap_table = &fdt_devmap[0]; 804 return (0); 805} 806 807struct arm32_dma_range * 808bus_dma_get_range(void) 809{ 810 811 return (NULL); 812} 813 814int 815bus_dma_get_range_nb(void) 816{ 817 818 return (0); 819} 820