pmap-v4.h revision 256708
1139735Simp/*- 2129198Scognet * Copyright (c) 1991 Regents of the University of California. 3129198Scognet * All rights reserved. 4129198Scognet * 5129198Scognet * This code is derived from software contributed to Berkeley by 6129198Scognet * the Systems Programming Group of the University of Utah Computer 7129198Scognet * Science Department and William Jolitz of UUNET Technologies Inc. 8129198Scognet * 9129198Scognet * Redistribution and use in source and binary forms, with or without 10129198Scognet * modification, are permitted provided that the following conditions 11129198Scognet * are met: 12129198Scognet * 1. Redistributions of source code must retain the above copyright 13129198Scognet * notice, this list of conditions and the following disclaimer. 14129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 15129198Scognet * notice, this list of conditions and the following disclaimer in the 16129198Scognet * documentation and/or other materials provided with the distribution. 17129198Scognet * 3. All advertising materials mentioning features or use of this software 18129198Scognet * must display the following acknowledgement: 19129198Scognet * This product includes software developed by the University of 20129198Scognet * California, Berkeley and its contributors. 21129198Scognet * 4. Neither the name of the University nor the names of its contributors 22129198Scognet * may be used to endorse or promote products derived from this software 23129198Scognet * without specific prior written permission. 24129198Scognet * 25129198Scognet * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26129198Scognet * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27129198Scognet * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28129198Scognet * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29129198Scognet * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30129198Scognet * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31129198Scognet * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32129198Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33129198Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34129198Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35129198Scognet * SUCH DAMAGE. 36129198Scognet * 37129198Scognet * Derived from hp300 version by Mike Hibler, this version by William 38129198Scognet * Jolitz uses a recursive map [a pde points to the page directory] to 39129198Scognet * map the page tables using the pagetables themselves. This is done to 40129198Scognet * reduce the impact on kernel virtual memory for lots of sparse address 41129198Scognet * space, and to reduce the cost of memory to each process. 42129198Scognet * 43129198Scognet * from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90 44129198Scognet * from: @(#)pmap.h 7.4 (Berkeley) 5/12/91 45129198Scognet * from: FreeBSD: src/sys/i386/include/pmap.h,v 1.70 2000/11/30 46129198Scognet * 47129198Scognet * $FreeBSD: head/sys/arm/include/pmap.h 256708 2013-10-17 21:38:14Z cognet $ 48129198Scognet */ 49129198Scognet 50129198Scognet#ifndef _MACHINE_PMAP_H_ 51129198Scognet#define _MACHINE_PMAP_H_ 52129198Scognet 53129198Scognet#include <machine/pte.h> 54159100Scognet#include <machine/cpuconf.h> 55129198Scognet/* 56129198Scognet * Pte related macros 57129198Scognet */ 58239268Sgonzo#if ARM_ARCH_6 || ARM_ARCH_7A 59239268Sgonzo#ifdef SMP 60239268Sgonzo#define PTE_NOCACHE 2 61239268Sgonzo#else 62239268Sgonzo#define PTE_NOCACHE 1 63239268Sgonzo#endif 64245147Sgonzo#define PTE_CACHE 6 65239268Sgonzo#define PTE_DEVICE 2 66256707Scognet#define PTE_PAGETABLE 6 67239268Sgonzo#else 68239268Sgonzo#define PTE_NOCACHE 1 69239268Sgonzo#define PTE_CACHE 2 70239268Sgonzo#define PTE_PAGETABLE 3 71239268Sgonzo#endif 72236992Simp 73239268Sgonzoenum mem_type { 74239268Sgonzo STRONG_ORD = 0, 75239268Sgonzo DEVICE_NOSHARE, 76239268Sgonzo DEVICE_SHARE, 77239268Sgonzo NRML_NOCACHE, 78239268Sgonzo NRML_IWT_OWT, 79239268Sgonzo NRML_IWB_OWB, 80239268Sgonzo NRML_IWBA_OWBA 81239268Sgonzo}; 82239268Sgonzo 83129198Scognet#ifndef LOCORE 84129198Scognet 85129198Scognet#include <sys/queue.h> 86222813Sattilio#include <sys/_cpuset.h> 87159325Salc#include <sys/_lock.h> 88159325Salc#include <sys/_mutex.h> 89129198Scognet 90129198Scognet#define PDESIZE sizeof(pd_entry_t) /* for assembly files */ 91129198Scognet#define PTESIZE sizeof(pt_entry_t) /* for assembly files */ 92129198Scognet 93129198Scognet#ifdef _KERNEL 94129198Scognet 95240983Salc#define vtophys(va) pmap_kextract((vm_offset_t)(va)) 96129198Scognet 97129198Scognet#endif 98129198Scognet 99244414Scognet#define pmap_page_get_memattr(m) ((m)->md.pv_memattr) 100254918Sraj#define pmap_page_is_write_mapped(m) (((m)->aflags & PGA_WRITEABLE) != 0) 101254918Sraj#if (ARM_MMU_V6 + ARM_MMU_V7) > 0 102254918Srajboolean_t pmap_page_is_mapped(vm_page_t); 103254918Sraj#else 104135641Scognet#define pmap_page_is_mapped(m) (!TAILQ_EMPTY(&(m)->md.pv_list)) 105254918Sraj#endif 106244414Scognetvoid pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma); 107195649Salc 108129198Scognet/* 109137362Scognet * Pmap stuff 110129198Scognet */ 111129198Scognet 112129198Scognet/* 113129198Scognet * This structure is used to hold a virtual<->physical address 114129198Scognet * association and is used mostly by bootstrap code 115129198Scognet */ 116129198Scognetstruct pv_addr { 117129198Scognet SLIST_ENTRY(pv_addr) pv_list; 118129198Scognet vm_offset_t pv_va; 119129198Scognet vm_paddr_t pv_pa; 120129198Scognet}; 121129198Scognet 122129198Scognetstruct pv_entry; 123250634Sgberstruct pv_chunk; 124129198Scognet 125129198Scognetstruct md_page { 126129198Scognet int pvh_attrs; 127244414Scognet vm_memattr_t pv_memattr; 128254536Sraj#if (ARM_MMU_V6 + ARM_MMU_V7) == 0 129194459Sthompsa vm_offset_t pv_kva; /* first kernel VA mapping */ 130254536Sraj#endif 131129198Scognet TAILQ_HEAD(,pv_entry) pv_list; 132129198Scognet}; 133129198Scognet 134129198Scognetstruct l1_ttable; 135129198Scognetstruct l2_dtable; 136129198Scognet 137129198Scognet 138129198Scognet/* 139129198Scognet * The number of L2 descriptor tables which can be tracked by an l2_dtable. 140129198Scognet * A bucket size of 16 provides for 16MB of contiguous virtual address 141129198Scognet * space per l2_dtable. Most processes will, therefore, require only two or 142129198Scognet * three of these to map their whole working set. 143129198Scognet */ 144129198Scognet#define L2_BUCKET_LOG2 4 145129198Scognet#define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2) 146129198Scognet/* 147129198Scognet * Given the above "L2-descriptors-per-l2_dtable" constant, the number 148129198Scognet * of l2_dtable structures required to track all possible page descriptors 149129198Scognet * mappable by an L1 translation table is given by the following constants: 150129198Scognet */ 151129198Scognet#define L2_LOG2 ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2) 152129198Scognet#define L2_SIZE (1 << L2_LOG2) 153129198Scognet 154129198Scognetstruct pmap { 155159325Salc struct mtx pm_mtx; 156129198Scognet u_int8_t pm_domain; 157129198Scognet struct l1_ttable *pm_l1; 158129198Scognet struct l2_dtable *pm_l2[L2_SIZE]; 159222813Sattilio cpuset_t pm_active; /* active on cpus */ 160129198Scognet struct pmap_statistics pm_stats; /* pmap statictics */ 161250634Sgber#if (ARM_MMU_V6 + ARM_MMU_V7) != 0 162250634Sgber TAILQ_HEAD(,pv_chunk) pm_pvchunk; /* list of mappings in pmap */ 163250634Sgber#else 164144760Scognet TAILQ_HEAD(,pv_entry) pm_pvlist; /* list of mappings in pmap */ 165250634Sgber#endif 166129198Scognet}; 167129198Scognet 168129198Scognettypedef struct pmap *pmap_t; 169129198Scognet 170129198Scognet#ifdef _KERNEL 171191873Salcextern struct pmap kernel_pmap_store; 172191873Salc#define kernel_pmap (&kernel_pmap_store) 173129198Scognet#define pmap_kernel() kernel_pmap 174137362Scognet 175159325Salc#define PMAP_ASSERT_LOCKED(pmap) \ 176159325Salc mtx_assert(&(pmap)->pm_mtx, MA_OWNED) 177159325Salc#define PMAP_LOCK(pmap) mtx_lock(&(pmap)->pm_mtx) 178159325Salc#define PMAP_LOCK_DESTROY(pmap) mtx_destroy(&(pmap)->pm_mtx) 179159325Salc#define PMAP_LOCK_INIT(pmap) mtx_init(&(pmap)->pm_mtx, "pmap", \ 180159325Salc NULL, MTX_DEF | MTX_DUPOK) 181159325Salc#define PMAP_OWNED(pmap) mtx_owned(&(pmap)->pm_mtx) 182159325Salc#define PMAP_MTX(pmap) (&(pmap)->pm_mtx) 183159325Salc#define PMAP_TRYLOCK(pmap) mtx_trylock(&(pmap)->pm_mtx) 184159325Salc#define PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->pm_mtx) 185129198Scognet#endif 186129198Scognet 187135641Scognet 188129198Scognet/* 189129198Scognet * For each vm_page_t, there is a list of all currently valid virtual 190164250Sru * mappings of that page. An entry is a pv_entry_t, the list is pv_list. 191129198Scognet */ 192129198Scognettypedef struct pv_entry { 193138413Scognet vm_offset_t pv_va; /* virtual address for mapping */ 194138413Scognet TAILQ_ENTRY(pv_entry) pv_list; 195250634Sgber int pv_flags; /* flags (wired, etc...) */ 196250634Sgber#if (ARM_MMU_V6 + ARM_MMU_V7) == 0 197250634Sgber pmap_t pv_pmap; /* pmap where mapping lies */ 198144760Scognet TAILQ_ENTRY(pv_entry) pv_plist; 199250634Sgber#endif 200129198Scognet} *pv_entry_t; 201129198Scognet 202250634Sgber/* 203250634Sgber * pv_entries are allocated in chunks per-process. This avoids the 204250634Sgber * need to track per-pmap assignments. 205250634Sgber */ 206250634Sgber#define _NPCM 8 207250634Sgber#define _NPCPV 252 208250634Sgber 209250634Sgberstruct pv_chunk { 210250634Sgber pmap_t pc_pmap; 211250634Sgber TAILQ_ENTRY(pv_chunk) pc_list; 212250634Sgber uint32_t pc_map[_NPCM]; /* bitmap; 1 = free */ 213250634Sgber uint32_t pc_dummy[3]; /* aligns pv_chunk to 4KB */ 214250634Sgber TAILQ_ENTRY(pv_chunk) pc_lru; 215250634Sgber struct pv_entry pc_pventry[_NPCPV]; 216250634Sgber}; 217250634Sgber 218129198Scognet#ifdef _KERNEL 219129198Scognet 220129198Scognetboolean_t pmap_get_pde_pte(pmap_t, vm_offset_t, pd_entry_t **, pt_entry_t **); 221129198Scognet 222129198Scognet/* 223129198Scognet * virtual address to page table entry and 224129198Scognet * to physical address. Likewise for alternate address space. 225129198Scognet * Note: these work recursively, thus vtopte of a pte will give 226129198Scognet * the corresponding pde that in turn maps it. 227129198Scognet */ 228129198Scognet 229135641Scognet/* 230135641Scognet * The current top of kernel VM. 231135641Scognet */ 232135641Scognetextern vm_offset_t pmap_curmaxkvaddr; 233135641Scognet 234132056Scognetstruct pcb; 235132056Scognet 236129198Scognetvoid pmap_set_pcb_pagedir(pmap_t, struct pcb *); 237129198Scognet/* Virtual address to page table entry */ 238129198Scognetstatic __inline pt_entry_t * 239129198Scognetvtopte(vm_offset_t va) 240129198Scognet{ 241129198Scognet pd_entry_t *pdep; 242129198Scognet pt_entry_t *ptep; 243129198Scognet 244129198Scognet if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == FALSE) 245129198Scognet return (NULL); 246129198Scognet return (ptep); 247129198Scognet} 248129198Scognet 249218311Simpextern vm_paddr_t phys_avail[]; 250129198Scognetextern vm_offset_t virtual_avail; 251129198Scognetextern vm_offset_t virtual_end; 252129198Scognet 253247046Salcvoid pmap_bootstrap(vm_offset_t firstaddr, struct pv_addr *l1pt); 254239268Sgonzoint pmap_change_attr(vm_offset_t, vm_size_t, int); 255129198Scognetvoid pmap_kenter(vm_offset_t va, vm_paddr_t pa); 256156191Scognetvoid pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa); 257184728Srajvoid *pmap_kenter_temp(vm_paddr_t pa, int i); 258142570Scognetvoid pmap_kenter_user(vm_offset_t va, vm_paddr_t pa); 259240983Salcvm_paddr_t pmap_kextract(vm_offset_t va); 260129198Scognetvoid pmap_kremove(vm_offset_t); 261129198Scognetvoid *pmap_mapdev(vm_offset_t, vm_size_t); 262129198Scognetvoid pmap_unmapdev(vm_offset_t, vm_size_t); 263129198Scognetvm_page_t pmap_use_pt(pmap_t, vm_offset_t); 264129198Scognetvoid pmap_debug(int); 265254918Sraj#if (ARM_MMU_V6 + ARM_MMU_V7) == 0 266129198Scognetvoid pmap_map_section(vm_offset_t, vm_offset_t, vm_offset_t, int, int); 267254918Sraj#endif 268129198Scognetvoid pmap_link_l2pt(vm_offset_t, vm_offset_t, struct pv_addr *); 269129198Scognetvm_size_t pmap_map_chunk(vm_offset_t, vm_offset_t, vm_offset_t, vm_size_t, int, int); 270129198Scognetvoid 271129198Scognetpmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot, 272129198Scognet int cache); 273129198Scognetint pmap_fault_fixup(pmap_t, vm_offset_t, vm_prot_t, int); 274239268Sgonzoint pmap_dmap_iscurrent(pmap_t pmap); 275129198Scognet 276129198Scognet/* 277129198Scognet * Definitions for MMU domains 278129198Scognet */ 279169756Scognet#define PMAP_DOMAINS 15 /* 15 'user' domains (1-15) */ 280169756Scognet#define PMAP_DOMAIN_KERNEL 0 /* The kernel uses domain #0 */ 281129198Scognet 282129198Scognet/* 283129198Scognet * The new pmap ensures that page-tables are always mapping Write-Thru. 284129198Scognet * Thus, on some platforms we can run fast and loose and avoid syncing PTEs 285129198Scognet * on every change. 286129198Scognet * 287129198Scognet * Unfortunately, not all CPUs have a write-through cache mode. So we 288129198Scognet * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs, 289129198Scognet * and if there is the chance for PTE syncs to be needed, we define 290129198Scognet * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run) 291129198Scognet * the code. 292129198Scognet */ 293129198Scognetextern int pmap_needs_pte_sync; 294129198Scognet 295129198Scognet/* 296129198Scognet * These macros define the various bit masks in the PTE. 297129198Scognet * 298129198Scognet * We use these macros since we use different bits on different processor 299129198Scognet * models. 300129198Scognet */ 301129198Scognet 302129198Scognet#define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C) 303171620Scognet#define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XSCALE_TEX(TEX_XSCALE_X)|\ 304171620Scognet L1_S_XSCALE_TEX(TEX_XSCALE_T)) 305129198Scognet 306129198Scognet#define L2_L_CACHE_MASK_generic (L2_B|L2_C) 307171620Scognet#define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_L_TEX(TEX_XSCALE_X) | \ 308171620Scognet L2_XSCALE_L_TEX(TEX_XSCALE_T)) 309129198Scognet 310129198Scognet#define L2_S_PROT_U_generic (L2_AP(AP_U)) 311129198Scognet#define L2_S_PROT_W_generic (L2_AP(AP_W)) 312129198Scognet#define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W) 313129198Scognet 314129198Scognet#define L2_S_PROT_U_xscale (L2_AP0(AP_U)) 315129198Scognet#define L2_S_PROT_W_xscale (L2_AP0(AP_W)) 316129198Scognet#define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W) 317129198Scognet 318129198Scognet#define L2_S_CACHE_MASK_generic (L2_B|L2_C) 319171620Scognet#define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_T_TEX(TEX_XSCALE_X)| \ 320171620Scognet L2_XSCALE_T_TEX(TEX_XSCALE_X)) 321129198Scognet 322129198Scognet#define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP) 323129198Scognet#define L1_S_PROTO_xscale (L1_TYPE_S) 324129198Scognet 325129198Scognet#define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2) 326129198Scognet#define L1_C_PROTO_xscale (L1_TYPE_C) 327129198Scognet 328129198Scognet#define L2_L_PROTO (L2_TYPE_L) 329129198Scognet 330129198Scognet#define L2_S_PROTO_generic (L2_TYPE_S) 331129198Scognet#define L2_S_PROTO_xscale (L2_TYPE_XSCALE_XS) 332129198Scognet 333129198Scognet/* 334129198Scognet * User-visible names for the ones that vary with MMU class. 335129198Scognet */ 336239268Sgonzo#if (ARM_MMU_V6 + ARM_MMU_V7) != 0 337239268Sgonzo#define L2_AP(x) (L2_AP0(x)) 338239268Sgonzo#else 339239268Sgonzo#define L2_AP(x) (L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x)) 340239268Sgonzo#endif 341129198Scognet 342129198Scognet#if ARM_NMMUS > 1 343129198Scognet/* More than one MMU class configured; use variables. */ 344129198Scognet#define L2_S_PROT_U pte_l2_s_prot_u 345129198Scognet#define L2_S_PROT_W pte_l2_s_prot_w 346129198Scognet#define L2_S_PROT_MASK pte_l2_s_prot_mask 347129198Scognet 348129198Scognet#define L1_S_CACHE_MASK pte_l1_s_cache_mask 349129198Scognet#define L2_L_CACHE_MASK pte_l2_l_cache_mask 350129198Scognet#define L2_S_CACHE_MASK pte_l2_s_cache_mask 351129198Scognet 352129198Scognet#define L1_S_PROTO pte_l1_s_proto 353129198Scognet#define L1_C_PROTO pte_l1_c_proto 354129198Scognet#define L2_S_PROTO pte_l2_s_proto 355129198Scognet 356129198Scognet#elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 357129198Scognet#define L2_S_PROT_U L2_S_PROT_U_generic 358129198Scognet#define L2_S_PROT_W L2_S_PROT_W_generic 359129198Scognet#define L2_S_PROT_MASK L2_S_PROT_MASK_generic 360129198Scognet 361129198Scognet#define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 362129198Scognet#define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 363129198Scognet#define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 364129198Scognet 365129198Scognet#define L1_S_PROTO L1_S_PROTO_generic 366129198Scognet#define L1_C_PROTO L1_C_PROTO_generic 367129198Scognet#define L2_S_PROTO L2_S_PROTO_generic 368129198Scognet 369129198Scognet#elif ARM_MMU_XSCALE == 1 370129198Scognet#define L2_S_PROT_U L2_S_PROT_U_xscale 371129198Scognet#define L2_S_PROT_W L2_S_PROT_W_xscale 372129198Scognet#define L2_S_PROT_MASK L2_S_PROT_MASK_xscale 373129198Scognet 374129198Scognet#define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale 375129198Scognet#define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale 376129198Scognet#define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale 377129198Scognet 378129198Scognet#define L1_S_PROTO L1_S_PROTO_xscale 379129198Scognet#define L1_C_PROTO L1_C_PROTO_xscale 380129198Scognet#define L2_S_PROTO L2_S_PROTO_xscale 381129198Scognet 382239268Sgonzo#elif (ARM_MMU_V6 + ARM_MMU_V7) != 0 383250928Sgber/* 384250928Sgber * AP[2:1] access permissions model: 385250928Sgber * 386250928Sgber * AP[2](APX) - Write Disable 387250928Sgber * AP[1] - User Enable 388250928Sgber * AP[0] - Reference Flag 389250928Sgber * 390250928Sgber * AP[2] AP[1] Kernel User 391250928Sgber * 0 0 R/W N 392250928Sgber * 0 1 R/W R/W 393250928Sgber * 1 0 R N 394250928Sgber * 1 1 R R 395250928Sgber * 396250928Sgber */ 397250928Sgber#define L2_S_PROT_R (0) /* kernel read */ 398250928Sgber#define L2_S_PROT_U (L2_AP0(2)) /* user read */ 399250928Sgber#define L2_S_REF (L2_AP0(1)) /* reference flag */ 400239268Sgonzo 401254532Sraj#define L2_S_PROT_MASK (L2_S_PROT_U|L2_S_PROT_R|L2_APX) 402250930Sgber#define L2_S_EXECUTABLE(pte) (!(pte & L2_XN)) 403239268Sgonzo#define L2_S_WRITABLE(pte) (!(pte & L2_APX)) 404250928Sgber#define L2_S_REFERENCED(pte) (!!(pte & L2_S_REF)) 405239268Sgonzo 406239268Sgonzo#ifndef SMP 407239268Sgonzo#define L1_S_CACHE_MASK (L1_S_TEX_MASK|L1_S_B|L1_S_C) 408239268Sgonzo#define L2_L_CACHE_MASK (L2_L_TEX_MASK|L2_B|L2_C) 409239268Sgonzo#define L2_S_CACHE_MASK (L2_S_TEX_MASK|L2_B|L2_C) 410239268Sgonzo#else 411239268Sgonzo#define L1_S_CACHE_MASK (L1_S_TEX_MASK|L1_S_B|L1_S_C|L1_SHARED) 412239268Sgonzo#define L2_L_CACHE_MASK (L2_L_TEX_MASK|L2_B|L2_C|L2_SHARED) 413239268Sgonzo#define L2_S_CACHE_MASK (L2_S_TEX_MASK|L2_B|L2_C|L2_SHARED) 414239268Sgonzo#endif /* SMP */ 415239268Sgonzo 416239268Sgonzo#define L1_S_PROTO (L1_TYPE_S) 417239268Sgonzo#define L1_C_PROTO (L1_TYPE_C) 418239268Sgonzo#define L2_S_PROTO (L2_TYPE_S) 419239268Sgonzo 420254918Sraj/* 421254918Sraj * Promotion to a 1MB (SECTION) mapping requires that the corresponding 422254918Sraj * 4KB (SMALL) page mappings have identical settings for the following fields: 423254918Sraj */ 424254918Sraj#define L2_S_PROMOTE (L2_S_REF | L2_SHARED | L2_S_PROT_MASK | \ 425254918Sraj L2_XN | L2_S_PROTO) 426254918Sraj 427254918Sraj/* 428254918Sraj * In order to compare 1MB (SECTION) entry settings with the 4KB (SMALL) 429254918Sraj * page mapping it is necessary to read and shift appropriate bits from 430254918Sraj * L1 entry to positions of the corresponding bits in the L2 entry. 431254918Sraj */ 432254918Sraj#define L1_S_DEMOTE(l1pd) ((((l1pd) & L1_S_PROTO) >> 0) | \ 433254918Sraj (((l1pd) & L1_SHARED) >> 6) | \ 434254918Sraj (((l1pd) & L1_S_REF) >> 6) | \ 435254918Sraj (((l1pd) & L1_S_PROT_MASK) >> 6) | \ 436254918Sraj (((l1pd) & L1_S_XN) >> 4)) 437254918Sraj 438239268Sgonzo#ifndef SMP 439239268Sgonzo#define ARM_L1S_STRONG_ORD (0) 440239268Sgonzo#define ARM_L1S_DEVICE_NOSHARE (L1_S_TEX(2)) 441239268Sgonzo#define ARM_L1S_DEVICE_SHARE (L1_S_B) 442239268Sgonzo#define ARM_L1S_NRML_NOCACHE (L1_S_TEX(1)) 443239268Sgonzo#define ARM_L1S_NRML_IWT_OWT (L1_S_C) 444239268Sgonzo#define ARM_L1S_NRML_IWB_OWB (L1_S_C|L1_S_B) 445239268Sgonzo#define ARM_L1S_NRML_IWBA_OWBA (L1_S_TEX(1)|L1_S_C|L1_S_B) 446239268Sgonzo 447239268Sgonzo#define ARM_L2L_STRONG_ORD (0) 448239268Sgonzo#define ARM_L2L_DEVICE_NOSHARE (L2_L_TEX(2)) 449239268Sgonzo#define ARM_L2L_DEVICE_SHARE (L2_B) 450239268Sgonzo#define ARM_L2L_NRML_NOCACHE (L2_L_TEX(1)) 451239268Sgonzo#define ARM_L2L_NRML_IWT_OWT (L2_C) 452239268Sgonzo#define ARM_L2L_NRML_IWB_OWB (L2_C|L2_B) 453239268Sgonzo#define ARM_L2L_NRML_IWBA_OWBA (L2_L_TEX(1)|L2_C|L2_B) 454239268Sgonzo 455239268Sgonzo#define ARM_L2S_STRONG_ORD (0) 456239268Sgonzo#define ARM_L2S_DEVICE_NOSHARE (L2_S_TEX(2)) 457239268Sgonzo#define ARM_L2S_DEVICE_SHARE (L2_B) 458239268Sgonzo#define ARM_L2S_NRML_NOCACHE (L2_S_TEX(1)) 459239268Sgonzo#define ARM_L2S_NRML_IWT_OWT (L2_C) 460239268Sgonzo#define ARM_L2S_NRML_IWB_OWB (L2_C|L2_B) 461239268Sgonzo#define ARM_L2S_NRML_IWBA_OWBA (L2_S_TEX(1)|L2_C|L2_B) 462239268Sgonzo#else 463239268Sgonzo#define ARM_L1S_STRONG_ORD (0) 464239268Sgonzo#define ARM_L1S_DEVICE_NOSHARE (L1_S_TEX(2)) 465239268Sgonzo#define ARM_L1S_DEVICE_SHARE (L1_S_B) 466239268Sgonzo#define ARM_L1S_NRML_NOCACHE (L1_S_TEX(1)|L1_SHARED) 467239268Sgonzo#define ARM_L1S_NRML_IWT_OWT (L1_S_C|L1_SHARED) 468239268Sgonzo#define ARM_L1S_NRML_IWB_OWB (L1_S_C|L1_S_B|L1_SHARED) 469239268Sgonzo#define ARM_L1S_NRML_IWBA_OWBA (L1_S_TEX(1)|L1_S_C|L1_S_B|L1_SHARED) 470239268Sgonzo 471239268Sgonzo#define ARM_L2L_STRONG_ORD (0) 472239268Sgonzo#define ARM_L2L_DEVICE_NOSHARE (L2_L_TEX(2)) 473239268Sgonzo#define ARM_L2L_DEVICE_SHARE (L2_B) 474239268Sgonzo#define ARM_L2L_NRML_NOCACHE (L2_L_TEX(1)|L2_SHARED) 475239268Sgonzo#define ARM_L2L_NRML_IWT_OWT (L2_C|L2_SHARED) 476239268Sgonzo#define ARM_L2L_NRML_IWB_OWB (L2_C|L2_B|L2_SHARED) 477239268Sgonzo#define ARM_L2L_NRML_IWBA_OWBA (L2_L_TEX(1)|L2_C|L2_B|L2_SHARED) 478239268Sgonzo 479239268Sgonzo#define ARM_L2S_STRONG_ORD (0) 480239268Sgonzo#define ARM_L2S_DEVICE_NOSHARE (L2_S_TEX(2)) 481239268Sgonzo#define ARM_L2S_DEVICE_SHARE (L2_B) 482239268Sgonzo#define ARM_L2S_NRML_NOCACHE (L2_S_TEX(1)|L2_SHARED) 483239268Sgonzo#define ARM_L2S_NRML_IWT_OWT (L2_C|L2_SHARED) 484239268Sgonzo#define ARM_L2S_NRML_IWB_OWB (L2_C|L2_B|L2_SHARED) 485239268Sgonzo#define ARM_L2S_NRML_IWBA_OWBA (L2_S_TEX(1)|L2_C|L2_B|L2_SHARED) 486239268Sgonzo#endif /* SMP */ 487129198Scognet#endif /* ARM_NMMUS > 1 */ 488129198Scognet 489129198Scognet#if (ARM_MMU_SA1 == 1) && (ARM_NMMUS == 1) 490129198Scognet#define PMAP_NEEDS_PTE_SYNC 1 491129198Scognet#define PMAP_INCLUDE_PTE_SYNC 492256707Scognet#elif defined(CPU_XSCALE_81342) || defined(ARM_ARCH_7) || defined(ARM_ARCH_7A) 493171620Scognet#define PMAP_NEEDS_PTE_SYNC 1 494171620Scognet#define PMAP_INCLUDE_PTE_SYNC 495129198Scognet#elif (ARM_MMU_SA1 == 0) 496129198Scognet#define PMAP_NEEDS_PTE_SYNC 0 497129198Scognet#endif 498129198Scognet 499129198Scognet/* 500129198Scognet * These macros return various bits based on kernel/user and protection. 501129198Scognet * Note that the compiler will usually fold these at compile time. 502129198Scognet */ 503239268Sgonzo#if (ARM_MMU_V6 + ARM_MMU_V7) == 0 504239268Sgonzo 505239268Sgonzo#define L1_S_PROT_U (L1_S_AP(AP_U)) 506239268Sgonzo#define L1_S_PROT_W (L1_S_AP(AP_W)) 507239268Sgonzo#define L1_S_PROT_MASK (L1_S_PROT_U|L1_S_PROT_W) 508239268Sgonzo#define L1_S_WRITABLE(pd) ((pd) & L1_S_PROT_W) 509239268Sgonzo 510129198Scognet#define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \ 511129198Scognet (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : 0)) 512129198Scognet 513239268Sgonzo#define L2_L_PROT_U (L2_AP(AP_U)) 514239268Sgonzo#define L2_L_PROT_W (L2_AP(AP_W)) 515239268Sgonzo#define L2_L_PROT_MASK (L2_L_PROT_U|L2_L_PROT_W) 516239268Sgonzo 517129198Scognet#define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \ 518129198Scognet (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : 0)) 519129198Scognet 520129198Scognet#define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \ 521129198Scognet (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : 0)) 522239268Sgonzo#else 523239268Sgonzo#define L1_S_PROT_U (L1_S_AP(AP_U)) 524254918Sraj#define L1_S_PROT_W (L1_S_APX) /* Write disable */ 525254918Sraj#define L1_S_PROT_MASK (L1_S_PROT_W|L1_S_PROT_U) 526254918Sraj#define L1_S_REF (L1_S_AP(AP_REF)) /* Reference flag */ 527254918Sraj#define L1_S_WRITABLE(pd) (!((pd) & L1_S_PROT_W)) 528254918Sraj#define L1_S_REFERENCED(pd) ((pd) & L1_S_REF) 529129198Scognet 530254918Sraj#define L1_S_PROT(ku, pr) (((((ku) == PTE_KERNEL) ? 0 : L1_S_PROT_U) | \ 531254918Sraj (((pr) & VM_PROT_WRITE) ? 0 : L1_S_PROT_W) | \ 532254918Sraj (((pr) & VM_PROT_EXECUTE) ? 0 : L1_S_XN))) 533239268Sgonzo 534239268Sgonzo#define L2_L_PROT_MASK (L2_APX|L2_AP0(0x3)) 535239268Sgonzo#define L2_L_PROT(ku, pr) (L2_L_PROT_MASK & ~((((ku) == PTE_KERNEL) ? L2_S_PROT_U : 0) | \ 536239268Sgonzo (((pr) & VM_PROT_WRITE) ? L2_APX : 0))) 537239268Sgonzo 538239268Sgonzo#define L2_S_PROT(ku, pr) (L2_S_PROT_MASK & ~((((ku) == PTE_KERNEL) ? L2_S_PROT_U : 0) | \ 539239268Sgonzo (((pr) & VM_PROT_WRITE) ? L2_APX : 0))) 540239268Sgonzo 541239268Sgonzo#endif 542239268Sgonzo 543129198Scognet/* 544129198Scognet * Macros to test if a mapping is mappable with an L1 Section mapping 545129198Scognet * or an L2 Large Page mapping. 546129198Scognet */ 547129198Scognet#define L1_S_MAPPABLE_P(va, pa, size) \ 548129198Scognet ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE) 549129198Scognet 550129198Scognet#define L2_L_MAPPABLE_P(va, pa, size) \ 551129198Scognet ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE) 552129198Scognet 553129198Scognet/* 554129198Scognet * Provide a fallback in case we were not able to determine it at 555129198Scognet * compile-time. 556129198Scognet */ 557129198Scognet#ifndef PMAP_NEEDS_PTE_SYNC 558129198Scognet#define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync 559129198Scognet#define PMAP_INCLUDE_PTE_SYNC 560129198Scognet#endif 561129198Scognet 562256707Scognet#ifdef ARM_L2_PIPT 563256707Scognet#define _sync_l2(pte, size) cpu_l2cache_wb_range(vtophys(pte), size) 564256707Scognet#else 565256708Scognet#define _sync_l2(pte, size) cpu_l2cache_wb_range(pte, size) 566256707Scognet#endif 567256707Scognet 568129198Scognet#define PTE_SYNC(pte) \ 569129198Scognetdo { \ 570171620Scognet if (PMAP_NEEDS_PTE_SYNC) { \ 571129198Scognet cpu_dcache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\ 572256707Scognet cpu_drain_writebuf(); \ 573256707Scognet _sync_l2((vm_offset_t)(pte), sizeof(pt_entry_t));\ 574228530Sraj } else \ 575228530Sraj cpu_drain_writebuf(); \ 576129198Scognet} while (/*CONSTCOND*/0) 577129198Scognet 578129198Scognet#define PTE_SYNC_RANGE(pte, cnt) \ 579129198Scognetdo { \ 580129198Scognet if (PMAP_NEEDS_PTE_SYNC) { \ 581129198Scognet cpu_dcache_wb_range((vm_offset_t)(pte), \ 582129198Scognet (cnt) << 2); /* * sizeof(pt_entry_t) */ \ 583256707Scognet cpu_drain_writebuf(); \ 584256707Scognet _sync_l2((vm_offset_t)(pte), \ 585171620Scognet (cnt) << 2); /* * sizeof(pt_entry_t) */ \ 586228530Sraj } else \ 587228530Sraj cpu_drain_writebuf(); \ 588129198Scognet} while (/*CONSTCOND*/0) 589129198Scognet 590129198Scognetextern pt_entry_t pte_l1_s_cache_mode; 591129198Scognetextern pt_entry_t pte_l1_s_cache_mask; 592129198Scognet 593129198Scognetextern pt_entry_t pte_l2_l_cache_mode; 594129198Scognetextern pt_entry_t pte_l2_l_cache_mask; 595129198Scognet 596129198Scognetextern pt_entry_t pte_l2_s_cache_mode; 597129198Scognetextern pt_entry_t pte_l2_s_cache_mask; 598129198Scognet 599129198Scognetextern pt_entry_t pte_l1_s_cache_mode_pt; 600129198Scognetextern pt_entry_t pte_l2_l_cache_mode_pt; 601129198Scognetextern pt_entry_t pte_l2_s_cache_mode_pt; 602129198Scognet 603129198Scognetextern pt_entry_t pte_l2_s_prot_u; 604129198Scognetextern pt_entry_t pte_l2_s_prot_w; 605129198Scognetextern pt_entry_t pte_l2_s_prot_mask; 606236992Simp 607129198Scognetextern pt_entry_t pte_l1_s_proto; 608129198Scognetextern pt_entry_t pte_l1_c_proto; 609129198Scognetextern pt_entry_t pte_l2_s_proto; 610129198Scognet 611129198Scognetextern void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t); 612248280Skibextern void (*pmap_copy_page_offs_func)(vm_paddr_t a_phys, 613248280Skib vm_offset_t a_offs, vm_paddr_t b_phys, vm_offset_t b_offs, int cnt); 614129198Scognetextern void (*pmap_zero_page_func)(vm_paddr_t, int, int); 615129198Scognet 616239268Sgonzo#if (ARM_MMU_GENERIC + ARM_MMU_V6 + ARM_MMU_V7 + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_81342) 617129198Scognetvoid pmap_copy_page_generic(vm_paddr_t, vm_paddr_t); 618129198Scognetvoid pmap_zero_page_generic(vm_paddr_t, int, int); 619129198Scognet 620129198Scognetvoid pmap_pte_init_generic(void); 621129198Scognet#if defined(CPU_ARM8) 622129198Scognetvoid pmap_pte_init_arm8(void); 623129198Scognet#endif 624129198Scognet#if defined(CPU_ARM9) 625129198Scognetvoid pmap_pte_init_arm9(void); 626129198Scognet#endif /* CPU_ARM9 */ 627129198Scognet#if defined(CPU_ARM10) 628129198Scognetvoid pmap_pte_init_arm10(void); 629129198Scognet#endif /* CPU_ARM10 */ 630239268Sgonzo#if (ARM_MMU_V6 + ARM_MMU_V7) != 0 631239268Sgonzovoid pmap_pte_init_mmu_v6(void); 632244476Sgonzo#endif /* (ARM_MMU_V6 + ARM_MMU_V7) != 0 */ 633129198Scognet#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 634129198Scognet 635129198Scognet#if /* ARM_MMU_SA1 == */1 636129198Scognetvoid pmap_pte_init_sa1(void); 637129198Scognet#endif /* ARM_MMU_SA1 == 1 */ 638129198Scognet 639129198Scognet#if ARM_MMU_XSCALE == 1 640129198Scognetvoid pmap_copy_page_xscale(vm_paddr_t, vm_paddr_t); 641129198Scognetvoid pmap_zero_page_xscale(vm_paddr_t, int, int); 642129198Scognet 643129198Scognetvoid pmap_pte_init_xscale(void); 644129198Scognet 645129198Scognetvoid xscale_setup_minidata(vm_offset_t, vm_offset_t, vm_offset_t); 646129198Scognet 647135641Scognetvoid pmap_use_minicache(vm_offset_t, vm_size_t); 648129198Scognet#endif /* ARM_MMU_XSCALE == 1 */ 649171620Scognet#if defined(CPU_XSCALE_81342) 650171620Scognet#define ARM_HAVE_SUPERSECTIONS 651171620Scognet#endif 652171620Scognet 653129198Scognet#define PTE_KERNEL 0 654129198Scognet#define PTE_USER 1 655129198Scognet#define l1pte_valid(pde) ((pde) != 0) 656129198Scognet#define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S) 657129198Scognet#define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C) 658129198Scognet#define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F) 659129198Scognet 660129198Scognet#define l2pte_index(v) (((v) & L2_ADDR_BITS) >> L2_S_SHIFT) 661129198Scognet#define l2pte_valid(pte) ((pte) != 0) 662129198Scognet#define l2pte_pa(pte) ((pte) & L2_S_FRAME) 663129198Scognet#define l2pte_minidata(pte) (((pte) & \ 664129198Scognet (L2_B | L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))\ 665129198Scognet == (L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X))) 666129198Scognet 667129198Scognet/* L1 and L2 page table macros */ 668129198Scognet#define pmap_pde_v(pde) l1pte_valid(*(pde)) 669129198Scognet#define pmap_pde_section(pde) l1pte_section_p(*(pde)) 670129198Scognet#define pmap_pde_page(pde) l1pte_page_p(*(pde)) 671129198Scognet#define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde)) 672129198Scognet 673129198Scognet#define pmap_pte_v(pte) l2pte_valid(*(pte)) 674129198Scognet#define pmap_pte_pa(pte) l2pte_pa(*(pte)) 675129198Scognet 676129198Scognet/* 677129198Scognet * Flags that indicate attributes of pages or mappings of pages. 678129198Scognet * 679129198Scognet * The PVF_MOD and PVF_REF flags are stored in the mdpage for each 680129198Scognet * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual 681129198Scognet * pv_entry's for each page. They live in the same "namespace" so 682129198Scognet * that we can clear multiple attributes at a time. 683129198Scognet * 684129198Scognet * Note the "non-cacheable" flag generally means the page has 685129198Scognet * multiple mappings in a given address space. 686129198Scognet */ 687129198Scognet#define PVF_MOD 0x01 /* page is modified */ 688129198Scognet#define PVF_REF 0x02 /* page is referenced */ 689129198Scognet#define PVF_WIRED 0x04 /* mapping is wired */ 690129198Scognet#define PVF_WRITE 0x08 /* mapping is writable */ 691129198Scognet#define PVF_EXEC 0x10 /* mapping is executable */ 692175840Scognet#define PVF_NC 0x20 /* mapping is non-cacheable */ 693175840Scognet#define PVF_MWC 0x40 /* mapping is used multiple times in userland */ 694194459Sthompsa#define PVF_UNMAN 0x80 /* mapping is unmanaged */ 695129198Scognet 696129198Scognetvoid vector_page_setprot(int); 697135641Scognet 698129198Scognet/* 699135641Scognet * This structure is used by machine-dependent code to describe 700135641Scognet * static mappings of devices, created at bootstrap time. 701129198Scognet */ 702135641Scognetstruct pmap_devmap { 703135641Scognet vm_offset_t pd_va; /* virtual address */ 704135641Scognet vm_paddr_t pd_pa; /* physical address */ 705135641Scognet vm_size_t pd_size; /* size of region */ 706135641Scognet vm_prot_t pd_prot; /* protection code */ 707135641Scognet int pd_cache; /* cache attributes */ 708135641Scognet}; 709129198Scognet 710135641Scognetconst struct pmap_devmap *pmap_devmap_find_pa(vm_paddr_t, vm_size_t); 711135641Scognetconst struct pmap_devmap *pmap_devmap_find_va(vm_offset_t, vm_size_t); 712129198Scognet 713135641Scognetvoid pmap_devmap_bootstrap(vm_offset_t, const struct pmap_devmap *); 714135641Scognetvoid pmap_devmap_register(const struct pmap_devmap *); 715137362Scognet 716147114Scognet#define SECTION_CACHE 0x1 717147114Scognet#define SECTION_PT 0x2 718147114Scognetvoid pmap_kenter_section(vm_offset_t, vm_paddr_t, int flags); 719171620Scognet#ifdef ARM_HAVE_SUPERSECTIONS 720170582Scognetvoid pmap_kenter_supersection(vm_offset_t, uint64_t, int flags); 721171620Scognet#endif 722147114Scognet 723137362Scognetextern char *_tmppt; 724137362Scognet 725152128Scognetvoid pmap_postinit(void); 726152128Scognet 727147114Scognet#ifdef ARM_USE_SMALL_ALLOC 728147114Scognetvoid arm_add_smallalloc_pages(void *, void *, int, int); 729161105Scognetvm_offset_t arm_ptovirt(vm_paddr_t); 730161105Scognetvoid arm_init_smallalloc(void); 731147114Scognetstruct arm_small_page { 732147114Scognet void *addr; 733147114Scognet TAILQ_ENTRY(arm_small_page) pg_list; 734147114Scognet}; 735150867Scognet 736150936Scognet#endif 737156191Scognet 738166063Scognet#define ARM_NOCACHE_KVA_SIZE 0x1000000 739156191Scognetextern vm_offset_t arm_nocache_startaddr; 740156191Scognetvoid *arm_remap_nocache(void *, vm_size_t); 741156191Scognetvoid arm_unmap_nocache(void *, vm_size_t); 742156191Scognet 743150867Scognetextern vm_paddr_t dump_avail[]; 744129198Scognet#endif /* _KERNEL */ 745129198Scognet 746129198Scognet#endif /* !LOCORE */ 747129198Scognet 748129198Scognet#endif /* !_MACHINE_PMAP_H_ */ 749