pmap-v4.h revision 166063
1139735Simp/*- 2129198Scognet * Copyright (c) 1991 Regents of the University of California. 3129198Scognet * All rights reserved. 4129198Scognet * 5129198Scognet * This code is derived from software contributed to Berkeley by 6129198Scognet * the Systems Programming Group of the University of Utah Computer 7129198Scognet * Science Department and William Jolitz of UUNET Technologies Inc. 8129198Scognet * 9129198Scognet * Redistribution and use in source and binary forms, with or without 10129198Scognet * modification, are permitted provided that the following conditions 11129198Scognet * are met: 12129198Scognet * 1. Redistributions of source code must retain the above copyright 13129198Scognet * notice, this list of conditions and the following disclaimer. 14129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 15129198Scognet * notice, this list of conditions and the following disclaimer in the 16129198Scognet * documentation and/or other materials provided with the distribution. 17129198Scognet * 3. All advertising materials mentioning features or use of this software 18129198Scognet * must display the following acknowledgement: 19129198Scognet * This product includes software developed by the University of 20129198Scognet * California, Berkeley and its contributors. 21129198Scognet * 4. Neither the name of the University nor the names of its contributors 22129198Scognet * may be used to endorse or promote products derived from this software 23129198Scognet * without specific prior written permission. 24129198Scognet * 25129198Scognet * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26129198Scognet * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27129198Scognet * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28129198Scognet * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29129198Scognet * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30129198Scognet * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31129198Scognet * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32129198Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33129198Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34129198Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35129198Scognet * SUCH DAMAGE. 36129198Scognet * 37129198Scognet * Derived from hp300 version by Mike Hibler, this version by William 38129198Scognet * Jolitz uses a recursive map [a pde points to the page directory] to 39129198Scognet * map the page tables using the pagetables themselves. This is done to 40129198Scognet * reduce the impact on kernel virtual memory for lots of sparse address 41129198Scognet * space, and to reduce the cost of memory to each process. 42129198Scognet * 43129198Scognet * from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90 44129198Scognet * from: @(#)pmap.h 7.4 (Berkeley) 5/12/91 45129198Scognet * from: FreeBSD: src/sys/i386/include/pmap.h,v 1.70 2000/11/30 46129198Scognet * 47129198Scognet * $FreeBSD: head/sys/arm/include/pmap.h 166063 2007-01-17 00:53:05Z cognet $ 48129198Scognet */ 49129198Scognet 50129198Scognet#ifndef _MACHINE_PMAP_H_ 51129198Scognet#define _MACHINE_PMAP_H_ 52129198Scognet 53129198Scognet#include <machine/pte.h> 54159100Scognet#include <machine/cpuconf.h> 55129198Scognet/* 56129198Scognet * Pte related macros 57129198Scognet */ 58129198Scognet#define PTE_NOCACHE 0 59129198Scognet#define PTE_CACHE 1 60137362Scognet#define PTE_PAGETABLE 2 61129198Scognet 62129198Scognet#ifndef LOCORE 63129198Scognet 64129198Scognet#include <sys/queue.h> 65159325Salc#include <sys/_lock.h> 66159325Salc#include <sys/_mutex.h> 67129198Scognet 68129198Scognet#define PDESIZE sizeof(pd_entry_t) /* for assembly files */ 69129198Scognet#define PTESIZE sizeof(pt_entry_t) /* for assembly files */ 70129198Scognet 71129198Scognet#ifdef _KERNEL 72129198Scognet 73135641Scognet#define vtophys(va) pmap_extract(pmap_kernel(), (vm_offset_t)(va)) 74135641Scognet#define pmap_kextract(va) pmap_extract(pmap_kernel(), (vm_offset_t)(va)) 75129198Scognet 76129198Scognet#endif 77129198Scognet 78135641Scognet#define pmap_page_is_mapped(m) (!TAILQ_EMPTY(&(m)->md.pv_list)) 79129198Scognet/* 80137362Scognet * Pmap stuff 81129198Scognet */ 82129198Scognet 83129198Scognet/* 84129198Scognet * This structure is used to hold a virtual<->physical address 85129198Scognet * association and is used mostly by bootstrap code 86129198Scognet */ 87129198Scognetstruct pv_addr { 88129198Scognet SLIST_ENTRY(pv_addr) pv_list; 89129198Scognet vm_offset_t pv_va; 90129198Scognet vm_paddr_t pv_pa; 91129198Scognet}; 92129198Scognet 93129198Scognetstruct pv_entry; 94129198Scognet 95129198Scognetstruct md_page { 96129198Scognet int pvh_attrs; 97129198Scognet u_int uro_mappings; 98129198Scognet u_int urw_mappings; 99129198Scognet union { 100129198Scognet u_short s_mappings[2]; /* Assume kernel count <= 65535 */ 101129198Scognet u_int i_mappings; 102129198Scognet } k_u; 103129198Scognet#define kro_mappings k_u.s_mappings[0] 104129198Scognet#define krw_mappings k_u.s_mappings[1] 105129198Scognet#define k_mappings k_u.i_mappings 106129198Scognet int pv_list_count; 107129198Scognet TAILQ_HEAD(,pv_entry) pv_list; 108129198Scognet}; 109129198Scognet 110129198Scognet#define VM_MDPAGE_INIT(pg) \ 111129198Scognetdo { \ 112129198Scognet TAILQ_INIT(&pg->pv_list); \ 113129198Scognet mtx_init(&(pg)->md_page.pvh_mtx, "MDPAGE Mutex", NULL, MTX_DEV);\ 114129198Scognet (pg)->mdpage.pvh_attrs = 0; \ 115129198Scognet (pg)->mdpage.uro_mappings = 0; \ 116129198Scognet (pg)->mdpage.urw_mappings = 0; \ 117129198Scognet (pg)->mdpage.k_mappings = 0; \ 118129198Scognet} while (/*CONSTCOND*/0) 119129198Scognet 120129198Scognetstruct l1_ttable; 121129198Scognetstruct l2_dtable; 122129198Scognet 123129198Scognet 124129198Scognet/* 125129198Scognet * The number of L2 descriptor tables which can be tracked by an l2_dtable. 126129198Scognet * A bucket size of 16 provides for 16MB of contiguous virtual address 127129198Scognet * space per l2_dtable. Most processes will, therefore, require only two or 128129198Scognet * three of these to map their whole working set. 129129198Scognet */ 130129198Scognet#define L2_BUCKET_LOG2 4 131129198Scognet#define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2) 132129198Scognet/* 133129198Scognet * Given the above "L2-descriptors-per-l2_dtable" constant, the number 134129198Scognet * of l2_dtable structures required to track all possible page descriptors 135129198Scognet * mappable by an L1 translation table is given by the following constants: 136129198Scognet */ 137129198Scognet#define L2_LOG2 ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2) 138129198Scognet#define L2_SIZE (1 << L2_LOG2) 139129198Scognet 140129198Scognetstruct pmap { 141159325Salc struct mtx pm_mtx; 142129198Scognet u_int8_t pm_domain; 143129198Scognet struct l1_ttable *pm_l1; 144129198Scognet struct l2_dtable *pm_l2[L2_SIZE]; 145129198Scognet pd_entry_t *pm_pdir; /* KVA of page directory */ 146129198Scognet int pm_count; /* reference count */ 147129198Scognet int pm_active; /* active on cpus */ 148129198Scognet struct pmap_statistics pm_stats; /* pmap statictics */ 149144760Scognet TAILQ_HEAD(,pv_entry) pm_pvlist; /* list of mappings in pmap */ 150129198Scognet}; 151129198Scognet 152129198Scognettypedef struct pmap *pmap_t; 153129198Scognet 154129198Scognet#ifdef _KERNEL 155129198Scognetextern pmap_t kernel_pmap; 156129198Scognet#define pmap_kernel() kernel_pmap 157137362Scognet 158159325Salc#define PMAP_ASSERT_LOCKED(pmap) \ 159159325Salc mtx_assert(&(pmap)->pm_mtx, MA_OWNED) 160159325Salc#define PMAP_LOCK(pmap) mtx_lock(&(pmap)->pm_mtx) 161159325Salc#define PMAP_LOCK_DESTROY(pmap) mtx_destroy(&(pmap)->pm_mtx) 162159325Salc#define PMAP_LOCK_INIT(pmap) mtx_init(&(pmap)->pm_mtx, "pmap", \ 163159325Salc NULL, MTX_DEF | MTX_DUPOK) 164159325Salc#define PMAP_OWNED(pmap) mtx_owned(&(pmap)->pm_mtx) 165159325Salc#define PMAP_MTX(pmap) (&(pmap)->pm_mtx) 166159325Salc#define PMAP_TRYLOCK(pmap) mtx_trylock(&(pmap)->pm_mtx) 167159325Salc#define PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->pm_mtx) 168129198Scognet#endif 169129198Scognet 170135641Scognet 171129198Scognet/* 172129198Scognet * For each vm_page_t, there is a list of all currently valid virtual 173164250Sru * mappings of that page. An entry is a pv_entry_t, the list is pv_list. 174129198Scognet */ 175129198Scognettypedef struct pv_entry { 176138413Scognet pmap_t pv_pmap; /* pmap where mapping lies */ 177138413Scognet vm_offset_t pv_va; /* virtual address for mapping */ 178138413Scognet TAILQ_ENTRY(pv_entry) pv_list; 179144760Scognet TAILQ_ENTRY(pv_entry) pv_plist; 180129198Scognet int pv_flags; /* flags (wired, etc...) */ 181129198Scognet} *pv_entry_t; 182129198Scognet 183129198Scognet#define PV_ENTRY_NULL ((pv_entry_t) 0) 184129198Scognet 185129198Scognet#ifdef _KERNEL 186129198Scognet 187129198Scognetboolean_t pmap_get_pde_pte(pmap_t, vm_offset_t, pd_entry_t **, pt_entry_t **); 188129198Scognet 189129198Scognet/* 190129198Scognet * virtual address to page table entry and 191129198Scognet * to physical address. Likewise for alternate address space. 192129198Scognet * Note: these work recursively, thus vtopte of a pte will give 193129198Scognet * the corresponding pde that in turn maps it. 194129198Scognet */ 195129198Scognet 196135641Scognet/* 197135641Scognet * The current top of kernel VM. 198135641Scognet */ 199135641Scognetextern vm_offset_t pmap_curmaxkvaddr; 200135641Scognet 201132056Scognetstruct pcb; 202132056Scognet 203129198Scognetvoid pmap_set_pcb_pagedir(pmap_t, struct pcb *); 204129198Scognet/* Virtual address to page table entry */ 205129198Scognetstatic __inline pt_entry_t * 206129198Scognetvtopte(vm_offset_t va) 207129198Scognet{ 208129198Scognet pd_entry_t *pdep; 209129198Scognet pt_entry_t *ptep; 210129198Scognet 211129198Scognet if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == FALSE) 212129198Scognet return (NULL); 213129198Scognet return (ptep); 214129198Scognet} 215129198Scognet 216129198Scognetextern vm_offset_t phys_avail[]; 217129198Scognetextern vm_offset_t virtual_avail; 218129198Scognetextern vm_offset_t virtual_end; 219129198Scognet 220129198Scognetvoid pmap_bootstrap(vm_offset_t, vm_offset_t, struct pv_addr *); 221129198Scognetvoid pmap_kenter(vm_offset_t va, vm_paddr_t pa); 222156191Scognetvoid pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa); 223142570Scognetvoid pmap_kenter_user(vm_offset_t va, vm_paddr_t pa); 224129198Scognetvoid pmap_kremove(vm_offset_t); 225129198Scognetvoid *pmap_mapdev(vm_offset_t, vm_size_t); 226129198Scognetvoid pmap_unmapdev(vm_offset_t, vm_size_t); 227129198Scognetvm_page_t pmap_use_pt(pmap_t, vm_offset_t); 228129198Scognetvoid pmap_debug(int); 229129198Scognetvoid pmap_map_section(vm_offset_t, vm_offset_t, vm_offset_t, int, int); 230129198Scognetvoid pmap_link_l2pt(vm_offset_t, vm_offset_t, struct pv_addr *); 231129198Scognetvm_size_t pmap_map_chunk(vm_offset_t, vm_offset_t, vm_offset_t, vm_size_t, int, int); 232129198Scognetvoid 233129198Scognetpmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot, 234129198Scognet int cache); 235129198Scognetint pmap_fault_fixup(pmap_t, vm_offset_t, vm_prot_t, int); 236129198Scognet 237129198Scognet/* 238129198Scognet * Definitions for MMU domains 239129198Scognet */ 240129198Scognet#define PMAP_DOMAINS 15 /* 15 'user' domains (0-14) */ 241129198Scognet#define PMAP_DOMAIN_KERNEL 15 /* The kernel uses domain #15 */ 242129198Scognet 243129198Scognet/* 244129198Scognet * The new pmap ensures that page-tables are always mapping Write-Thru. 245129198Scognet * Thus, on some platforms we can run fast and loose and avoid syncing PTEs 246129198Scognet * on every change. 247129198Scognet * 248129198Scognet * Unfortunately, not all CPUs have a write-through cache mode. So we 249129198Scognet * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs, 250129198Scognet * and if there is the chance for PTE syncs to be needed, we define 251129198Scognet * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run) 252129198Scognet * the code. 253129198Scognet */ 254129198Scognetextern int pmap_needs_pte_sync; 255129198Scognet 256129198Scognet/* 257129198Scognet * These macros define the various bit masks in the PTE. 258129198Scognet * 259129198Scognet * We use these macros since we use different bits on different processor 260129198Scognet * models. 261129198Scognet */ 262129198Scognet#define L1_S_PROT_U (L1_S_AP(AP_U)) 263129198Scognet#define L1_S_PROT_W (L1_S_AP(AP_W)) 264129198Scognet#define L1_S_PROT_MASK (L1_S_PROT_U|L1_S_PROT_W) 265129198Scognet 266129198Scognet#define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C) 267129198Scognet#define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XSCALE_TEX(TEX_XSCALE_X)) 268129198Scognet 269129198Scognet#define L2_L_PROT_U (L2_AP(AP_U)) 270129198Scognet#define L2_L_PROT_W (L2_AP(AP_W)) 271129198Scognet#define L2_L_PROT_MASK (L2_L_PROT_U|L2_L_PROT_W) 272129198Scognet 273129198Scognet#define L2_L_CACHE_MASK_generic (L2_B|L2_C) 274129198Scognet#define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_L_TEX(TEX_XSCALE_X)) 275129198Scognet 276129198Scognet#define L2_S_PROT_U_generic (L2_AP(AP_U)) 277129198Scognet#define L2_S_PROT_W_generic (L2_AP(AP_W)) 278129198Scognet#define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W) 279129198Scognet 280129198Scognet#define L2_S_PROT_U_xscale (L2_AP0(AP_U)) 281129198Scognet#define L2_S_PROT_W_xscale (L2_AP0(AP_W)) 282129198Scognet#define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W) 283129198Scognet 284129198Scognet#define L2_S_CACHE_MASK_generic (L2_B|L2_C) 285129198Scognet#define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_T_TEX(TEX_XSCALE_X)) 286129198Scognet 287129198Scognet#define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP) 288129198Scognet#define L1_S_PROTO_xscale (L1_TYPE_S) 289129198Scognet 290129198Scognet#define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2) 291129198Scognet#define L1_C_PROTO_xscale (L1_TYPE_C) 292129198Scognet 293129198Scognet#define L2_L_PROTO (L2_TYPE_L) 294129198Scognet 295129198Scognet#define L2_S_PROTO_generic (L2_TYPE_S) 296129198Scognet#define L2_S_PROTO_xscale (L2_TYPE_XSCALE_XS) 297129198Scognet 298129198Scognet/* 299129198Scognet * User-visible names for the ones that vary with MMU class. 300129198Scognet */ 301129198Scognet 302129198Scognet#if ARM_NMMUS > 1 303129198Scognet/* More than one MMU class configured; use variables. */ 304129198Scognet#define L2_S_PROT_U pte_l2_s_prot_u 305129198Scognet#define L2_S_PROT_W pte_l2_s_prot_w 306129198Scognet#define L2_S_PROT_MASK pte_l2_s_prot_mask 307129198Scognet 308129198Scognet#define L1_S_CACHE_MASK pte_l1_s_cache_mask 309129198Scognet#define L2_L_CACHE_MASK pte_l2_l_cache_mask 310129198Scognet#define L2_S_CACHE_MASK pte_l2_s_cache_mask 311129198Scognet 312129198Scognet#define L1_S_PROTO pte_l1_s_proto 313129198Scognet#define L1_C_PROTO pte_l1_c_proto 314129198Scognet#define L2_S_PROTO pte_l2_s_proto 315129198Scognet 316129198Scognet#elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 317129198Scognet#define L2_S_PROT_U L2_S_PROT_U_generic 318129198Scognet#define L2_S_PROT_W L2_S_PROT_W_generic 319129198Scognet#define L2_S_PROT_MASK L2_S_PROT_MASK_generic 320129198Scognet 321129198Scognet#define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 322129198Scognet#define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 323129198Scognet#define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 324129198Scognet 325129198Scognet#define L1_S_PROTO L1_S_PROTO_generic 326129198Scognet#define L1_C_PROTO L1_C_PROTO_generic 327129198Scognet#define L2_S_PROTO L2_S_PROTO_generic 328129198Scognet 329129198Scognet#elif ARM_MMU_XSCALE == 1 330129198Scognet#define L2_S_PROT_U L2_S_PROT_U_xscale 331129198Scognet#define L2_S_PROT_W L2_S_PROT_W_xscale 332129198Scognet#define L2_S_PROT_MASK L2_S_PROT_MASK_xscale 333129198Scognet 334129198Scognet#define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale 335129198Scognet#define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale 336129198Scognet#define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale 337129198Scognet 338129198Scognet#define L1_S_PROTO L1_S_PROTO_xscale 339129198Scognet#define L1_C_PROTO L1_C_PROTO_xscale 340129198Scognet#define L2_S_PROTO L2_S_PROTO_xscale 341129198Scognet 342129198Scognet#endif /* ARM_NMMUS > 1 */ 343129198Scognet 344158531Scognet#ifdef SKYEYE_WORKAROUNDS 345158531Scognet#define PMAP_NEEDS_PTE_SYNC 1 346158531Scognet#define PMAP_INCLUDE_PTE_SYNC 347158531Scognet#else 348129198Scognet#if (ARM_MMU_SA1 == 1) && (ARM_NMMUS == 1) 349129198Scognet#define PMAP_NEEDS_PTE_SYNC 1 350129198Scognet#define PMAP_INCLUDE_PTE_SYNC 351129198Scognet#elif (ARM_MMU_SA1 == 0) 352129198Scognet#define PMAP_NEEDS_PTE_SYNC 0 353129198Scognet#endif 354158531Scognet#endif 355129198Scognet 356129198Scognet/* 357129198Scognet * These macros return various bits based on kernel/user and protection. 358129198Scognet * Note that the compiler will usually fold these at compile time. 359129198Scognet */ 360129198Scognet#define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \ 361129198Scognet (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : 0)) 362129198Scognet 363129198Scognet#define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \ 364129198Scognet (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : 0)) 365129198Scognet 366129198Scognet#define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \ 367129198Scognet (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : 0)) 368129198Scognet 369129198Scognet/* 370129198Scognet * Macros to test if a mapping is mappable with an L1 Section mapping 371129198Scognet * or an L2 Large Page mapping. 372129198Scognet */ 373129198Scognet#define L1_S_MAPPABLE_P(va, pa, size) \ 374129198Scognet ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE) 375129198Scognet 376129198Scognet#define L2_L_MAPPABLE_P(va, pa, size) \ 377129198Scognet ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE) 378129198Scognet 379129198Scognet/* 380129198Scognet * Provide a fallback in case we were not able to determine it at 381129198Scognet * compile-time. 382129198Scognet */ 383129198Scognet#ifndef PMAP_NEEDS_PTE_SYNC 384129198Scognet#define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync 385129198Scognet#define PMAP_INCLUDE_PTE_SYNC 386129198Scognet#endif 387129198Scognet 388129198Scognet#define PTE_SYNC(pte) \ 389129198Scognetdo { \ 390129198Scognet if (PMAP_NEEDS_PTE_SYNC) \ 391129198Scognet cpu_dcache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\ 392129198Scognet} while (/*CONSTCOND*/0) 393129198Scognet 394129198Scognet#define PTE_SYNC_RANGE(pte, cnt) \ 395129198Scognetdo { \ 396129198Scognet if (PMAP_NEEDS_PTE_SYNC) { \ 397129198Scognet cpu_dcache_wb_range((vm_offset_t)(pte), \ 398129198Scognet (cnt) << 2); /* * sizeof(pt_entry_t) */ \ 399129198Scognet } \ 400129198Scognet} while (/*CONSTCOND*/0) 401129198Scognet 402129198Scognetextern pt_entry_t pte_l1_s_cache_mode; 403129198Scognetextern pt_entry_t pte_l1_s_cache_mask; 404129198Scognet 405129198Scognetextern pt_entry_t pte_l2_l_cache_mode; 406129198Scognetextern pt_entry_t pte_l2_l_cache_mask; 407129198Scognet 408129198Scognetextern pt_entry_t pte_l2_s_cache_mode; 409129198Scognetextern pt_entry_t pte_l2_s_cache_mask; 410129198Scognet 411129198Scognetextern pt_entry_t pte_l1_s_cache_mode_pt; 412129198Scognetextern pt_entry_t pte_l2_l_cache_mode_pt; 413129198Scognetextern pt_entry_t pte_l2_s_cache_mode_pt; 414129198Scognet 415129198Scognetextern pt_entry_t pte_l2_s_prot_u; 416129198Scognetextern pt_entry_t pte_l2_s_prot_w; 417129198Scognetextern pt_entry_t pte_l2_s_prot_mask; 418129198Scognet 419129198Scognetextern pt_entry_t pte_l1_s_proto; 420129198Scognetextern pt_entry_t pte_l1_c_proto; 421129198Scognetextern pt_entry_t pte_l2_s_proto; 422129198Scognet 423129198Scognetextern void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t); 424129198Scognetextern void (*pmap_zero_page_func)(vm_paddr_t, int, int); 425129198Scognet 426164080Scognet#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_81342) 427129198Scognetvoid pmap_copy_page_generic(vm_paddr_t, vm_paddr_t); 428129198Scognetvoid pmap_zero_page_generic(vm_paddr_t, int, int); 429129198Scognet 430129198Scognetvoid pmap_pte_init_generic(void); 431129198Scognet#if defined(CPU_ARM8) 432129198Scognetvoid pmap_pte_init_arm8(void); 433129198Scognet#endif 434129198Scognet#if defined(CPU_ARM9) 435129198Scognetvoid pmap_pte_init_arm9(void); 436129198Scognet#endif /* CPU_ARM9 */ 437129198Scognet#if defined(CPU_ARM10) 438129198Scognetvoid pmap_pte_init_arm10(void); 439129198Scognet#endif /* CPU_ARM10 */ 440129198Scognet#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 441129198Scognet 442129198Scognet#if /* ARM_MMU_SA1 == */1 443129198Scognetvoid pmap_pte_init_sa1(void); 444129198Scognet#endif /* ARM_MMU_SA1 == 1 */ 445129198Scognet 446129198Scognet#if ARM_MMU_XSCALE == 1 447129198Scognetvoid pmap_copy_page_xscale(vm_paddr_t, vm_paddr_t); 448129198Scognetvoid pmap_zero_page_xscale(vm_paddr_t, int, int); 449129198Scognet 450129198Scognetvoid pmap_pte_init_xscale(void); 451129198Scognet 452129198Scognetvoid xscale_setup_minidata(vm_offset_t, vm_offset_t, vm_offset_t); 453129198Scognet 454135641Scognetvoid pmap_use_minicache(vm_offset_t, vm_size_t); 455129198Scognet#endif /* ARM_MMU_XSCALE == 1 */ 456129198Scognet#define PTE_KERNEL 0 457129198Scognet#define PTE_USER 1 458129198Scognet#define l1pte_valid(pde) ((pde) != 0) 459129198Scognet#define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S) 460129198Scognet#define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C) 461129198Scognet#define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F) 462129198Scognet 463129198Scognet#define l2pte_index(v) (((v) & L2_ADDR_BITS) >> L2_S_SHIFT) 464129198Scognet#define l2pte_valid(pte) ((pte) != 0) 465129198Scognet#define l2pte_pa(pte) ((pte) & L2_S_FRAME) 466129198Scognet#define l2pte_minidata(pte) (((pte) & \ 467129198Scognet (L2_B | L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))\ 468129198Scognet == (L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X))) 469129198Scognet 470129198Scognet/* L1 and L2 page table macros */ 471129198Scognet#define pmap_pde_v(pde) l1pte_valid(*(pde)) 472129198Scognet#define pmap_pde_section(pde) l1pte_section_p(*(pde)) 473129198Scognet#define pmap_pde_page(pde) l1pte_page_p(*(pde)) 474129198Scognet#define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde)) 475129198Scognet 476129198Scognet#define pmap_pte_v(pte) l2pte_valid(*(pte)) 477129198Scognet#define pmap_pte_pa(pte) l2pte_pa(*(pte)) 478129198Scognet 479129198Scognet/* 480129198Scognet * Flags that indicate attributes of pages or mappings of pages. 481129198Scognet * 482129198Scognet * The PVF_MOD and PVF_REF flags are stored in the mdpage for each 483129198Scognet * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual 484129198Scognet * pv_entry's for each page. They live in the same "namespace" so 485129198Scognet * that we can clear multiple attributes at a time. 486129198Scognet * 487129198Scognet * Note the "non-cacheable" flag generally means the page has 488129198Scognet * multiple mappings in a given address space. 489129198Scognet */ 490129198Scognet#define PVF_MOD 0x01 /* page is modified */ 491129198Scognet#define PVF_REF 0x02 /* page is referenced */ 492129198Scognet#define PVF_WIRED 0x04 /* mapping is wired */ 493129198Scognet#define PVF_WRITE 0x08 /* mapping is writable */ 494129198Scognet#define PVF_EXEC 0x10 /* mapping is executable */ 495129198Scognet#define PVF_UNC 0x20 /* mapping is 'user' non-cacheable */ 496129198Scognet#define PVF_KNC 0x40 /* mapping is 'kernel' non-cacheable */ 497129198Scognet#define PVF_NC (PVF_UNC|PVF_KNC) 498129198Scognet 499129198Scognetvoid vector_page_setprot(int); 500135641Scognet 501135641Scognetvoid pmap_update(pmap_t); 502135641Scognet 503129198Scognet/* 504135641Scognet * This structure is used by machine-dependent code to describe 505135641Scognet * static mappings of devices, created at bootstrap time. 506129198Scognet */ 507135641Scognetstruct pmap_devmap { 508135641Scognet vm_offset_t pd_va; /* virtual address */ 509135641Scognet vm_paddr_t pd_pa; /* physical address */ 510135641Scognet vm_size_t pd_size; /* size of region */ 511135641Scognet vm_prot_t pd_prot; /* protection code */ 512135641Scognet int pd_cache; /* cache attributes */ 513135641Scognet}; 514129198Scognet 515135641Scognetconst struct pmap_devmap *pmap_devmap_find_pa(vm_paddr_t, vm_size_t); 516135641Scognetconst struct pmap_devmap *pmap_devmap_find_va(vm_offset_t, vm_size_t); 517129198Scognet 518135641Scognetvoid pmap_devmap_bootstrap(vm_offset_t, const struct pmap_devmap *); 519135641Scognetvoid pmap_devmap_register(const struct pmap_devmap *); 520137362Scognet 521147114Scognet#define SECTION_CACHE 0x1 522147114Scognet#define SECTION_PT 0x2 523147114Scognetvoid pmap_kenter_section(vm_offset_t, vm_paddr_t, int flags); 524147114Scognet 525137362Scognetextern char *_tmppt; 526137362Scognet 527152128Scognetvoid pmap_postinit(void); 528152128Scognet 529147114Scognet#ifdef ARM_USE_SMALL_ALLOC 530147114Scognetvoid arm_add_smallalloc_pages(void *, void *, int, int); 531161105Scognetvm_offset_t arm_ptovirt(vm_paddr_t); 532161105Scognetvoid arm_init_smallalloc(void); 533147114Scognetstruct arm_small_page { 534147114Scognet void *addr; 535147114Scognet TAILQ_ENTRY(arm_small_page) pg_list; 536147114Scognet}; 537150867Scognet 538150936Scognet#endif 539156191Scognet 540166063Scognet#define ARM_NOCACHE_KVA_SIZE 0x1000000 541156191Scognetextern vm_offset_t arm_nocache_startaddr; 542156191Scognetvoid *arm_remap_nocache(void *, vm_size_t); 543156191Scognetvoid arm_unmap_nocache(void *, vm_size_t); 544156191Scognet 545150867Scognetextern vm_paddr_t dump_avail[]; 546129198Scognet#endif /* _KERNEL */ 547129198Scognet 548129198Scognet#endif /* !LOCORE */ 549129198Scognet 550129198Scognet#endif /* !_MACHINE_PMAP_H_ */ 551