intr.h revision 289529
1/* $NetBSD: intr.h,v 1.7 2003/06/16 20:01:00 thorpej Exp $ */ 2 3/*- 4 * Copyright (c) 1997 Mark Brinicombe. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Mark Brinicombe 18 * for the NetBSD Project. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * $FreeBSD: head/sys/arm/include/intr.h 289529 2015-10-18 18:26:19Z ian $ 36 * 37 */ 38 39#ifndef _MACHINE_INTR_H_ 40#define _MACHINE_INTR_H_ 41 42#ifdef FDT 43#include <dev/ofw/openfirm.h> 44#endif 45 46#ifdef ARM_INTRNG 47 48#ifndef NIRQ 49#define NIRQ 1024 /* XXX - It should be an option. */ 50#endif 51 52#ifdef notyet 53#define INTR_SOLO INTR_MD1 54typedef int arm_irq_filter_t(void *arg, struct trapframe *tf); 55#else 56typedef int arm_irq_filter_t(void *arg); 57#endif 58 59#define ARM_ISRC_NAMELEN (MAXCOMLEN + 1) 60 61typedef void arm_ipi_filter_t(void *arg); 62 63enum arm_isrc_type { 64 ARM_ISRCT_NAMESPACE, 65 ARM_ISRCT_FDT 66}; 67 68#define ARM_ISRCF_REGISTERED 0x01 /* registered in a controller */ 69#define ARM_ISRCF_PERCPU 0x02 /* per CPU interrupt */ 70#define ARM_ISRCF_BOUND 0x04 /* bound to a CPU */ 71 72/* Interrupt source definition. */ 73struct arm_irqsrc { 74 device_t isrc_dev; /* where isrc is mapped */ 75 intptr_t isrc_xref; /* device reference key */ 76 uintptr_t isrc_data; /* device data for isrc */ 77 u_int isrc_irq; /* unique identificator */ 78 enum arm_isrc_type isrc_type; /* how is isrc decribed */ 79 u_int isrc_flags; 80 char isrc_name[ARM_ISRC_NAMELEN]; 81 uint16_t isrc_nspc_type; 82 uint16_t isrc_nspc_num; 83 enum intr_trigger isrc_trig; 84 enum intr_polarity isrc_pol; 85 cpuset_t isrc_cpu; /* on which CPUs is enabled */ 86 u_int isrc_index; 87 u_long * isrc_count; 88 u_int isrc_handlers; 89 struct intr_event * isrc_event; 90 arm_irq_filter_t * isrc_filter; 91 arm_ipi_filter_t * isrc_ipifilter; 92 void * isrc_arg; 93#ifdef FDT 94 u_int isrc_ncells; 95 pcell_t isrc_cells[]; /* leave it last */ 96#endif 97}; 98 99void arm_irq_set_name(struct arm_irqsrc *isrc, const char *fmt, ...) 100 __printflike(2, 3); 101 102void arm_irq_dispatch(struct arm_irqsrc *isrc, struct trapframe *tf); 103 104#define ARM_IRQ_NSPC_NONE 0 105#define ARM_IRQ_NSPC_PLAIN 1 106#define ARM_IRQ_NSPC_IRQ 2 107#define ARM_IRQ_NSPC_IPI 3 108 109u_int arm_namespace_map_irq(device_t dev, uint16_t type, uint16_t num); 110#ifdef FDT 111u_int arm_fdt_map_irq(phandle_t, pcell_t *, u_int); 112#endif 113 114int arm_pic_register(device_t dev, intptr_t xref); 115int arm_pic_unregister(device_t dev, intptr_t xref); 116int arm_pic_claim_root(device_t dev, intptr_t xref, arm_irq_filter_t *filter, 117 void *arg, u_int ipicount); 118 119int arm_irq_add_handler(device_t dev, driver_filter_t, driver_intr_t, void *, 120 u_int, int, void **); 121int arm_irq_remove_handler(device_t dev, u_int, void *); 122int arm_irq_config(u_int, enum intr_trigger, enum intr_polarity); 123int arm_irq_describe(u_int, void *, const char *); 124 125u_int arm_irq_next_cpu(u_int current_cpu, cpuset_t *cpumask); 126 127#ifdef SMP 128int arm_irq_bind(u_int, int); 129 130void arm_ipi_dispatch(struct arm_irqsrc *isrc, struct trapframe *tf); 131 132#define AISHF_NOALLOC 0x0001 133 134int arm_ipi_set_handler(u_int ipi, const char *name, arm_ipi_filter_t *filter, 135 void *arg, u_int flags); 136 137void arm_pic_init_secondary(void); 138#endif 139 140#else /* ARM_INTRNG */ 141 142/* XXX move to std.* files? */ 143#ifdef CPU_XSCALE_81342 144#define NIRQ 128 145#elif defined(CPU_XSCALE_PXA2X0) 146#include <arm/xscale/pxa/pxareg.h> 147#define NIRQ IRQ_GPIO_MAX 148#elif defined(SOC_MV_DISCOVERY) 149#define NIRQ 96 150#elif defined(CPU_ARM9) || defined(SOC_MV_KIRKWOOD) || \ 151 defined(CPU_XSCALE_IXP435) 152#define NIRQ 64 153#elif defined(CPU_CORTEXA) 154#define NIRQ 1020 155#elif defined(CPU_KRAIT) 156#define NIRQ 288 157#elif defined(CPU_ARM1176) 158#define NIRQ 128 159#elif defined(SOC_MV_ARMADAXP) 160#define MAIN_IRQ_NUM 116 161#define ERR_IRQ_NUM 32 162#define ERR_IRQ (MAIN_IRQ_NUM) 163#define MSI_IRQ_NUM 32 164#define MSI_IRQ (ERR_IRQ + ERR_IRQ_NUM) 165#define NIRQ (MAIN_IRQ_NUM + ERR_IRQ_NUM + MSI_IRQ_NUM) 166#else 167#define NIRQ 32 168#endif 169 170int arm_get_next_irq(int); 171void arm_mask_irq(uintptr_t); 172void arm_unmask_irq(uintptr_t); 173void arm_intrnames_init(void); 174void arm_setup_irqhandler(const char *, int (*)(void*), void (*)(void*), 175 void *, int, int, void **); 176int arm_remove_irqhandler(int, void *); 177extern void (*arm_post_filter)(void *); 178extern int (*arm_config_irq)(int irq, enum intr_trigger trig, 179 enum intr_polarity pol); 180 181void arm_pic_init_secondary(void); 182int gic_decode_fdt(uint32_t iparentnode, uint32_t *intrcells, int *interrupt, 183 int *trig, int *pol); 184 185#ifdef FDT 186int arm_fdt_map_irq(phandle_t, pcell_t *, int); 187#endif 188 189#endif /* ARM_INTRNG */ 190 191void arm_irq_memory_barrier(uintptr_t); 192 193#endif /* _MACHINE_INTR_H */ 194