armreg.h revision 278518
1228690Sdes/* $NetBSD: armreg.h,v 1.37 2007/01/06 00:50:54 christos Exp $ */ 2228690Sdes 3228690Sdes/*- 4228690Sdes * Copyright (c) 1998, 2001 Ben Harris 5228690Sdes * Copyright (c) 1994-1996 Mark Brinicombe. 6228690Sdes * Copyright (c) 1994 Brini. 7228690Sdes * All rights reserved. 8228690Sdes * 9255376Sdes * This code is derived from software written for Brini by Mark Brinicombe 10228690Sdes * 11228690Sdes * Redistribution and use in source and binary forms, with or without 12228690Sdes * modification, are permitted provided that the following conditions 13236109Sdes * are met: 14236109Sdes * 1. Redistributions of source code must retain the above copyright 15236109Sdes * notice, this list of conditions and the following disclaimer. 16228690Sdes * 2. Redistributions in binary form must reproduce the above copyright 17228690Sdes * notice, this list of conditions and the following disclaimer in the 18228690Sdes * documentation and/or other materials provided with the distribution. 19228690Sdes * 3. All advertising materials mentioning features or use of this software 20228690Sdes * must display the following acknowledgement: 21228690Sdes * This product includes software developed by Brini. 22228690Sdes * 4. The name of the company nor the name of the author may be used to 23228690Sdes * endorse or promote products derived from this software without specific 24228690Sdes * prior written permission. 25228690Sdes * 26228690Sdes * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 27228690Sdes * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28228690Sdes * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29255376Sdes * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30228690Sdes * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31228690Sdes * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32228690Sdes * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33228690Sdes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34228690Sdes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35228690Sdes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36228690Sdes * SUCH DAMAGE. 37255376Sdes * 38228690Sdes * $FreeBSD: head/sys/arm/include/armreg.h 278518 2015-02-10 14:11:23Z zbb $ 39228690Sdes */ 40228690Sdes 41228690Sdes#ifndef MACHINE_ARMREG_H 42228690Sdes#define MACHINE_ARMREG_H 43228690Sdes 44228690Sdes#include <machine/acle-compat.h> 45228690Sdes 46228690Sdes#define INSN_SIZE 4 47228690Sdes#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 48228690Sdes#define PSR_MODE 0x0000001f /* mode mask */ 49228690Sdes#define PSR_USR32_MODE 0x00000010 50228690Sdes#define PSR_FIQ32_MODE 0x00000011 51228690Sdes#define PSR_IRQ32_MODE 0x00000012 52228690Sdes#define PSR_SVC32_MODE 0x00000013 53228690Sdes#define PSR_MON32_MODE 0x00000016 54228690Sdes#define PSR_ABT32_MODE 0x00000017 55228690Sdes#define PSR_HYP32_MODE 0x0000001a 56228690Sdes#define PSR_UND32_MODE 0x0000001b 57228690Sdes#define PSR_SYS32_MODE 0x0000001f 58228690Sdes#define PSR_32_MODE 0x00000010 59228690Sdes#define PSR_T 0x00000020 /* Instruction set bit */ 60228690Sdes#define PSR_F 0x00000040 /* FIQ disable bit */ 61228690Sdes#define PSR_I 0x00000080 /* IRQ disable bit */ 62228690Sdes#define PSR_A 0x00000100 /* Imprecise abort bit */ 63228690Sdes#define PSR_E 0x00000200 /* Data endianess bit */ 64228690Sdes#define PSR_GE 0x000f0000 /* Greater than or equal to bits */ 65228690Sdes#define PSR_J 0x01000000 /* Java bit */ 66228690Sdes#define PSR_Q 0x08000000 /* Sticky overflow bit */ 67228690Sdes#define PSR_V 0x10000000 /* Overflow bit */ 68228690Sdes#define PSR_C 0x20000000 /* Carry bit */ 69228690Sdes#define PSR_Z 0x40000000 /* Zero bit */ 70228690Sdes#define PSR_N 0x80000000 /* Negative bit */ 71228690Sdes#define PSR_FLAGS 0xf0000000 /* Flags mask. */ 72228690Sdes 73228690Sdes/* The high-order byte is always the implementor */ 74228690Sdes#define CPU_ID_IMPLEMENTOR_MASK 0xff000000 75228690Sdes#define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ 76228690Sdes#define CPU_ID_DEC 0x44000000 /* 'D' */ 77228690Sdes#define CPU_ID_INTEL 0x69000000 /* 'i' */ 78228690Sdes#define CPU_ID_TI 0x54000000 /* 'T' */ 79228690Sdes#define CPU_ID_FARADAY 0x66000000 /* 'f' */ 80228690Sdes 81228690Sdes/* How to decide what format the CPUID is in. */ 82228690Sdes#define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) 83228690Sdes#define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) 84228690Sdes#define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) 85228690Sdes 86228690Sdes/* On recent ARMs this byte holds the architecture and variant (sub-model) */ 87228690Sdes#define CPU_ID_ARCH_MASK 0x000f0000 88228690Sdes#define CPU_ID_ARCH_V3 0x00000000 89228690Sdes#define CPU_ID_ARCH_V4 0x00010000 90228690Sdes#define CPU_ID_ARCH_V4T 0x00020000 91228690Sdes#define CPU_ID_ARCH_V5 0x00030000 92228690Sdes#define CPU_ID_ARCH_V5T 0x00040000 93228690Sdes#define CPU_ID_ARCH_V5TE 0x00050000 94228690Sdes#define CPU_ID_ARCH_V5TEJ 0x00060000 95228690Sdes#define CPU_ID_ARCH_V6 0x00070000 96228690Sdes#define CPU_ID_CPUID_SCHEME 0x000f0000 97228690Sdes#define CPU_ID_VARIANT_MASK 0x00f00000 98228690Sdes 99228690Sdes/* Next three nybbles are part number */ 100228690Sdes#define CPU_ID_PARTNO_MASK 0x0000fff0 101228690Sdes 102228690Sdes/* Intel XScale has sub fields in part number */ 103228690Sdes#define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ 104228690Sdes#define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ 105228690Sdes#define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ 106228690Sdes 107228690Sdes/* And finally, the revision number. */ 108228690Sdes#define CPU_ID_REVISION_MASK 0x0000000f 109228690Sdes 110228690Sdes/* Individual CPUs are probably best IDed by everything but the revision. */ 111228690Sdes#define CPU_ID_CPU_MASK 0xfffffff0 112228690Sdes 113228690Sdes/* ARM9 and later CPUs */ 114228690Sdes#define CPU_ID_ARM920T 0x41129200 115228690Sdes#define CPU_ID_ARM920T_ALT 0x41009200 116228690Sdes#define CPU_ID_ARM922T 0x41029220 117228690Sdes#define CPU_ID_ARM926EJS 0x41069260 118228690Sdes#define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ 119255376Sdes#define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ 120228690Sdes#define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ 121228690Sdes#define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ 122228690Sdes#define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ 123228690Sdes#define CPU_ID_ARM1022ES 0x4105a220 124228690Sdes#define CPU_ID_ARM1026EJS 0x4106a260 125228690Sdes#define CPU_ID_ARM1136JS 0x4107b360 126228690Sdes#define CPU_ID_ARM1136JSR1 0x4117b360 127228690Sdes#define CPU_ID_ARM1176JZS 0x410fb760 128228690Sdes#define CPU_ID_CORTEXA5 0x410fc050 129228690Sdes#define CPU_ID_CORTEXA7 0x410fc070 130228690Sdes#define CPU_ID_CORTEXA8R1 0x411fc080 131228690Sdes#define CPU_ID_CORTEXA8R2 0x412fc080 132228690Sdes#define CPU_ID_CORTEXA8R3 0x413fc080 133228690Sdes#define CPU_ID_CORTEXA9R1 0x411fc090 134255376Sdes#define CPU_ID_CORTEXA9R2 0x412fc090 135228690Sdes#define CPU_ID_CORTEXA9R3 0x413fc090 136228690Sdes#define CPU_ID_CORTEXA12R0 0x410fc0d0 137228690Sdes#define CPU_ID_CORTEXA15R0 0x410fc0f0 138228690Sdes#define CPU_ID_CORTEXA15R1 0x411fc0f0 139228690Sdes#define CPU_ID_CORTEXA15R2 0x412fc0f0 140228690Sdes#define CPU_ID_CORTEXA15R3 0x413fc0f0 141228690Sdes#define CPU_ID_KRAIT 0x510f06f0 /* Snapdragon S4 Pro/APQ8064 */ 142228690Sdes#define CPU_ID_TI925T 0x54029250 143228690Sdes#define CPU_ID_MV88FR131 0x56251310 /* Marvell Feroceon 88FR131 Core */ 144228690Sdes#define CPU_ID_MV88FR331 0x56153310 /* Marvell Feroceon 88FR331 Core */ 145228690Sdes#define CPU_ID_MV88FR571_VD 0x56155710 /* Marvell Feroceon 88FR571-VD Core (ID from datasheet) */ 146228690Sdes 147228690Sdes/* 148228690Sdes * LokiPlus core has also ID set to 0x41159260 and this define cause execution of unsupported 149255376Sdes * L2-cache instructions so need to disable it. 0x41159260 is a generic ARM926E-S ID. 150228690Sdes */ 151228690Sdes#ifdef SOC_MV_LOKIPLUS 152228690Sdes#define CPU_ID_MV88FR571_41 0x00000000 153228690Sdes#else 154228690Sdes#define CPU_ID_MV88FR571_41 0x41159260 /* Marvell Feroceon 88FR571-VD Core (actual ID from CPU reg) */ 155228690Sdes#endif 156228690Sdes 157228690Sdes#define CPU_ID_MV88SV581X_V7 0x561F5810 /* Marvell Sheeva 88SV581x v7 Core */ 158228690Sdes#define CPU_ID_MV88SV584X_V7 0x562F5840 /* Marvell Sheeva 88SV584x v7 Core */ 159228690Sdes/* Marvell's CPUIDs with ARM ID in implementor field */ 160228690Sdes#define CPU_ID_ARM_88SV581X_V7 0x413FC080 /* Marvell Sheeva 88SV581x v7 Core */ 161228690Sdes 162228690Sdes#define CPU_ID_FA526 0x66015260 163228690Sdes#define CPU_ID_FA626TE 0x66056260 164255376Sdes#define CPU_ID_80200 0x69052000 165228690Sdes#define CPU_ID_PXA250 0x69052100 /* sans core revision */ 166228690Sdes#define CPU_ID_PXA210 0x69052120 167228690Sdes#define CPU_ID_PXA250A 0x69052100 /* 1st version Core */ 168228690Sdes#define CPU_ID_PXA210A 0x69052120 /* 1st version Core */ 169228690Sdes#define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ 170228690Sdes#define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ 171228690Sdes#define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ 172228690Sdes#define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ 173228690Sdes#define CPU_ID_PXA27X 0x69054110 174228690Sdes#define CPU_ID_80321_400 0x69052420 175228690Sdes#define CPU_ID_80321_600 0x69052430 176228690Sdes#define CPU_ID_80321_400_B0 0x69052c20 177228690Sdes#define CPU_ID_80321_600_B0 0x69052c30 178228690Sdes#define CPU_ID_80219_400 0x69052e20 /* A0 stepping/revision. */ 179255376Sdes#define CPU_ID_80219_600 0x69052e30 /* A0 stepping/revision. */ 180228690Sdes#define CPU_ID_81342 0x69056810 181228690Sdes#define CPU_ID_IXP425 0x690541c0 182228690Sdes#define CPU_ID_IXP425_533 0x690541c0 183228690Sdes#define CPU_ID_IXP425_400 0x690541d0 184228690Sdes#define CPU_ID_IXP425_266 0x690541f0 185228690Sdes#define CPU_ID_IXP435 0x69054040 186228690Sdes#define CPU_ID_IXP465 0x69054200 187228690Sdes 188228690Sdes/* CPUID registers */ 189228690Sdes#define ARM_PFR0_ARM_ISA_MASK 0x0000000f 190228690Sdes 191228690Sdes#define ARM_PFR0_THUMB_MASK 0x000000f0 192228690Sdes#define ARM_PFR0_THUMB 0x10 193228690Sdes#define ARM_PFR0_THUMB2 0x30 194255376Sdes 195228690Sdes#define ARM_PFR0_JAZELLE_MASK 0x00000f00 196228690Sdes#define ARM_PFR0_THUMBEE_MASK 0x0000f000 197228690Sdes 198228690Sdes#define ARM_PFR1_ARMV4_MASK 0x0000000f 199228690Sdes#define ARM_PFR1_SEC_EXT_MASK 0x000000f0 200228690Sdes#define ARM_PFR1_MICROCTRL_MASK 0x00000f00 201228690Sdes 202228690Sdes/* 203228690Sdes * Post-ARM3 CP15 registers: 204228690Sdes * 205228690Sdes * 1 Control register 206228690Sdes * 207228690Sdes * 2 Translation Table Base 208228690Sdes * 209228690Sdes * 3 Domain Access Control 210228690Sdes * 211228690Sdes * 4 Reserved 212228690Sdes * 213228690Sdes * 5 Fault Status 214228690Sdes * 215228690Sdes * 6 Fault Address 216228690Sdes * 217228690Sdes * 7 Cache/write-buffer Control 218228690Sdes * 219228690Sdes * 8 TLB Control 220228690Sdes * 221228690Sdes * 9 Cache Lockdown 222228690Sdes * 223228690Sdes * 10 TLB Lockdown 224228690Sdes * 225228690Sdes * 11 Reserved 226228690Sdes * 227228690Sdes * 12 Reserved 228228690Sdes * 229228690Sdes * 13 Process ID (for FCSE) 230228690Sdes * 231228690Sdes * 14 Reserved 232228690Sdes * 233228690Sdes * 15 Implementation Dependent 234228690Sdes */ 235228690Sdes 236228690Sdes/* Some of the definitions below need cleaning up for V3/V4 architectures */ 237228690Sdes 238228690Sdes/* CPU control register (CP15 register 1) */ 239228690Sdes#define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ 240228690Sdes#define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ 241228690Sdes#define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ 242228690Sdes#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ 243228690Sdes#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ 244228690Sdes#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ 245228690Sdes#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ 246228690Sdes#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ 247228690Sdes#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ 248228690Sdes#define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ 249228690Sdes#define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ 250228690Sdes#define CPU_CONTROL_SW_ENABLE 0x00000400 /* SW: SWP instruction enable */ 251228690Sdes#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ 252228690Sdes#define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ 253228690Sdes#define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ 254228690Sdes#define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ 255228690Sdes#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ 256228690Sdes#define CPU_CONTROL_HAF_ENABLE 0x00020000 /* HA: Hardware Access Flag Enable */ 257228690Sdes#define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */ 258228690Sdes#define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */ 259228690Sdes#define CPU_CONTROL_V6_EXTPAGE 0x00800000 /* XP: ARMv6 extended page tables */ 260228690Sdes#define CPU_CONTROL_V_ENABLE 0x01000000 /* VE: Interrupt vectors enable */ 261228690Sdes#define CPU_CONTROL_EX_BEND 0x02000000 /* EE: exception endianness */ 262228690Sdes#define CPU_CONTROL_L2_ENABLE 0x04000000 /* L2 Cache enabled */ 263228690Sdes#define CPU_CONTROL_NMFI 0x08000000 /* NMFI: Non maskable FIQ */ 264228690Sdes#define CPU_CONTROL_TR_ENABLE 0x10000000 /* TRE: TEX Remap*/ 265228690Sdes#define CPU_CONTROL_AF_ENABLE 0x20000000 /* AFE: Access Flag enable */ 266228690Sdes#define CPU_CONTROL_TE_ENABLE 0x40000000 /* TE: Thumb Exception enable */ 267228690Sdes 268228690Sdes#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE 269228690Sdes 270228690Sdes/* ARM11x6 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 271228690Sdes#define ARM11X6_AUXCTL_RS 0x00000001 /* return stack */ 272228690Sdes#define ARM11X6_AUXCTL_DB 0x00000002 /* dynamic branch prediction */ 273236109Sdes#define ARM11X6_AUXCTL_SB 0x00000004 /* static branch prediction */ 274236109Sdes#define ARM11X6_AUXCTL_TR 0x00000008 /* MicroTLB replacement strat. */ 275228690Sdes#define ARM11X6_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */ 276228690Sdes#define ARM11X6_AUXCTL_RA 0x00000020 /* clean entire cache disable */ 277228690Sdes#define ARM11X6_AUXCTL_RV 0x00000040 /* block transfer cache disable */ 278228690Sdes#define ARM11X6_AUXCTL_CZ 0x00000080 /* restrict cache size */ 279255376Sdes 280255376Sdes/* ARM1136 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 281255376Sdes#define ARM1136_AUXCTL_PFI 0x80000000 /* PFI: partial FI mode. */ 282255376Sdes /* This is an undocumented flag 283255376Sdes * used to work around a cache bug 284255376Sdes * in r0 steppings. See errata 285255376Sdes * 364296. 286255376Sdes */ 287255376Sdes/* ARM1176 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 288255376Sdes#define ARM1176_AUXCTL_PHD 0x10000000 /* inst. prefetch halting disable */ 289255376Sdes#define ARM1176_AUXCTL_BFD 0x20000000 /* branch folding disable */ 290255376Sdes#define ARM1176_AUXCTL_FSD 0x40000000 /* force speculative ops disable */ 291255376Sdes#define ARM1176_AUXCTL_FIO 0x80000000 /* low intr latency override */ 292255376Sdes 293255376Sdes/* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */ 294255376Sdes#define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */ 295255376Sdes#define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */ 296255376Sdes/* Note: XSCale core 3 uses those for LLR DCcahce attributes */ 297228690Sdes#define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */ 298228690Sdes#define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */ 299228690Sdes#define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */ 300228690Sdes#define XSCALE_AUXCTL_MD_MASK 0x00000030 301228690Sdes 302228690Sdes/* Xscale Core 3 only */ 303228690Sdes#define XSCALE_AUXCTL_LLR 0x00000400 /* Enable L2 for LLR Cache */ 304228690Sdes 305228690Sdes/* Marvell Extra Features Register (CP15 register 1, opcode2 0) */ 306228690Sdes#define MV_DC_REPLACE_LOCK 0x80000000 /* Replace DCache Lock */ 307228690Sdes#define MV_DC_STREAM_ENABLE 0x20000000 /* DCache Streaming Switch */ 308228690Sdes#define MV_WA_ENABLE 0x10000000 /* Enable Write Allocate */ 309228690Sdes#define MV_L2_PREFETCH_DISABLE 0x01000000 /* L2 Cache Prefetch Disable */ 310228690Sdes#define MV_L2_INV_EVICT_ERR 0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */ 311228690Sdes#define MV_L2_ENABLE 0x00400000 /* L2 Cache enable */ 312228690Sdes#define MV_IC_REPLACE_LOCK 0x00080000 /* Replace ICache Lock */ 313228690Sdes#define MV_BGH_ENABLE 0x00040000 /* Branch Global History Register Enable */ 314228690Sdes#define MV_BTB_DISABLE 0x00020000 /* Branch Target Buffer Disable */ 315228690Sdes#define MV_L1_PARERR_ENABLE 0x00010000 /* L1 Parity Error Enable */ 316228690Sdes 317228690Sdes/* Cache type register definitions */ 318228690Sdes#define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ 319228690Sdes#define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ 320228690Sdes#define CPU_CT_S (1U << 24) /* split cache */ 321228690Sdes#define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ 322228690Sdes#define CPU_CT_FORMAT(x) ((x) >> 29) 323255376Sdes/* Cache type register definitions for ARM v7 */ 324228690Sdes#define CPU_CT_IMINLINE(x) ((x) & 0xf) /* I$ min line size */ 325228690Sdes#define CPU_CT_DMINLINE(x) (((x) >> 16) & 0xf) /* D$ min line size */ 326228690Sdes 327228690Sdes#define CPU_CT_CTYPE_WT 0 /* write-through */ 328255376Sdes#define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ 329228690Sdes#define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ 330228690Sdes#define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ 331228690Sdes#define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ 332228690Sdes 333228690Sdes#define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ 334228690Sdes#define CPU_CT_xSIZE_M (1U << 2) /* multiplier */ 335228690Sdes#define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ 336228690Sdes#define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ 337228690Sdes 338228690Sdes#define CPU_CT_ARMV7 0x4 339228690Sdes/* ARM v7 Cache type definitions */ 340228690Sdes#define CPUV7_CT_CTYPE_WT (1U << 31) 341228690Sdes#define CPUV7_CT_CTYPE_WB (1 << 30) 342236109Sdes#define CPUV7_CT_CTYPE_RA (1 << 29) 343236109Sdes#define CPUV7_CT_CTYPE_WA (1 << 28) 344236109Sdes 345236109Sdes#define CPUV7_CT_xSIZE_LEN(x) ((x) & 0x7) /* line size */ 346236109Sdes#define CPUV7_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x3ff) /* associativity */ 347236109Sdes#define CPUV7_CT_xSIZE_SET(x) (((x) >> 13) & 0x7fff) /* num sets */ 348236109Sdes 349236109Sdes#define CPU_CLIDR_CTYPE(reg,x) (((reg) >> ((x) * 3)) & 0x7) 350228690Sdes#define CPU_CLIDR_LOUIS(reg) (((reg) >> 21) & 0x7) 351228690Sdes#define CPU_CLIDR_LOC(reg) (((reg) >> 24) & 0x7) 352228690Sdes#define CPU_CLIDR_LOUU(reg) (((reg) >> 27) & 0x7) 353255376Sdes 354255376Sdes#define CACHE_ICACHE 1 355255376Sdes#define CACHE_DCACHE 2 356255376Sdes#define CACHE_SEP_CACHE 3 357255376Sdes#define CACHE_UNI_CACHE 4 358255376Sdes 359255376Sdes/* Fault status register definitions */ 360255376Sdes#define FAULT_USER 0x10 361255376Sdes 362228690Sdes#if __ARM_ARCH < 6 363228690Sdes#define FAULT_TYPE_MASK 0x0f 364228690Sdes#define FAULT_WRTBUF_0 0x00 /* Vector Exception */ 365228690Sdes#define FAULT_WRTBUF_1 0x02 /* Terminal Exception */ 366228690Sdes#define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */ 367228690Sdes#define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */ 368228690Sdes#define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */ 369228690Sdes#define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */ 370228690Sdes#define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */ 371228690Sdes#define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */ 372228690Sdes#define FAULT_ALIGN_0 0x01 /* Alignment */ 373228690Sdes#define FAULT_ALIGN_1 0x03 /* Alignment */ 374228690Sdes#define FAULT_TRANS_S 0x05 /* Translation -- Section */ 375228690Sdes#define FAULT_TRANS_F 0x06 /* Translation -- Flag */ 376228690Sdes#define FAULT_TRANS_P 0x07 /* Translation -- Page */ 377228690Sdes#define FAULT_DOMAIN_S 0x09 /* Domain -- Section */ 378228690Sdes#define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ 379228690Sdes#define FAULT_PERM_S 0x0d /* Permission -- Section */ 380228690Sdes#define FAULT_PERM_P 0x0f /* Permission -- Page */ 381228690Sdes 382228690Sdes#define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */ 383228690Sdes#define FAULT_EXTERNAL 0x400 /* External abort (armv6+) */ 384228690Sdes#define FAULT_WNR 0x800 /* Write-not-Read access (armv6+) */ 385228690Sdes 386228690Sdes#else /* __ARM_ARCH < 6 */ 387228690Sdes 388228690Sdes#define FAULT_ALIGN 0x001 /* Alignment Fault */ 389255376Sdes#define FAULT_DEBUG 0x002 /* Debug Event */ 390255376Sdes#define FAULT_ACCESS_L1 0x003 /* Access Bit (L1) */ 391228690Sdes#define FAULT_ICACHE 0x004 /* Instruction cache maintenance */ 392228690Sdes#define FAULT_TRAN_L1 0x005 /* Translation Fault (L1) */ 393228690Sdes#define FAULT_ACCESS_L2 0x006 /* Access Bit (L2) */ 394228690Sdes#define FAULT_TRAN_L2 0x007 /* Translation Fault (L2) */ 395228690Sdes#define FAULT_EA_PREC 0x008 /* External Abort */ 396228690Sdes#define FAULT_DOMAIN_L1 0x009 /* Domain Fault (L1) */ 397228690Sdes#define FAULT_DOMAIN_L2 0x00B /* Domain Fault (L2) */ 398228690Sdes#define FAULT_EA_TRAN_L1 0x00C /* External Translation Abort (L1) */ 399228690Sdes#define FAULT_PERM_L1 0x00D /* Permission Fault (L1) */ 400228690Sdes#define FAULT_EA_TRAN_L2 0x00E /* External Translation Abort (L2) */ 401228690Sdes#define FAULT_PERM_L2 0x00F /* Permission Fault (L2) */ 402228690Sdes#define FAULT_TLB_CONFLICT 0x010 /* Permission Fault (L2) */ 403228690Sdes#define FAULT_EA_IMPREC 0x016 /* Asynchronous External Abort */ 404228690Sdes#define FAULT_PE_IMPREC 0x018 /* Asynchronous Parity Error */ 405228690Sdes#define FAULT_PARITY 0x019 /* Parity Error */ 406228690Sdes#define FAULT_PE_TRAN_L1 0x01C /* Parity Error on Translation (L1) */ 407228690Sdes#define FAULT_PE_TRAN_L2 0x01E /* Parity Error on Translation (L2) */ 408228690Sdes 409228690Sdes#define FSR_TO_FAULT(fsr) (((fsr) & 0xF) | \ 410228690Sdes ((((fsr) & (1 << 10)) >> (10 - 4)))) 411228690Sdes#define FSR_LPAE (1 << 9) /* LPAE indicator */ 412228690Sdes#define FSR_WNR (1 << 11) /* Write-not-Read access */ 413228690Sdes#define FSR_EXT (1 << 12) /* DECERR/SLVERR for external*/ 414228690Sdes#define FSR_CM (1 << 13) /* Cache maintenance fault */ 415228690Sdes#endif /* !__ARM_ARCH < 6 */ 416228690Sdes 417228690Sdes/* 418228690Sdes * Address of the vector page, low and high versions. 419228690Sdes */ 420228690Sdes#ifndef __ASSEMBLER__ 421228690Sdes#define ARM_VECTORS_LOW 0x00000000U 422228690Sdes#define ARM_VECTORS_HIGH 0xffff0000U 423228690Sdes#else 424228690Sdes#define ARM_VECTORS_LOW 0 425228690Sdes#define ARM_VECTORS_HIGH 0xffff0000 426228690Sdes#endif 427228690Sdes 428228690Sdes/* 429228690Sdes * ARM Instructions 430228690Sdes * 431228690Sdes * 3 3 2 2 2 432228690Sdes * 1 0 9 8 7 0 433228690Sdes * +-------+-------------------------------------------------------+ 434228690Sdes * | cond | instruction dependant | 435228690Sdes * |c c c c| | 436228690Sdes * +-------+-------------------------------------------------------+ 437228690Sdes */ 438228690Sdes 439228690Sdes#define INSN_SIZE 4 /* Always 4 bytes */ 440228690Sdes#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 441228690Sdes#define INSN_COND_AL 0xe0000000 /* Always condition */ 442228690Sdes 443228690Sdes#define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */ 444228690Sdes 445228690Sdes#endif /* !MACHINE_ARMREG_H */ 446228690Sdes