armreg.h revision 186352
1219820Sjeff/* $NetBSD: armreg.h,v 1.37 2007/01/06 00:50:54 christos Exp $ */ 2219820Sjeff 3219820Sjeff/*- 4219820Sjeff * Copyright (c) 1998, 2001 Ben Harris 5219820Sjeff * Copyright (c) 1994-1996 Mark Brinicombe. 6219820Sjeff * Copyright (c) 1994 Brini. 7219820Sjeff * All rights reserved. 8219820Sjeff * 9219820Sjeff * This code is derived from software written for Brini by Mark Brinicombe 10219820Sjeff * 11219820Sjeff * Redistribution and use in source and binary forms, with or without 12219820Sjeff * modification, are permitted provided that the following conditions 13219820Sjeff * are met: 14219820Sjeff * 1. Redistributions of source code must retain the above copyright 15219820Sjeff * notice, this list of conditions and the following disclaimer. 16219820Sjeff * 2. Redistributions in binary form must reproduce the above copyright 17219820Sjeff * notice, this list of conditions and the following disclaimer in the 18219820Sjeff * documentation and/or other materials provided with the distribution. 19219820Sjeff * 3. All advertising materials mentioning features or use of this software 20219820Sjeff * must display the following acknowledgement: 21219820Sjeff * This product includes software developed by Brini. 22219820Sjeff * 4. The name of the company nor the name of the author may be used to 23219820Sjeff * endorse or promote products derived from this software without specific 24219820Sjeff * prior written permission. 25219820Sjeff * 26219820Sjeff * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 27219820Sjeff * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28219820Sjeff * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29219820Sjeff * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30219820Sjeff * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31219820Sjeff * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32219820Sjeff * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33219820Sjeff * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34219820Sjeff * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35219820Sjeff * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36219820Sjeff * SUCH DAMAGE. 37219820Sjeff * 38219820Sjeff * $FreeBSD: head/sys/arm/include/armreg.h 186352 2008-12-20 03:26:09Z sam $ 39219820Sjeff */ 40219820Sjeff 41219820Sjeff#ifndef MACHINE_ARMREG_H 42219820Sjeff#define MACHINE_ARMREG_H 43219820Sjeff 44219820Sjeff#define INSN_SIZE 4 45219820Sjeff#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 46219820Sjeff#define PSR_MODE 0x0000001f /* mode mask */ 47219820Sjeff#define PSR_USR26_MODE 0x00000000 48219820Sjeff#define PSR_FIQ26_MODE 0x00000001 49219820Sjeff#define PSR_IRQ26_MODE 0x00000002 50219820Sjeff#define PSR_SVC26_MODE 0x00000003 51219820Sjeff#define PSR_USR32_MODE 0x00000010 52219820Sjeff#define PSR_FIQ32_MODE 0x00000011 53219820Sjeff#define PSR_IRQ32_MODE 0x00000012 54219820Sjeff#define PSR_SVC32_MODE 0x00000013 55219820Sjeff#define PSR_ABT32_MODE 0x00000017 56219820Sjeff#define PSR_UND32_MODE 0x0000001b 57219820Sjeff#define PSR_SYS32_MODE 0x0000001f 58219820Sjeff#define PSR_32_MODE 0x00000010 59219820Sjeff#define PSR_FLAGS 0xf0000000 /* flags */ 60219820Sjeff 61219820Sjeff#define PSR_C_bit (1 << 29) /* carry */ 62219820Sjeff 63219820Sjeff/* The high-order byte is always the implementor */ 64219820Sjeff#define CPU_ID_IMPLEMENTOR_MASK 0xff000000 65219820Sjeff#define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ 66219820Sjeff#define CPU_ID_DEC 0x44000000 /* 'D' */ 67219820Sjeff#define CPU_ID_INTEL 0x69000000 /* 'i' */ 68219820Sjeff#define CPU_ID_TI 0x54000000 /* 'T' */ 69219820Sjeff#define CPU_ID_FARADAY 0x66000000 /* 'f' */ 70219820Sjeff 71219820Sjeff/* How to decide what format the CPUID is in. */ 72219820Sjeff#define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) 73219820Sjeff#define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) 74219820Sjeff#define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) 75219820Sjeff 76219820Sjeff/* On ARM3 and ARM6, this byte holds the foundry ID. */ 77219820Sjeff#define CPU_ID_FOUNDRY_MASK 0x00ff0000 78219820Sjeff#define CPU_ID_FOUNDRY_VLSI 0x00560000 79219820Sjeff 80219820Sjeff/* On ARM7 it holds the architecture and variant (sub-model) */ 81219820Sjeff#define CPU_ID_7ARCH_MASK 0x00800000 82219820Sjeff#define CPU_ID_7ARCH_V3 0x00000000 83219820Sjeff#define CPU_ID_7ARCH_V4T 0x00800000 84219820Sjeff#define CPU_ID_7VARIANT_MASK 0x007f0000 85219820Sjeff 86219820Sjeff/* On more recent ARMs, it does the same, but in a different format */ 87219820Sjeff#define CPU_ID_ARCH_MASK 0x000f0000 88219820Sjeff#define CPU_ID_ARCH_V3 0x00000000 89219820Sjeff#define CPU_ID_ARCH_V4 0x00010000 90219820Sjeff#define CPU_ID_ARCH_V4T 0x00020000 91219820Sjeff#define CPU_ID_ARCH_V5 0x00030000 92219820Sjeff#define CPU_ID_ARCH_V5T 0x00040000 93219820Sjeff#define CPU_ID_ARCH_V5TE 0x00050000 94219820Sjeff#define CPU_ID_ARCH_V5TEJ 0x00060000 95219820Sjeff#define CPU_ID_ARCH_V6 0x00070000 96219820Sjeff#define CPU_ID_VARIANT_MASK 0x00f00000 97219820Sjeff 98219820Sjeff/* Next three nybbles are part number */ 99219820Sjeff#define CPU_ID_PARTNO_MASK 0x0000fff0 100219820Sjeff 101219820Sjeff/* Intel XScale has sub fields in part number */ 102219820Sjeff#define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ 103219820Sjeff#define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ 104219820Sjeff#define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ 105219820Sjeff 106219820Sjeff/* And finally, the revision number. */ 107219820Sjeff#define CPU_ID_REVISION_MASK 0x0000000f 108219820Sjeff 109219820Sjeff/* Individual CPUs are probably best IDed by everything but the revision. */ 110219820Sjeff#define CPU_ID_CPU_MASK 0xfffffff0 111219820Sjeff 112219820Sjeff/* Fake CPU IDs for ARMs without CP15 */ 113219820Sjeff#define CPU_ID_ARM2 0x41560200 114219820Sjeff#define CPU_ID_ARM250 0x41560250 115219820Sjeff 116219820Sjeff/* Pre-ARM7 CPUs -- [15:12] == 0 */ 117219820Sjeff#define CPU_ID_ARM3 0x41560300 118219820Sjeff#define CPU_ID_ARM600 0x41560600 119219820Sjeff#define CPU_ID_ARM610 0x41560610 120219820Sjeff#define CPU_ID_ARM620 0x41560620 121219820Sjeff 122219820Sjeff/* ARM7 CPUs -- [15:12] == 7 */ 123219820Sjeff#define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */ 124219820Sjeff#define CPU_ID_ARM710 0x41007100 125219820Sjeff#define CPU_ID_ARM7500 0x41027100 126219820Sjeff#define CPU_ID_ARM710A 0x41047100 /* inc ARM7100 */ 127219820Sjeff#define CPU_ID_ARM7500FE 0x41077100 128219820Sjeff#define CPU_ID_ARM710T 0x41807100 129219820Sjeff#define CPU_ID_ARM720T 0x41807200 130219820Sjeff#define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */ 131219820Sjeff#define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */ 132219820Sjeff 133219820Sjeff/* Post-ARM7 CPUs */ 134219820Sjeff#define CPU_ID_ARM810 0x41018100 135219820Sjeff#define CPU_ID_ARM920T 0x41129200 136219820Sjeff#define CPU_ID_ARM920T_ALT 0x41009200 137219820Sjeff#define CPU_ID_ARM922T 0x41029220 138219820Sjeff#define CPU_ID_ARM926EJS 0x41069260 139219820Sjeff#define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ 140219820Sjeff#define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ 141219820Sjeff#define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ 142219820Sjeff#define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ 143219820Sjeff#define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ 144219820Sjeff#define CPU_ID_ARM1022ES 0x4105a220 145219820Sjeff#define CPU_ID_ARM1026EJS 0x4106a260 146219820Sjeff#define CPU_ID_ARM1136JS 0x4107b360 147219820Sjeff#define CPU_ID_ARM1136JSR1 0x4117b360 148219820Sjeff#define CPU_ID_SA110 0x4401a100 149219820Sjeff#define CPU_ID_SA1100 0x4401a110 150219820Sjeff#define CPU_ID_TI925T 0x54029250 151219820Sjeff#define CPU_ID_MV88FR131 0x56251310 /* Marvell Feroceon 88FR131 Core */ 152219820Sjeff#define CPU_ID_MV88FR571_VD 0x56155710 /* Marvell Feroceon 88FR571-VD Core (ID from datasheet) */ 153219820Sjeff#define CPU_ID_MV88FR571_41 0x41159260 /* Marvell Feroceon 88FR571-VD Core (actual ID from CPU reg) */ 154219820Sjeff#define CPU_ID_FA526 0x66015260 155219820Sjeff#define CPU_ID_SA1110 0x6901b110 156219820Sjeff#define CPU_ID_IXP1200 0x6901c120 157219820Sjeff#define CPU_ID_80200 0x69052000 158219820Sjeff#define CPU_ID_PXA250 0x69052100 /* sans core revision */ 159219820Sjeff#define CPU_ID_PXA210 0x69052120 160219820Sjeff#define CPU_ID_PXA250A 0x69052100 /* 1st version Core */ 161219820Sjeff#define CPU_ID_PXA210A 0x69052120 /* 1st version Core */ 162219820Sjeff#define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ 163219820Sjeff#define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ 164219820Sjeff#define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ 165219820Sjeff#define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ 166219820Sjeff#define CPU_ID_PXA27X 0x69054110 167219820Sjeff#define CPU_ID_80321_400 0x69052420 168219820Sjeff#define CPU_ID_80321_600 0x69052430 169219820Sjeff#define CPU_ID_80321_400_B0 0x69052c20 170219820Sjeff#define CPU_ID_80321_600_B0 0x69052c30 171219820Sjeff#define CPU_ID_80219_400 0x69052e20 /* A0 stepping/revision. */ 172219820Sjeff#define CPU_ID_80219_600 0x69052e30 /* A0 stepping/revision. */ 173219820Sjeff#define CPU_ID_81342 0x69056810 174219820Sjeff#define CPU_ID_IXP425_533 0x690541c0 175219820Sjeff#define CPU_ID_IXP425_400 0x690541d0 176219820Sjeff#define CPU_ID_IXP425_266 0x690541f0 177219820Sjeff#define CPU_ID_IXP435 0x69054040 178219820Sjeff 179219820Sjeff/* ARM3-specific coprocessor 15 registers */ 180219820Sjeff#define ARM3_CP15_FLUSH 1 181219820Sjeff#define ARM3_CP15_CONTROL 2 182219820Sjeff#define ARM3_CP15_CACHEABLE 3 183219820Sjeff#define ARM3_CP15_UPDATEABLE 4 184219820Sjeff#define ARM3_CP15_DISRUPTIVE 5 185219820Sjeff 186219820Sjeff/* ARM3 Control register bits */ 187219820Sjeff#define ARM3_CTL_CACHE_ON 0x00000001 188219820Sjeff#define ARM3_CTL_SHARED 0x00000002 189219820Sjeff#define ARM3_CTL_MONITOR 0x00000004 190219820Sjeff 191219820Sjeff/* 192219820Sjeff * Post-ARM3 CP15 registers: 193219820Sjeff * 194219820Sjeff * 1 Control register 195219820Sjeff * 196219820Sjeff * 2 Translation Table Base 197219820Sjeff * 198219820Sjeff * 3 Domain Access Control 199219820Sjeff * 200219820Sjeff * 4 Reserved 201219820Sjeff * 202219820Sjeff * 5 Fault Status 203219820Sjeff * 204219820Sjeff * 6 Fault Address 205219820Sjeff * 206219820Sjeff * 7 Cache/write-buffer Control 207219820Sjeff * 208219820Sjeff * 8 TLB Control 209219820Sjeff * 210219820Sjeff * 9 Cache Lockdown 211219820Sjeff * 212219820Sjeff * 10 TLB Lockdown 213219820Sjeff * 214219820Sjeff * 11 Reserved 215219820Sjeff * 216219820Sjeff * 12 Reserved 217219820Sjeff * 218219820Sjeff * 13 Process ID (for FCSE) 219219820Sjeff * 220219820Sjeff * 14 Reserved 221219820Sjeff * 222219820Sjeff * 15 Implementation Dependent 223219820Sjeff */ 224219820Sjeff 225219820Sjeff/* Some of the definitions below need cleaning up for V3/V4 architectures */ 226219820Sjeff 227219820Sjeff/* CPU control register (CP15 register 1) */ 228219820Sjeff#define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ 229219820Sjeff#define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ 230219820Sjeff#define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ 231219820Sjeff#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ 232219820Sjeff#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ 233219820Sjeff#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ 234219820Sjeff#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ 235219820Sjeff#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ 236219820Sjeff#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ 237219820Sjeff#define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ 238219820Sjeff#define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ 239219820Sjeff#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ 240219820Sjeff#define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ 241219820Sjeff#define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ 242219820Sjeff#define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ 243219820Sjeff#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ 244219820Sjeff#define CPU_CONTROL_L2_ENABLE 0x04000000 /* L2 Cache enabled */ 245219820Sjeff 246219820Sjeff#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE 247219820Sjeff 248219820Sjeff/* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */ 249219820Sjeff#define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */ 250219820Sjeff#define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */ 251219820Sjeff/* Note: XSCale core 3 uses those for LLR DCcahce attributes */ 252219820Sjeff#define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */ 253219820Sjeff#define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */ 254219820Sjeff#define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */ 255219820Sjeff#define XSCALE_AUXCTL_MD_MASK 0x00000030 256219820Sjeff 257219820Sjeff/* Xscale Core 3 only */ 258219820Sjeff#define XSCALE_AUXCTL_LLR 0x00000400 /* Enable L2 for LLR Cache */ 259219820Sjeff 260219820Sjeff/* Marvell Feroceon Extra Features Register (CP15 register 1, opcode2 0) */ 261219820Sjeff#define FC_DCACHE_REPL_LOCK 0x80000000 /* Replace DCache Lock */ 262219820Sjeff#define FC_DCACHE_STREAM_EN 0x20000000 /* DCache Streaming Switch */ 263219820Sjeff#define FC_WR_ALLOC_EN 0x10000000 /* Enable Write Allocate */ 264219820Sjeff#define FC_L2_PREF_DIS 0x01000000 /* L2 Cache Prefetch Disable */ 265219820Sjeff#define FC_L2_INV_EVICT_LINE 0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */ 266219820Sjeff#define FC_L2CACHE_EN 0x00400000 /* L2 enable */ 267219820Sjeff#define FC_ICACHE_REPL_LOCK 0x00080000 /* Replace ICache Lock */ 268219820Sjeff#define FC_GLOB_HIST_REG_EN 0x00040000 /* Branch Global History Register Enable */ 269219820Sjeff#define FC_BRANCH_TARG_BUF_DIS 0x00020000 /* Branch Target Buffer Disable */ 270219820Sjeff#define FC_L1_PAR_ERR_EN 0x00010000 /* L1 Parity Error Enable */ 271219820Sjeff 272219820Sjeff/* Cache type register definitions */ 273219820Sjeff#define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ 274219820Sjeff#define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ 275219820Sjeff#define CPU_CT_S (1U << 24) /* split cache */ 276219820Sjeff#define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ 277219820Sjeff 278219820Sjeff#define CPU_CT_CTYPE_WT 0 /* write-through */ 279219820Sjeff#define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ 280219820Sjeff#define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ 281219820Sjeff#define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ 282219820Sjeff#define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ 283219820Sjeff 284219820Sjeff#define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ 285219820Sjeff#define CPU_CT_xSIZE_M (1U << 2) /* multiplier */ 286219820Sjeff#define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ 287219820Sjeff#define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ 288219820Sjeff 289219820Sjeff/* Fault status register definitions */ 290219820Sjeff 291219820Sjeff#define FAULT_TYPE_MASK 0x0f 292219820Sjeff#define FAULT_USER 0x10 293219820Sjeff 294219820Sjeff#define FAULT_WRTBUF_0 0x00 /* Vector Exception */ 295219820Sjeff#define FAULT_WRTBUF_1 0x02 /* Terminal Exception */ 296219820Sjeff#define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */ 297219820Sjeff#define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */ 298219820Sjeff#define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */ 299219820Sjeff#define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */ 300219820Sjeff#define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */ 301219820Sjeff#define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */ 302219820Sjeff#define FAULT_ALIGN_0 0x01 /* Alignment */ 303219820Sjeff#define FAULT_ALIGN_1 0x03 /* Alignment */ 304219820Sjeff#define FAULT_TRANS_S 0x05 /* Translation -- Section */ 305219820Sjeff#define FAULT_TRANS_P 0x07 /* Translation -- Page */ 306219820Sjeff#define FAULT_DOMAIN_S 0x09 /* Domain -- Section */ 307219820Sjeff#define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ 308219820Sjeff#define FAULT_PERM_S 0x0d /* Permission -- Section */ 309219820Sjeff#define FAULT_PERM_P 0x0f /* Permission -- Page */ 310219820Sjeff 311219820Sjeff#define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */ 312219820Sjeff 313219820Sjeff/* 314219820Sjeff * Address of the vector page, low and high versions. 315219820Sjeff */ 316219820Sjeff#define ARM_VECTORS_LOW 0x00000000U 317219820Sjeff#define ARM_VECTORS_HIGH 0xffff0000U 318219820Sjeff 319219820Sjeff/* 320219820Sjeff * ARM Instructions 321219820Sjeff * 322219820Sjeff * 3 3 2 2 2 323219820Sjeff * 1 0 9 8 7 0 324219820Sjeff * +-------+-------------------------------------------------------+ 325219820Sjeff * | cond | instruction dependant | 326219820Sjeff * |c c c c| | 327219820Sjeff * +-------+-------------------------------------------------------+ 328219820Sjeff */ 329219820Sjeff 330219820Sjeff#define INSN_SIZE 4 /* Always 4 bytes */ 331219820Sjeff#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 332219820Sjeff#define INSN_COND_AL 0xe0000000 /* Always condition */ 333219820Sjeff 334219820Sjeff#define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */ 335219820Sjeff 336219820Sjeff#endif /* !MACHINE_ARMREG_H */ 337219820Sjeff