armreg.h revision 183835
1193323Sed/* $NetBSD: armreg.h,v 1.37 2007/01/06 00:50:54 christos Exp $ */ 2193323Sed 3193323Sed/*- 4193323Sed * Copyright (c) 1998, 2001 Ben Harris 5193323Sed * Copyright (c) 1994-1996 Mark Brinicombe. 6193323Sed * Copyright (c) 1994 Brini. 7193323Sed * All rights reserved. 8193323Sed * 9193323Sed * This code is derived from software written for Brini by Mark Brinicombe 10193323Sed * 11193323Sed * Redistribution and use in source and binary forms, with or without 12193323Sed * modification, are permitted provided that the following conditions 13193323Sed * are met: 14193323Sed * 1. Redistributions of source code must retain the above copyright 15193323Sed * notice, this list of conditions and the following disclaimer. 16243830Sdim * 2. Redistributions in binary form must reproduce the above copyright 17226633Sdim * notice, this list of conditions and the following disclaimer in the 18239462Sdim * documentation and/or other materials provided with the distribution. 19239462Sdim * 3. All advertising materials mentioning features or use of this software 20193323Sed * must display the following acknowledgement: 21193323Sed * This product includes software developed by Brini. 22239462Sdim * 4. The name of the company nor the name of the author may be used to 23239462Sdim * endorse or promote products derived from this software without specific 24239462Sdim * prior written permission. 25239462Sdim * 26239462Sdim * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 27239462Sdim * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28239462Sdim * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29239462Sdim * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30239462Sdim * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31239462Sdim * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32239462Sdim * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33239462Sdim * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34239462Sdim * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35239462Sdim * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36239462Sdim * SUCH DAMAGE. 37195340Sed * 38277320Sdim * $FreeBSD: head/sys/arm/include/armreg.h 183835 2008-10-13 18:16:54Z raj $ 39193323Sed */ 40277320Sdim 41277320Sdim#ifndef MACHINE_ARMREG_H 42193323Sed#define MACHINE_ARMREG_H 43277320Sdim 44277320Sdim#define INSN_SIZE 4 45277320Sdim#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 46277320Sdim#define PSR_MODE 0x0000001f /* mode mask */ 47277320Sdim#define PSR_USR26_MODE 0x00000000 48277320Sdim#define PSR_FIQ26_MODE 0x00000001 49277320Sdim#define PSR_IRQ26_MODE 0x00000002 50277320Sdim#define PSR_SVC26_MODE 0x00000003 51193323Sed#define PSR_USR32_MODE 0x00000010 52277320Sdim#define PSR_FIQ32_MODE 0x00000011 53277320Sdim#define PSR_IRQ32_MODE 0x00000012 54277320Sdim#define PSR_SVC32_MODE 0x00000013 55277320Sdim#define PSR_ABT32_MODE 0x00000017 56277320Sdim#define PSR_UND32_MODE 0x0000001b 57277320Sdim#define PSR_SYS32_MODE 0x0000001f 58193323Sed#define PSR_32_MODE 0x00000010 59193323Sed#define PSR_FLAGS 0xf0000000 /* flags */ 60193323Sed 61195340Sed#define PSR_C_bit (1 << 29) /* carry */ 62193323Sed 63193323Sed/* The high-order byte is always the implementor */ 64193323Sed#define CPU_ID_IMPLEMENTOR_MASK 0xff000000 65193323Sed#define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ 66218893Sdim#define CPU_ID_DEC 0x44000000 /* 'D' */ 67193323Sed#define CPU_ID_INTEL 0x69000000 /* 'i' */ 68218893Sdim#define CPU_ID_TI 0x54000000 /* 'T' */ 69193323Sed#define CPU_ID_FARADAY 0x66000000 /* 'f' */ 70193323Sed 71193323Sed/* How to decide what format the CPUID is in. */ 72288943Sdim#define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) 73193323Sed#define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) 74193323Sed#define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) 75193323Sed 76193323Sed/* On ARM3 and ARM6, this byte holds the foundry ID. */ 77193323Sed#define CPU_ID_FOUNDRY_MASK 0x00ff0000 78193323Sed#define CPU_ID_FOUNDRY_VLSI 0x00560000 79193323Sed 80193323Sed/* On ARM7 it holds the architecture and variant (sub-model) */ 81193323Sed#define CPU_ID_7ARCH_MASK 0x00800000 82195340Sed#define CPU_ID_7ARCH_V3 0x00000000 83193323Sed#define CPU_ID_7ARCH_V4T 0x00800000 84193323Sed#define CPU_ID_7VARIANT_MASK 0x007f0000 85193323Sed 86193323Sed/* On more recent ARMs, it does the same, but in a different format */ 87193323Sed#define CPU_ID_ARCH_MASK 0x000f0000 88193323Sed#define CPU_ID_ARCH_V3 0x00000000 89193323Sed#define CPU_ID_ARCH_V4 0x00010000 90288943Sdim#define CPU_ID_ARCH_V4T 0x00020000 91193323Sed#define CPU_ID_ARCH_V5 0x00030000 92193323Sed#define CPU_ID_ARCH_V5T 0x00040000 93193323Sed#define CPU_ID_ARCH_V5TE 0x00050000 94193323Sed#define CPU_ID_ARCH_V5TEJ 0x00060000 95193323Sed#define CPU_ID_ARCH_V6 0x00070000 96193323Sed#define CPU_ID_VARIANT_MASK 0x00f00000 97193323Sed 98193323Sed/* Next three nybbles are part number */ 99193323Sed#define CPU_ID_PARTNO_MASK 0x0000fff0 100243830Sdim 101193323Sed/* Intel XScale has sub fields in part number */ 102193323Sed#define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ 103193323Sed#define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ 104193323Sed#define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ 105193323Sed 106193323Sed/* And finally, the revision number. */ 107193323Sed#define CPU_ID_REVISION_MASK 0x0000000f 108193323Sed 109193323Sed/* Individual CPUs are probably best IDed by everything but the revision. */ 110193323Sed#define CPU_ID_CPU_MASK 0xfffffff0 111193323Sed 112193323Sed/* Fake CPU IDs for ARMs without CP15 */ 113193323Sed#define CPU_ID_ARM2 0x41560200 114288943Sdim#define CPU_ID_ARM250 0x41560250 115193323Sed 116193323Sed/* Pre-ARM7 CPUs -- [15:12] == 0 */ 117193323Sed#define CPU_ID_ARM3 0x41560300 118276479Sdim#define CPU_ID_ARM600 0x41560600 119193323Sed#define CPU_ID_ARM610 0x41560610 120193323Sed#define CPU_ID_ARM620 0x41560620 121288943Sdim 122193323Sed/* ARM7 CPUs -- [15:12] == 7 */ 123193323Sed#define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */ 124193323Sed#define CPU_ID_ARM710 0x41007100 125193323Sed#define CPU_ID_ARM7500 0x41027100 126193323Sed#define CPU_ID_ARM710A 0x41047100 /* inc ARM7100 */ 127288943Sdim#define CPU_ID_ARM7500FE 0x41077100 128193323Sed#define CPU_ID_ARM710T 0x41807100 129193323Sed#define CPU_ID_ARM720T 0x41807200 130193323Sed#define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */ 131193323Sed#define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */ 132193323Sed 133193323Sed/* Post-ARM7 CPUs */ 134193323Sed#define CPU_ID_ARM810 0x41018100 135193323Sed#define CPU_ID_ARM920T 0x41129200 136288943Sdim#define CPU_ID_ARM920T_ALT 0x41009200 137243830Sdim#define CPU_ID_ARM922T 0x41029220 138193323Sed#define CPU_ID_ARM926EJS 0x41069260 139288943Sdim#define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ 140193323Sed#define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ 141193323Sed#define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ 142193323Sed#define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ 143193323Sed#define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ 144193323Sed#define CPU_ID_ARM1022ES 0x4105a220 145193323Sed#define CPU_ID_ARM1026EJS 0x4106a260 146193323Sed#define CPU_ID_ARM1136JS 0x4107b360 147193323Sed#define CPU_ID_ARM1136JSR1 0x4117b360 148276479Sdim#define CPU_ID_SA110 0x4401a100 149193323Sed#define CPU_ID_SA1100 0x4401a110 150193323Sed#define CPU_ID_TI925T 0x54029250 151288943Sdim#define CPU_ID_MV88FR131 0x56251310 /* Marvell Feroceon 88FR131 Core */ 152193323Sed#define CPU_ID_MV88FR571_VD 0x56155710 /* Marvell Feroceon 88FR571-VD Core (ID from datasheet) */ 153193323Sed#define CPU_ID_MV88FR571_41 0x41159260 /* Marvell Feroceon 88FR571-VD Core (actual ID from CPU reg) */ 154193323Sed#define CPU_ID_FA526 0x66015260 155193323Sed#define CPU_ID_SA1110 0x6901b110 156193323Sed#define CPU_ID_IXP1200 0x6901c120 157276479Sdim#define CPU_ID_80200 0x69052000 158193323Sed#define CPU_ID_PXA250 0x69052100 /* sans core revision */ 159193323Sed#define CPU_ID_PXA210 0x69052120 160288943Sdim#define CPU_ID_PXA250A 0x69052100 /* 1st version Core */ 161193323Sed#define CPU_ID_PXA210A 0x69052120 /* 1st version Core */ 162193323Sed#define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ 163193323Sed#define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ 164193323Sed#define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ 165193323Sed#define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ 166193323Sed#define CPU_ID_PXA27X 0x69054110 167193323Sed#define CPU_ID_80321_400 0x69052420 168288943Sdim#define CPU_ID_80321_600 0x69052430 169193323Sed#define CPU_ID_80321_400_B0 0x69052c20 170193323Sed#define CPU_ID_80321_600_B0 0x69052c30 171193323Sed#define CPU_ID_80219_400 0x69052e20 /* A0 stepping/revision. */ 172193323Sed#define CPU_ID_80219_600 0x69052e30 /* A0 stepping/revision. */ 173193323Sed#define CPU_ID_81342 0x69056810 174193323Sed#define CPU_ID_IXP425_533 0x690541c0 175193323Sed#define CPU_ID_IXP425_400 0x690541d0 176193323Sed#define CPU_ID_IXP425_266 0x690541f0 177193323Sed 178193323Sed/* ARM3-specific coprocessor 15 registers */ 179193323Sed#define ARM3_CP15_FLUSH 1 180193323Sed#define ARM3_CP15_CONTROL 2 181193323Sed#define ARM3_CP15_CACHEABLE 3 182193323Sed#define ARM3_CP15_UPDATEABLE 4 183280031Sdim#define ARM3_CP15_DISRUPTIVE 5 184296417Sdim 185296417Sdim/* ARM3 Control register bits */ 186280031Sdim#define ARM3_CTL_CACHE_ON 0x00000001 187193323Sed#define ARM3_CTL_SHARED 0x00000002 188193323Sed#define ARM3_CTL_MONITOR 0x00000004 189193323Sed 190280031Sdim/* 191296417Sdim * Post-ARM3 CP15 registers: 192296417Sdim * 193280031Sdim * 1 Control register 194193323Sed * 195193323Sed * 2 Translation Table Base 196193323Sed * 197193323Sed * 3 Domain Access Control 198276479Sdim * 199276479Sdim * 4 Reserved 200276479Sdim * 201276479Sdim * 5 Fault Status 202276479Sdim * 203276479Sdim * 6 Fault Address 204276479Sdim * 205276479Sdim * 7 Cache/write-buffer Control 206276479Sdim * 207276479Sdim * 8 TLB Control 208288943Sdim * 209276479Sdim * 9 Cache Lockdown 210276479Sdim * 211276479Sdim * 10 TLB Lockdown 212276479Sdim * 213276479Sdim * 11 Reserved 214276479Sdim * 215276479Sdim * 12 Reserved 216276479Sdim * 217288943Sdim * 13 Process ID (for FCSE) 218276479Sdim * 219276479Sdim * 14 Reserved 220276479Sdim * 221193323Sed * 15 Implementation Dependent 222193323Sed */ 223276479Sdim 224276479Sdim/* Some of the definitions below need cleaning up for V3/V4 architectures */ 225276479Sdim 226276479Sdim/* CPU control register (CP15 register 1) */ 227276479Sdim#define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ 228276479Sdim#define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ 229276479Sdim#define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ 230276479Sdim#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ 231276479Sdim#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ 232276479Sdim#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ 233276479Sdim#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ 234276479Sdim#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ 235277320Sdim#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ 236277320Sdim#define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ 237277320Sdim#define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ 238277320Sdim#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ 239277320Sdim#define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ 240277320Sdim#define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ 241277320Sdim#define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ 242277320Sdim#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ 243277320Sdim#define CPU_CONTROL_L2_ENABLE 0x04000000 /* L2 Cache enabled */ 244277320Sdim 245277320Sdim#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE 246277320Sdim 247277320Sdim/* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */ 248277320Sdim#define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */ 249277320Sdim#define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */ 250193323Sed/* Note: XSCale core 3 uses those for LLR DCcahce attributes */ 251193323Sed#define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */ 252193323Sed#define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */ 253193323Sed#define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */ 254198090Srdivacky#define XSCALE_AUXCTL_MD_MASK 0x00000030 255198090Srdivacky 256198090Srdivacky/* Xscale Core 3 only */ 257198090Srdivacky#define XSCALE_AUXCTL_LLR 0x00000400 /* Enable L2 for LLR Cache */ 258193323Sed 259193323Sed/* Marvell Feroceon Extra Features Register (CP15 register 1, opcode2 0) */ 260193323Sed#define FC_DCACHE_REPL_LOCK 0x80000000 /* Replace DCache Lock */ 261193323Sed#define FC_DCACHE_STREAM_EN 0x20000000 /* DCache Streaming Switch */ 262193323Sed#define FC_WR_ALLOC_EN 0x10000000 /* Enable Write Allocate */ 263193323Sed#define FC_L2_PREF_DIS 0x01000000 /* L2 Cache Prefetch Disable */ 264193323Sed#define FC_L2_INV_EVICT_LINE 0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */ 265193323Sed#define FC_L2CACHE_EN 0x00400000 /* L2 enable */ 266193323Sed#define FC_ICACHE_REPL_LOCK 0x00080000 /* Replace ICache Lock */ 267193323Sed#define FC_GLOB_HIST_REG_EN 0x00040000 /* Branch Global History Register Enable */ 268193323Sed#define FC_BRANCH_TARG_BUF_DIS 0x00020000 /* Branch Target Buffer Disable */ 269193323Sed#define FC_L1_PAR_ERR_EN 0x00010000 /* L1 Parity Error Enable */ 270193323Sed 271193323Sed/* Cache type register definitions */ 272243830Sdim#define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ 273193323Sed#define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ 274193323Sed#define CPU_CT_S (1U << 24) /* split cache */ 275193323Sed#define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ 276239462Sdim 277239462Sdim#define CPU_CT_CTYPE_WT 0 /* write-through */ 278239462Sdim#define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ 279239462Sdim#define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ 280239462Sdim#define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ 281239462Sdim#define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ 282239462Sdim 283239462Sdim#define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ 284239462Sdim#define CPU_CT_xSIZE_M (1U << 2) /* multiplier */ 285#define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ 286#define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ 287 288/* Fault status register definitions */ 289 290#define FAULT_TYPE_MASK 0x0f 291#define FAULT_USER 0x10 292 293#define FAULT_WRTBUF_0 0x00 /* Vector Exception */ 294#define FAULT_WRTBUF_1 0x02 /* Terminal Exception */ 295#define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */ 296#define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */ 297#define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */ 298#define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */ 299#define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */ 300#define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */ 301#define FAULT_ALIGN_0 0x01 /* Alignment */ 302#define FAULT_ALIGN_1 0x03 /* Alignment */ 303#define FAULT_TRANS_S 0x05 /* Translation -- Section */ 304#define FAULT_TRANS_P 0x07 /* Translation -- Page */ 305#define FAULT_DOMAIN_S 0x09 /* Domain -- Section */ 306#define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ 307#define FAULT_PERM_S 0x0d /* Permission -- Section */ 308#define FAULT_PERM_P 0x0f /* Permission -- Page */ 309 310#define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */ 311 312/* 313 * Address of the vector page, low and high versions. 314 */ 315#define ARM_VECTORS_LOW 0x00000000U 316#define ARM_VECTORS_HIGH 0xffff0000U 317 318/* 319 * ARM Instructions 320 * 321 * 3 3 2 2 2 322 * 1 0 9 8 7 0 323 * +-------+-------------------------------------------------------+ 324 * | cond | instruction dependant | 325 * |c c c c| | 326 * +-------+-------------------------------------------------------+ 327 */ 328 329#define INSN_SIZE 4 /* Always 4 bytes */ 330#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 331#define INSN_COND_AL 0xe0000000 /* Always condition */ 332 333#define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */ 334 335#endif /* !MACHINE_ARMREG_H */ 336