1248557Sray/* $NetBSD: imx51_ccmreg.h,v 1.1 2012/04/17 09:33:31 bsh Exp $ */ 2248557Sray/* 3248557Sray * Copyright (c) 2011, 2012 Genetec Corporation. All rights reserved. 4248557Sray * Written by Hashimoto Kenichi for Genetec Corporation. 5248557Sray * 6248557Sray * Redistribution and use in source and binary forms, with or without 7248557Sray * modification, are permitted provided that the following conditions 8248557Sray * are met: 9248557Sray * 1. Redistributions of source code must retain the above copyright 10248557Sray * notice, this list of conditions and the following disclaimer. 11248557Sray * 2. Redistributions in binary form must reproduce the above copyright 12248557Sray * notice, this list of conditions and the following disclaimer in the 13248557Sray * documentation and/or other materials provided with the distribution. 14248557Sray * 15248557Sray * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 16248557Sray * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 17248557Sray * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 18248557Sray * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 19248557Sray * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20248557Sray * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21248557Sray * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22248557Sray * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23248557Sray * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24248557Sray * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25248557Sray * POSSIBILITY OF SUCH DAMAGE. 26248557Sray */ 27248557Sray 28248557Sray/*- 29250357Sray * Copyright (c) 2012, 2013 The FreeBSD Foundation 30248557Sray * All rights reserved. 31248557Sray * 32248557Sray * Portions of this software were developed by Oleksandr Rybalko 33248557Sray * under sponsorship from the FreeBSD Foundation. 34248557Sray * 35248557Sray * Redistribution and use in source and binary forms, with or without 36248557Sray * modification, are permitted provided that the following conditions 37248557Sray * are met: 38248557Sray * 1. Redistributions of source code must retain the above copyright 39248557Sray * notice, this list of conditions and the following disclaimer. 40248557Sray * 2. Redistributions in binary form must reproduce the above copyright 41248557Sray * notice, this list of conditions and the following disclaimer in the 42248557Sray * documentation and/or other materials provided with the distribution. 43248557Sray * 44248557Sray * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 45248557Sray * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 46248557Sray * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 47248557Sray * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 48248557Sray * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 49248557Sray * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 50248557Sray * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 51248557Sray * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 52248557Sray * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 53248557Sray * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 54248557Sray * SUCH DAMAGE. 55248557Sray * 56248557Sray * $FreeBSD: releng/11.0/sys/arm/freescale/imx/imx51_ccmreg.h 257383 2013-10-30 14:33:15Z ian $ 57248557Sray */ 58248557Sray 59248557Sray#ifndef _IMX51_CCMREG_H 60248557Sray#define _IMX51_CCMREG_H 61248557Sray 62248557Sray#include <sys/cdefs.h> 63248557Sray 64248557Sray/* register offset address */ 65248557Sray 66248557Sray#define CCMC_BASE 0x73fd4000 67248557Sray#define CCMC_CCR 0x0000 68248557Sray#define CCR_FPM_MULT 0x00001000 69248557Sray#define CCMC_CCDR 0x0004 70248557Sray#define CCMC_CSR 0x0008 71248557Sray#define CCMC_CCSR 0x000c 72248557Sray#define CCSR_LP_APM 0x00000200 73248557Sray#define CCSR_STEP_SEL_SHIFT 7 74248557Sray#define CCSR_STEP_SEL_MASK 0x00000180 75248557Sray#define CCSR_PLL2_DIV_PODF_SHIFT 5 76248557Sray#define CCSR_PLL2_DIV_PODF_MASK 0x00000060 77248557Sray#define CCSR_PLL3_DIV_PODF_SHIFT 3 78248557Sray#define CCSR_PLL3_DIV_PODF_MASK 0x00000030 79248557Sray#define CCSR_PLL1_SW_CLK_SEL 0x00000004 80248557Sray#define CCSR_PLL2_SW_CLK_SEL 0x00000002 81248557Sray#define CCSR_PLL3_SW_CLK_SEL 0x00000001 82248557Sray#define CCMC_CACRR 0x0010 83248557Sray#define CCMC_CBCDR 0x0014 84248557Sray#define CBCDR_DDR_HIGH_FREQ_CLK_SEL 0x40000000 85248557Sray#define CBCDR_DDR_CLK_PODF_SHIFT 27 86248557Sray#define CBCDR_DDR_CLK_PODF_MASK 0x38000000 87248557Sray#define CBCDR_EMI_CLK_SEL 0x04000000 88248557Sray#define CBCDR_PERIPH_CLK_SEL 0x02000000 89248557Sray#define CBCDR_EMI_SLOW_PODF_SHIFT 22 90248557Sray#define CBCDR_EMI_SLOW_PODF_MASK 0x01c00000 91248557Sray#define CBCDR_AXI_B_PODF_SHIFT 19 92248557Sray#define CBCDR_AXI_B_PODF_MASK 0x00380000 93248557Sray#define CBCDR_AXI_A_PODF_SHIFT 16 94248557Sray#define CBCDR_AXI_A_PODF_MASK 0x1fff0000 95248557Sray#define CBCDR_NFC_PODF_SHIFT 13 96248557Sray#define CBCDR_NFC_PODF_MASK 0x00018000 97248557Sray#define CBCDR_AHB_PODF_SHIFT 10 98248557Sray#define CBCDR_AHB_PODF_MASK 0x00001c00 99248557Sray#define CBCDR_IPG_PODF_SHIFT 8 100248557Sray#define CBCDR_IPG_PODF_MASK 0x00000300 101248557Sray#define CBCDR_PERCLK_PRED1_SHIFT 6 102248557Sray#define CBCDR_PERCLK_PRED1_MASK 0x000000c0 103248557Sray#define CBCDR_PERCLK_PRED2_SHIFT 3 104248557Sray#define CBCDR_PERCLK_PRED2_MASK 0x00000038 105248557Sray#define CBCDR_PERCLK_PODF_SHIFT 0 106248557Sray#define CBCDR_PERCLK_PODF_MASK 0x00000007 107248557Sray#define CCMC_CBCMR 0x0018 108248557Sray#define CBCMR_PERIPH_APM_SEL_SHIFT 12 109248557Sray#define CBCMR_PERIPH_APM_SEL_MASK 0x00003000 110248557Sray#define CBCMR_IPU_HSP_CLK_SEL_SHIFT 6 111248557Sray#define CBCMR_IPU_HSP_CLK_SEL_MASK 0x000000c0 112248557Sray#define CBCMR_PERCLK_LP_APM_SEL 0x00000002 113248557Sray#define CBCMR_PERCLK_IPG_SEL 0x00000001 114248557Sray#define CCMC_CSCMR1 0x001c 115248557Sray#define CSCMR1_UART_CLK_SEL_SHIFT 24 116248557Sray#define CSCMR1_UART_CLK_SEL_MASK 0x03000000 117257383Sian#define CSCMR1_USBPHY_CLK_SEL_SHIFT 26 118257383Sian#define CSCMR1_USBPHY_CLK_SEL_MASK 0x04000000 119257383Sian#define CSCMR1_USBOH3_CLK_SEL_SHIFT 22 120257383Sian#define CSCMR1_USBOH3_CLK_SEL_MASK 0x00c00000 121248557Sray#define CCMC_CSCMR2 0x0020 122248557Sray#define CCMC_CSCDR1 0x0024 123248557Sray#define CSCDR1_UART_CLK_PRED_SHIFT 3 124248557Sray#define CSCDR1_UART_CLK_PRED_MASK 0x00000038 125248557Sray#define CSCDR1_UART_CLK_PODF_SHIFT 0 126248557Sray#define CSCDR1_UART_CLK_PODF_MASK 0x00000007 127257383Sian#define CSCDR1_USBOH3_CLK_PRED_SHIFT 8 128257383Sian#define CSCDR1_USBOH3_CLK_PRED_MASK 0x00000700 129257383Sian#define CSCDR1_USBOH3_CLK_PODF_SHIFT 6 130257383Sian#define CSCDR1_USBOH3_CLK_PODF_MASK 0x000000c0 131248557Sray#define CCMC_CS1CDR 0x0028 132248557Sray#define CCMC_CS2CDR 0x002c 133248557Sray#define CCMC_CDCDR 0x0030 134248557Sray#define CCMC_CSCDR2 0x0038 135248557Sray#define CCMC_CSCDR3 0x003c 136248557Sray#define CCMC_CSCDR4 0x0040 137248557Sray#define CCMC_CWDR 0x0044 138248557Sray#define CCMC_CDHIPR 0x0048 139248557Sray#define CCMC_CDCR 0x004c 140248557Sray#define CDCR_PERIPH_CLK_DVFS_PODF_SHIFT 0 141248557Sray#define CDCR_PERIPH_CLK_DVFS_PODF_MASK 0x00000003 142248557Sray#define CCMC_CTOR 0x0050 143248557Sray#define CCMC_CLPCR 0x0054 144248557Sray#define CCMC_CISR 0x0058 145248557Sray#define CCMC_CIMR 0x005c 146248557Sray#define CCMC_CCOSR 0x0060 147248557Sray#define CCMC_CGPR 0x0064 148248557Sray#define CCMC_CCGR(n) (0x0068 + (n) * 4) 149248557Sray#define CCMC_CMEOR 0x0084 150248557Sray 151248557Sray#define CCMC_SIZE 0x88 152248557Sray 153248557Sray/* CCGR Clock Gate Register */ 154248557Sray 155248557Sray#define CCMR_CCGR_NSOURCE 16 156248557Sray#define CCMR_CCGR_NGROUPS 7 157248557Sray#define CCMR_CCGR_MODULE(clk) ((clk) / CCMR_CCGR_NSOURCE) 158248557Sray#define __CCGR_NUM(a, b) ((a) * 16 + (b)) 159248557Sray 160248557Sray#define CCGR_ARM_BUS_CLK __CCGR_NUM(0, 0) 161248557Sray#define CCGR_ARM_AXI_CLK __CCGR_NUM(0, 1) 162248557Sray#define CCGR_ARM_DEBUG_CLK __CCGR_NUM(0, 2) 163248557Sray#define CCGR_TZIC_CLK __CCGR_NUM(0, 3) 164248557Sray#define CCGR_DAP_CLK __CCGR_NUM(0, 4) 165248557Sray#define CCGR_TPIU_CLK __CCGR_NUM(0, 5) 166248557Sray#define CCGR_CTI2_CLK __CCGR_NUM(0, 6) 167248557Sray#define CCGR_CTI3_CLK __CCGR_NUM(0, 7) 168248557Sray#define CCGR_AHBMUX1_CLK __CCGR_NUM(0, 8) 169248557Sray#define CCGR_AHBMUX2_CLK __CCGR_NUM(0, 9) 170248557Sray#define CCGR_ROMCP_CLK __CCGR_NUM(0, 10) 171248557Sray#define CCGR_ROM_CLK __CCGR_NUM(0, 11) 172248557Sray#define CCGR_AIPS_TZ1_CLK __CCGR_NUM(0, 12) 173248557Sray#define CCGR_AIPS_TZ2_CLK __CCGR_NUM(0, 13) 174248557Sray#define CCGR_AHB_MAX_CLK __CCGR_NUM(0, 14) 175248557Sray#define CCGR_IIM_CLK __CCGR_NUM(0, 15) 176248557Sray#define CCGR_TMAX1_CLK __CCGR_NUM(1, 0) 177248557Sray#define CCGR_TMAX2_CLK __CCGR_NUM(1, 1) 178248557Sray#define CCGR_TMAX3_CLK __CCGR_NUM(1, 2) 179248557Sray#define CCGR_UART1_CLK __CCGR_NUM(1, 3) 180248557Sray#define CCGR_UART1_SERIAL_CLK __CCGR_NUM(1, 4) 181248557Sray#define CCGR_UART2_CLK __CCGR_NUM(1, 5) 182248557Sray#define CCGR_UART2_SERIAL_CLK __CCGR_NUM(1, 6) 183248557Sray#define CCGR_UART3_CLK __CCGR_NUM(1, 7) 184248557Sray#define CCGR_UART3_SERIAL_CLK __CCGR_NUM(1, 8) 185248557Sray#define CCGR_I2C1_SERIAL_CLK __CCGR_NUM(1, 9) 186248557Sray#define CCGR_I2C2_SERIAL_CLK __CCGR_NUM(1, 10) 187248557Sray#define CCGR_HSI2C_CLK __CCGR_NUM(1, 11) 188248557Sray#define CCGR_HSI2C_SERIAL_CLK __CCGR_NUM(1, 12) 189248557Sray#define CCGR_FIRI_CLK __CCGR_NUM(1, 13) 190248557Sray#define CCGR_FIRI_SERIAL_CLK __CCGR_NUM(1, 14) 191248557Sray#define CCGR_SCC_CLK __CCGR_NUM(1, 15) 192248557Sray 193248557Sray#define CCGR_USB_PHY_CLK __CCGR_NUM(2, 0) 194248557Sray#define CCGR_EPIT1_CLK __CCGR_NUM(2, 1) 195248557Sray#define CCGR_EPIT1_SERIAL_CLK __CCGR_NUM(2, 2) 196248557Sray#define CCGR_EPIT2_CLK __CCGR_NUM(2, 3) 197248557Sray#define CCGR_EPIT2_SERIAL_CLK __CCGR_NUM(2, 4) 198248557Sray#define CCGR_PWM1_CLK __CCGR_NUM(2, 5) 199248557Sray#define CCGR_PWM1_SERIAL_CLK __CCGR_NUM(2, 6) 200248557Sray#define CCGR_PWM2_CLK __CCGR_NUM(2, 7) 201248557Sray#define CCGR_PWM2_SERIAL_CLK __CCGR_NUM(2, 8) 202248557Sray#define CCGR_GPT_CLK __CCGR_NUM(2, 9) 203248557Sray#define CCGR_GPT_SERIAL_CLK __CCGR_NUM(2, 10) 204248557Sray#define CCGR_OWIRE_CLK __CCGR_NUM(2, 11) 205248557Sray#define CCGR_FEC_CLK __CCGR_NUM(2, 12) 206248557Sray#define CCGR_USBOH3_IPG_AHB_CLK __CCGR_NUM(2, 13) 207248557Sray#define CCGR_USBOH3_60M_CLK __CCGR_NUM(2, 14) 208248557Sray#define CCGR_TVE_CLK __CCGR_NUM(2, 15) 209248557Sray 210248557Sray#define CCGR_ESDHC1_CLK __CCGR_NUM(3, 0) 211248557Sray#define CCGR_ESDHC1_SERIAL_CLK __CCGR_NUM(3, 1) 212248557Sray#define CCGR_ESDHC2_CLK __CCGR_NUM(3, 2) 213248557Sray#define CCGR_ESDHC2_SERIAL_CLK __CCGR_NUM(3, 3) 214248557Sray#define CCGR_ESDHC3_CLK __CCGR_NUM(3, 4) 215248557Sray#define CCGR_ESDHC3_SERIAL_CLK __CCGR_NUM(3, 5) 216248557Sray#define CCGR_ESDHC4_CLK __CCGR_NUM(3, 6) 217248557Sray#define CCGR_ESDHC4_SERIAL_CLK __CCGR_NUM(3, 7) 218248557Sray#define CCGR_SSI1_CLK __CCGR_NUM(3, 8) 219248557Sray#define CCGR_SSI1_SERIAL_CLK __CCGR_NUM(3, 9) 220248557Sray#define CCGR_SSI2_CLK __CCGR_NUM(3, 10) 221248557Sray#define CCGR_SSI2_SERIAL_CLK __CCGR_NUM(3, 11) 222248557Sray#define CCGR_SSI3_CLK __CCGR_NUM(3, 12) 223248557Sray#define CCGR_SSI3_SERIAL_CLK __CCGR_NUM(3, 13) 224248557Sray#define CCGR_SSI_EXT1_CLK __CCGR_NUM(3, 14) 225248557Sray#define CCGR_SSI_EXT2_CLK __CCGR_NUM(3, 15) 226248557Sray 227248557Sray#define CCGR_PATA_CLK __CCGR_NUM(4, 0) 228248557Sray#define CCGR_SIM_CLK __CCGR_NUM(4, 1) 229248557Sray#define CCGR_SIM_SERIAL_CLK __CCGR_NUM(4, 2) 230248557Sray#define CCGR_SAHARA_CLK __CCGR_NUM(4, 3) 231248557Sray#define CCGR_RTIC_CLK __CCGR_NUM(4, 4) 232248557Sray#define CCGR_ECSPI1_CLK __CCGR_NUM(4, 5) 233248557Sray#define CCGR_ECSPI1_SERIAL_CLK __CCGR_NUM(4, 6) 234248557Sray#define CCGR_ECSPI2_CLK __CCGR_NUM(4, 7) 235248557Sray#define CCGR_ECSPI2_SERIAL_CLK __CCGR_NUM(4, 8) 236248557Sray#define CCGR_CSPI_CLK __CCGR_NUM(4, 9) 237248557Sray#define CCGR_SRTC_CLK __CCGR_NUM(4, 10) 238248557Sray#define CCGR_SDMA_CLK __CCGR_NUM(4, 11) 239248557Sray 240248557Sray#define CCGR_SPBA_CLK __CCGR_NUM(5, 0) 241248557Sray#define CCGR_GPU_CLK __CCGR_NUM(5, 1) 242248557Sray#define CCGR_GARB_CLK __CCGR_NUM(5, 2) 243248557Sray#define CCGR_VPU_CLK __CCGR_NUM(5, 3) 244248557Sray#define CCGR_VPU_SERIAL_CLK __CCGR_NUM(5, 4) 245248557Sray#define CCGR_IPU_CLK __CCGR_NUM(5, 5) 246248557Sray#define CCGR_EMI_GARB_CLK __CCGR_NUM(6, 0) 247248557Sray#define CCGR_IPU_DI0_CLK __CCGR_NUM(6, 1) 248248557Sray#define CCGR_IPU_DI1_CLK __CCGR_NUM(6, 2) 249248557Sray#define CCGR_GPU2D_CLK __CCGR_NUM(6, 3) 250248557Sray#define CCGR_SLIMBUS_CLK __CCGR_NUM(6, 4) 251248557Sray#define CCGR_SLIMBUS_SERIAL_CLK __CCGR_NUM(6, 5) 252248557Sray 253248557Sray#define CCGR_CLK_MODE_OFF 0 254248557Sray#define CCGR_CLK_MODE_RUNMODE 1 255248557Sray#define CCGR_CLK_MODE_ALWAYS 3 256248557Sray 257248557Sray#endif /* _IMX51_CCMREG_H */ 258248557Sray 259