1210040Scognet/*- 2210040Scognet * Copyright (c) 2009 Sylvestre Gallon. All rights reserved. 3213496Scognet * Copyright (c) 2010 Greg Ansley. All rights reserved. 4210040Scognet * 5210040Scognet * Redistribution and use in source and binary forms, with or without 6210040Scognet * modification, are permitted provided that the following conditions 7210040Scognet * are met: 8210040Scognet * 1. Redistributions of source code must retain the above copyright 9210040Scognet * notice, this list of conditions and the following disclaimer. 10210040Scognet * 2. Redistributions in binary form must reproduce the above copyright 11210040Scognet * notice, this list of conditions and the following disclaimer in the 12210040Scognet * documentation and/or other materials provided with the distribution. 13210040Scognet * 14210040Scognet * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15210040Scognet * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16210040Scognet * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17210040Scognet * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18210040Scognet * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19210040Scognet * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20210040Scognet * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21210040Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22210040Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23210040Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24210040Scognet * SUCH DAMAGE. 25210040Scognet */ 26210040Scognet 27210040Scognet/* $FreeBSD: releng/11.0/sys/arm/at91/at91sam9g20reg.h 272163 2014-09-26 09:07:02Z kevlo $ */ 28210040Scognet 29210040Scognet#ifndef AT91SAM9G20REG_H_ 30210040Scognet#define AT91SAM9G20REG_H_ 31210040Scognet 32213496Scognet/* Chip Specific limits */ 33213496Scognet#define SAM9G20_PLL_A_MIN_IN_FREQ 2000000 /* 2 Mhz */ 34213496Scognet#define SAM9G20_PLL_A_MAX_IN_FREQ 32000000 /* 32 Mhz */ 35213496Scognet#define SAM9G20_PLL_A_MIN_OUT_FREQ 400000000 /* 400 Mhz */ 36213496Scognet#define SAM9G20_PLL_A_MAX_OUT_FREQ 800000000 /* 800 Mhz */ 37213496Scognet#define SAM9G20_PLL_A_MUL_SHIFT 16 38236989Simp#define SAM9G20_PLL_A_MUL_MASK 0xFF 39213496Scognet#define SAM9G20_PLL_A_DIV_SHIFT 0 40236989Simp#define SAM9G20_PLL_A_DIV_MASK 0xFF 41213496Scognet 42213496Scognet#define SAM9G20_PLL_B_MIN_IN_FREQ 2000000 /* 2 Mhz */ 43213496Scognet#define SAM9G20_PLL_B_MAX_IN_FREQ 32000000 /* 32 Mhz */ 44213496Scognet#define SAM9G20_PLL_B_MIN_OUT_FREQ 30000000 /* 30 Mhz */ 45213496Scognet#define SAM9G20_PLL_B_MAX_OUT_FREQ 100000000 /* 100 Mhz */ 46213496Scognet#define SAM9G20_PLL_B_MUL_SHIFT 16 47236989Simp#define SAM9G20_PLL_B_MUL_MASK 0x3F 48213496Scognet#define SAM9G20_PLL_B_DIV_SHIFT 0 49236989Simp#define SAM9G20_PLL_B_DIV_MASK 0xFF 50213496Scognet 51236989Simp/* 52210040Scognet * Memory map, from datasheet : 53210040Scognet * 0x00000000 - 0x0ffffffff : Internal Memories 54210040Scognet * 0x10000000 - 0x1ffffffff : Chip Select 0 55210040Scognet * 0x20000000 - 0x2ffffffff : Chip Select 1 56210040Scognet * 0x30000000 - 0x3ffffffff : Chip Select 2 57210040Scognet * 0x40000000 - 0x4ffffffff : Chip Select 3 58210040Scognet * 0x50000000 - 0x5ffffffff : Chip Select 4 59210040Scognet * 0x60000000 - 0x6ffffffff : Chip Select 5 60210040Scognet * 0x70000000 - 0x7ffffffff : Chip Select 6 61210040Scognet * 0x80000000 - 0x8ffffffff : Chip Select 7 62210040Scognet * 0x90000000 - 0xeffffffff : Undefined (Abort) 63210040Scognet * 0xf0000000 - 0xfffffffff : Peripherals 64210040Scognet */ 65210040Scognet 66210040Scognet#define AT91_CHIPSELECT_0 0x10000000 67210040Scognet#define AT91_CHIPSELECT_1 0x20000000 68210040Scognet#define AT91_CHIPSELECT_2 0x30000000 69210040Scognet#define AT91_CHIPSELECT_3 0x40000000 70210040Scognet#define AT91_CHIPSELECT_4 0x50000000 71210040Scognet#define AT91_CHIPSELECT_5 0x60000000 72210040Scognet#define AT91_CHIPSELECT_6 0x70000000 73210040Scognet#define AT91_CHIPSELECT_7 0x80000000 74210040Scognet 75210040Scognet 76210040Scognet#define AT91SAM9G20_EMAC_BASE 0xffc4000 77210040Scognet#define AT91SAM9G20_EMAC_SIZE 0x4000 78210040Scognet 79210040Scognet#define AT91SAM9G20_RSTC_BASE 0xffffd00 80213496Scognet#define AT91SAM9G20_RSTC_SIZE 0x10 81210040Scognet 82210040Scognet#define RSTC_CR 0 83210040Scognet#define RSTC_PROCRST (1 << 0) 84210040Scognet#define RSTC_PERRST (1 << 2) 85210040Scognet#define RSTC_KEY (0xa5 << 24) 86210040Scognet 87210040Scognet/* USART*/ 88210040Scognet 89213496Scognet#define AT91SAM9G20_USART_SIZE 0x4000 90210040Scognet#define AT91SAM9G20_USART0_BASE 0xffb0000 91210040Scognet#define AT91SAM9G20_USART0_PDC 0xffb0100 92213496Scognet#define AT91SAM9G20_USART0_SIZE AT91SAM9G20_USART_SIZE 93210040Scognet#define AT91SAM9G20_USART1_BASE 0xffb4000 94210040Scognet#define AT91SAM9G20_USART1_PDC 0xffb4100 95213496Scognet#define AT91SAM9G20_USART1_SIZE AT91SAM9G20_USART_SIZE 96210040Scognet#define AT91SAM9G20_USART2_BASE 0xffb8000 97210040Scognet#define AT91SAM9G20_USART2_PDC 0xffb8100 98213496Scognet#define AT91SAM9G20_USART2_SIZE AT91SAM9G20_USART_SIZE 99213496Scognet#define AT91SAM9G20_USART3_BASE 0xffd0000 100213496Scognet#define AT91SAM9G20_USART3_PDC 0xffd0100 101213496Scognet#define AT91SAM9G20_USART3_SIZE AT91SAM9G20_USART_SIZE 102213496Scognet#define AT91SAM9G20_USART4_BASE 0xffd4000 103213496Scognet#define AT91SAM9G20_USART4_PDC 0xffd4100 104213496Scognet#define AT91SAM9G20_USART4_SIZE AT91SAM9G20_USART_SIZE 105213496Scognet#define AT91SAM9G20_USART5_BASE 0xffd8000 106213496Scognet#define AT91SAM9G20_USART5_PDC 0xffd8100 107213496Scognet#define AT91SAM9G20_USART5_SIZE AT91SAM9G20_USART_SIZE 108210040Scognet 109210040Scognet/*TC*/ 110210040Scognet#define AT91SAM9G20_TC0_BASE 0xffa0000 111210040Scognet#define AT91SAM9G20_TC0_SIZE 0x4000 112210040Scognet#define AT91SAM9G20_TC0C0_BASE 0xffa0000 113210040Scognet#define AT91SAM9G20_TC0C1_BASE 0xffa0040 114210040Scognet#define AT91SAM9G20_TC0C2_BASE 0xffa0080 115210040Scognet 116210040Scognet#define AT91SAM9G20_TC1_BASE 0xffdc000 117210040Scognet#define AT91SAM9G20_TC1_SIZE 0x4000 118210040Scognet 119210040Scognet/*SPI*/ 120210040Scognet 121210040Scognet#define AT91SAM9G20_SPI0_BASE 0xffc8000 122210040Scognet 123210040Scognet#define AT91SAM9G20_SPI0_SIZE 0x4000 124210040Scognet#define AT91SAM9G20_IRQ_SPI0 12 125210040Scognet 126210040Scognet#define AT91SAM9G20_SPI1_BASE 0xffcc000 127210040Scognet#define AT91SAM9G20_SPI1_SIZE 0x4000 128210040Scognet#define AT91SAM9G20_IRQ_SPI1 13 129210040Scognet 130210040Scognet/* System Registers */ 131213496Scognet#define AT91SAM9G20_SYS_BASE 0xffff000 132213496Scognet#define AT91SAM9G20_SYS_SIZE 0x1000 133210040Scognet 134213496Scognet#define AT91SAM9G20_MATRIX_BASE 0xfffee00 135213496Scognet#define AT91SAM9G20_MATRIX_SIZE 0x1000 136213496Scognet#define AT91SAM9G20_EBICSA 0x011C 137210040Scognet 138210040Scognet#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) 139210040Scognet 140213496Scognet#define AT91SAM9G20_DBGU_BASE 0xffff200 141213496Scognet#define AT91SAM9G20_DBGU_SIZE 0x200 142210040Scognet 143210040Scognet/* 144210040Scognet * PIO 145210040Scognet */ 146210040Scognet#define AT91SAM9G20_PIOA_BASE 0xffff400 147213496Scognet#define AT91SAM9G20_PIOA_SIZE 0x200 148210040Scognet#define AT91SAM9G20_PIOB_BASE 0xffff600 149213496Scognet#define AT91SAM9G20_PIOB_SIZE 0x200 150210040Scognet#define AT91SAM9G20_PIOC_BASE 0xffff800 151213496Scognet#define AT91SAM9G20_PIOC_SIZE 0x200 152210040Scognet 153210040Scognet#define AT91RM92_PMC_BASE 0xffffc00 154210040Scognet#define AT91RM92_PMC_SIZE 0x100 155210040Scognet/* IRQs : */ 156210040Scognet/* 157236989Simp * 0: AIC 158210040Scognet * 1: System peripheral (System timer, RTC, DBGU) 159210040Scognet * 2: PIO Controller A 160210040Scognet * 3: PIO Controller B 161210040Scognet * 4: PIO Controller C 162213496Scognet * 5: ADC 163210040Scognet * 6: USART 0 164210040Scognet * 7: USART 1 165210040Scognet * 8: USART 2 166210040Scognet * 9: MMC Interface 167210040Scognet * 10: USB device port 168272163Skevlo * 11: Two-wire interface 169213496Scognet * 12: SPI 0 170213496Scognet * 13: SPI 1 171210040Scognet * 14: SSC 172213496Scognet * 15: - (reserved) 173213496Scognet * 16: - (reserved) 174210040Scognet * 17: Timer Counter 0 175210040Scognet * 18: Timer Counter 1 176210040Scognet * 19: Timer Counter 2 177210040Scognet * 20: USB Host port 178210040Scognet * 21: EMAC 179213496Scognet * 22: ISI 180213496Scognet * 23: USART 3 181213496Scognet * 24: USART 4 182213496Scognet * 25: USART 2 183213496Scognet * 26: Timer Counter 3 184213496Scognet * 27: Timer Counter 4 185213496Scognet * 28: Timer Counter 5 186213496Scognet * 29: AIC IRQ0 187213496Scognet * 30: AIC IRQ1 188213496Scognet * 31: AIC IRQ2 189210040Scognet */ 190210040Scognet 191210040Scognet#define AT91SAM9G20_IRQ_SYSTEM 1 192210040Scognet#define AT91SAM9G20_IRQ_PIOA 2 193210040Scognet#define AT91SAM9G20_IRQ_PIOB 3 194210040Scognet#define AT91SAM9G20_IRQ_PIOC 4 195210040Scognet#define AT91SAM9G20_IRQ_USART0 6 196210040Scognet#define AT91SAM9G20_IRQ_USART1 7 197210040Scognet#define AT91SAM9G20_IRQ_USART2 8 198210040Scognet#define AT91SAM9G20_IRQ_MCI 9 199210040Scognet#define AT91SAM9G20_IRQ_UDP 10 200210040Scognet#define AT91SAM9G20_IRQ_TWI 11 201210040Scognet#define AT91SAM9G20_IRQ_SPI0 12 202210040Scognet#define AT91SAM9G20_IRQ_SPI1 13 203210040Scognet#define AT91SAM9G20_IRQ_SSC0 14 204210040Scognet#define AT91SAM9G20_IRQ_SSC1 15 205210040Scognet#define AT91SAM9G20_IRQ_SSC2 16 206210040Scognet#define AT91SAM9G20_IRQ_TC0 17 207210040Scognet#define AT91SAM9G20_IRQ_TC1 18 208210040Scognet#define AT91SAM9G20_IRQ_TC2 19 209210040Scognet#define AT91SAM9G20_IRQ_UHP 20 210213496Scognet#define AT91SAM9G20_IRQ_EMAC 21 211213496Scognet#define AT91SAM9G20_IRQ_USART3 23 212213496Scognet#define AT91SAM9G20_IRQ_USART4 24 213213496Scognet#define AT91SAM9G20_IRQ_USART5 25 214210040Scognet#define AT91SAM9G20_IRQ_AICBASE 29 215210040Scognet 216213496Scognet/* Alias */ 217213496Scognet#define AT91SAM9G20_IRQ_DBGU AT91SAM9G20_IRQ_SYSTEM 218213496Scognet#define AT91SAM9G20_IRQ_PMC AT91SAM9G20_IRQ_SYSTEM 219213496Scognet#define AT91SAM9G20_IRQ_WDT AT91SAM9G20_IRQ_SYSTEM 220213496Scognet#define AT91SAM9G20_IRQ_PIT AT91SAM9G20_IRQ_SYSTEM 221213496Scognet#define AT91SAM9G20_IRQ_RSTC AT91SAM9G20_IRQ_SYSTEM 222213496Scognet#define AT91SAM9G20_IRQ_OHCI AT91SAM9G20_IRQ_UHP 223213496Scognet#define AT91SAM9G20_IRQ_NAND (-1) 224262925Simp#define AT91SAM9G20_IRQ_AIC (-1) 225213496Scognet 226213496Scognet#define AT91SAM9G20_AIC_BASE 0xffff000 227213496Scognet#define AT91SAM9G20_AIC_SIZE 0x200 228213496Scognet 229210040Scognet/* Timer */ 230210040Scognet 231210040Scognet#define AT91SAM9G20_WDT_BASE 0xffffd40 232210040Scognet#define AT91SAM9G20_WDT_SIZE 0x10 233210040Scognet 234210040Scognet#define AT91SAM9G20_PIT_BASE 0xffffd30 235234923Simp#define AT91SAM9G20_PIT_SIZE 0x10 236210040Scognet 237210040Scognet#define AT91SAM9G20_SMC_BASE 0xfffec00 238210040Scognet#define AT91SAM9G20_SMC_SIZE 0x200 239210040Scognet 240210040Scognet#define AT91SAM9G20_PMC_BASE 0xffffc00 241210040Scognet#define AT91SAM9G20_PMC_SIZE 0x100 242210040Scognet 243210040Scognet#define AT91SAM9G20_UDP_BASE 0xffa4000 244210040Scognet#define AT91SAM9G20_UDP_SIZE 0x4000 245210040Scognet 246213496Scognet#define AT91SAM9G20_MCI_BASE 0xffa8000 247213496Scognet#define AT91SAM9G20_MCI_SIZE 0x4000 248210040Scognet 249213496Scognet#define AT91SAM9G20_TWI_BASE 0xffaC000 250213496Scognet#define AT91SAM9G20_TWI_SIZE 0x4000 251210040Scognet 252213496Scognet/* XXX Needs to be carfully coordinated with 253213496Scognet * other * soc's so phyical and vm address 254213496Scognet * mapping are unique. XXX 255213496Scognet */ 256261322Simp#define AT91SAM9G20_OHCI_VA_BASE 0xdfc00000 257261322Simp#define AT91SAM9G20_OHCI_BASE 0x00500000 258261322Simp#define AT91SAM9G20_OHCI_SIZE 0x00100000 259210040Scognet 260261322Simp#define AT91SAM9G20_NAND_VA_BASE 0xe0000000 261261322Simp#define AT91SAM9G20_NAND_BASE 0x40000000 262261322Simp#define AT91SAM9G20_NAND_SIZE 0x10000000 263210040Scognet 264210040Scognet/* SDRAMC */ 265210040Scognet#define AT91SAM9G20_SDRAMC_BASE 0xfffea00 266210040Scognet#define AT91SAM9G20_SDRAMC_MR 0x00 267210040Scognet#define AT91SAM9G20_SDRAMC_MR_MODE_NORMAL 0 268210040Scognet#define AT91SAM9G20_SDRAMC_MR_MODE_NOP 1 269210040Scognet#define AT91SAM9G20_SDRAMC_MR_MODE_PRECHARGE 2 270210040Scognet#define AT91SAM9G20_SDRAMC_MR_MODE_LOAD_MODE_REGISTER 3 271210040Scognet#define AT91SAM9G20_SDRAMC_MR_MODE_REFRESH 4 272210040Scognet#define AT91SAM9G20_SDRAMC_TR 0x04 273210040Scognet#define AT91SAM9G20_SDRAMC_CR 0x08 274210040Scognet#define AT91SAM9G20_SDRAMC_CR_NC_8 0x0 275210040Scognet#define AT91SAM9G20_SDRAMC_CR_NC_9 0x1 276210040Scognet#define AT91SAM9G20_SDRAMC_CR_NC_10 0x2 277210040Scognet#define AT91SAM9G20_SDRAMC_CR_NC_11 0x3 278210040Scognet#define AT91SAM9G20_SDRAMC_CR_NC_MASK 0x00000003 279210040Scognet#define AT91SAM9G20_SDRAMC_CR_NR_11 0x0 280210040Scognet#define AT91SAM9G20_SDRAMC_CR_NR_12 0x4 281210040Scognet#define AT91SAM9G20_SDRAMC_CR_NR_13 0x8 282210040Scognet#define AT91SAM9G20_SDRAMC_CR_NR_RES 0xc 283210040Scognet#define AT91SAM9G20_SDRAMC_CR_NR_MASK 0x0000000c 284210040Scognet#define AT91SAM9G20_SDRAMC_CR_NB_2 0x00 285210040Scognet#define AT91SAM9G20_SDRAMC_CR_NB_4 0x10 286213496Scognet#define AT91SAM9G20_SDRAMC_CR_DBW_16 0x80 287210040Scognet#define AT91SAM9G20_SDRAMC_CR_NB_MASK 0x00000010 288210040Scognet#define AT91SAM9G20_SDRAMC_CR_NCAS_MASK 0x00000060 289210040Scognet#define AT91SAM9G20_SDRAMC_CR_TWR_MASK 0x00000780 290210040Scognet#define AT91SAM9G20_SDRAMC_CR_TRC_MASK 0x00007800 291210040Scognet#define AT91SAM9G20_SDRAMC_CR_TRP_MASK 0x00078000 292210040Scognet#define AT91SAM9G20_SDRAMC_CR_TRCD_MASK 0x00780000 293210040Scognet#define AT91SAM9G20_SDRAMC_CR_TRAS_MASK 0x07800000 294210040Scognet#define AT91SAM9G20_SDRAMC_CR_TXSR_MASK 0x78000000 295210040Scognet#define AT91SAM9G20_SDRAMC_HSR 0x0c 296210040Scognet#define AT91SAM9G20_SDRAMC_LPR 0x10 297210040Scognet#define AT91SAM9G20_SDRAMC_IER 0x14 298210040Scognet#define AT91SAM9G20_SDRAMC_IDR 0x18 299210040Scognet#define AT91SAM9G20_SDRAMC_IMR 0x1c 300210040Scognet#define AT91SAM9G20_SDRAMC_ISR 0x20 301210040Scognet#define AT91SAM9G20_SDRAMC_MDR 0x24 302210040Scognet 303210040Scognet#endif /* AT91SAM9G20REG_H_*/ 304210040Scognet 305