1155324Simp/*- 2155324Simp * Copyright (c) 2005 Olivier Houchard. All rights reserved. 3155324Simp * 4155324Simp * Redistribution and use in source and binary forms, with or without 5155324Simp * modification, are permitted provided that the following conditions 6155324Simp * are met: 7155324Simp * 1. Redistributions of source code must retain the above copyright 8155324Simp * notice, this list of conditions and the following disclaimer. 9155324Simp * 2. Redistributions in binary form must reproduce the above copyright 10155324Simp * notice, this list of conditions and the following disclaimer in the 11155324Simp * documentation and/or other materials provided with the distribution. 12155324Simp * 13185265Simp * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14185265Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15185265Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16185265Simp * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17185265Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18185265Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19185265Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20185265Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21185265Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22185265Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23185265Simp * SUCH DAMAGE. 24155324Simp */ 25155324Simp 26155324Simp/* $FreeBSD: releng/11.0/sys/arm/at91/at91_usartreg.h 185265 2008-11-25 00:13:26Z imp $ */ 27155324Simp 28155324Simp#ifndef AT91USARTREG_H_ 29155324Simp#define AT91USARTREG_H_ 30155324Simp 31155324Simp#define USART_CR 0x00 /* Control register */ 32157561Simp#define USART_CR_RSTRX (1UL << 2) /* Reset Receiver */ 33157561Simp#define USART_CR_RSTTX (1UL << 3) /* Reset Transmitter */ 34157561Simp#define USART_CR_RXEN (1UL << 4) /* Receiver Enable */ 35157561Simp#define USART_CR_RXDIS (1UL << 5) /* Receiver Disable */ 36157561Simp#define USART_CR_TXEN (1UL << 6) /* Transmitter Enable */ 37157561Simp#define USART_CR_TXDIS (1UL << 7) /* Transmitter Disable */ 38157561Simp#define USART_CR_RSTSTA (1UL << 8) /* Reset Status Bits */ 39157561Simp#define USART_CR_STTBRK (1UL << 9) /* Start Break */ 40157561Simp#define USART_CR_STPBRK (1UL << 10) /* Stop Break */ 41157561Simp#define USART_CR_STTTO (1UL << 11) /* Start Time-out */ 42157561Simp#define USART_CR_SENDA (1UL << 12) /* Send Address */ 43157561Simp#define USART_CR_RSTIT (1UL << 13) /* Reset Iterations */ 44157561Simp#define USART_CR_RSTNACK (1UL << 14) /* Reset Non Acknowledge */ 45157561Simp#define USART_CR_RETTO (1UL << 15) /* Rearm Time-out */ 46157561Simp#define USART_CR_DTREN (1UL << 16) /* Data Terminal ready Enable */ 47157561Simp#define USART_CR_DTRDIS (1UL << 17) /* Data Terminal ready Disable */ 48157561Simp#define USART_CR_RTSEN (1UL << 18) /* Request to Send enable */ 49157561Simp#define USART_CR_RTSDIS (1UL << 19) /* Request to Send Disable */ 50155324Simp 51155324Simp#define USART_MR 0x04 /* Mode register */ 52155324Simp#define USART_MR_MODE_NORMAL 0 /* Normal/Async/3-wire rs-232 */ 53155324Simp#define USART_MR_MODE_RS485 1 /* RS485 */ 54155324Simp#define USART_MR_MODE_HWFLOW 2 /* Hardware flow control/handshake */ 55155324Simp#define USART_MR_MODE_MODEM 3 /* Full modem protocol */ 56155324Simp#define USART_MR_MODE_ISO7816T0 4 /* ISO7816 T=0 */ 57155324Simp#define USART_MR_MODE_ISO7816T1 6 /* ISO7816 T=1 */ 58155324Simp#define USART_MR_MODE_IRDA 8 /* IrDA mode */ 59155324Simp#define USART_MR_USCLKS_MCK (0U << 4) /* use MCK for baudclock */ 60155324Simp#define USART_MR_USCLKS_MCKDIV (1U << 4) /* use MCK/DIV for baudclock */ 61155324Simp#define USART_MR_USCLKS_SCK (3U << 4) /* use SCK (ext) for baudclock */ 62155324Simp#define USART_MR_CHRL_5BITS (0U << 6) 63155324Simp#define USART_MR_CHRL_6BITS (1U << 6) 64155324Simp#define USART_MR_CHRL_7BITS (2U << 6) 65155324Simp#define USART_MR_CHRL_8BITS (3U << 6) 66155324Simp#define USART_MR_SYNC (1U << 8) /* 1 -> sync 0 -> async */ 67155324Simp#define USART_MR_PAR_EVEN (0U << 9) 68155324Simp#define USART_MR_PAR_ODD (1U << 9) 69155324Simp#define USART_MR_PAR_SPACE (2U << 9) 70155324Simp#define USART_MR_PAR_MARK (3U << 9) 71155324Simp#define USART_MR_PAR_NONE (4U << 9) 72155324Simp#define USART_MR_PAR_MULTIDROP (6U << 9) 73155324Simp#define USART_MR_NBSTOP_1 (0U << 12) 74155324Simp#define USART_MR_NBSTOP_1_5 (1U << 12) 75155324Simp#define USART_MR_NBSTOP_2 (2U << 12) 76155324Simp#define USART_MR_CHMODE_NORMAL (0U << 14) 77155324Simp#define USART_MR_CHMODE_ECHO (1U << 14) 78155324Simp#define USART_MR_CHMODE_LOOP (2U << 14) 79155324Simp#define USART_MR_CHMODE_REMLOOP (3U << 14) 80155324Simp#define USART_MR_MSBF (1U << 16) 81155324Simp#define USART_MR_MODE9 (1U << 17) 82155324Simp#define USART_MR_CKLO_SCK (1U << 18) 83155324Simp#define USART_MR_OVER16 0 84155324Simp#define USART_MR_OVER8 (1U << 19) 85155324Simp#define USART_MR_INACK (1U << 20) /* Inhibit NACK generation */ 86155324Simp#define USART_MR_DSNACK (1U << 21) /* Disable Successive NACK */ 87155324Simp#define USART_MR_MAXITERATION(x) ((x) << 24) 88155324Simp#define USART_MR_FILTER (1U << 28) /* Filters for Ir lines */ 89155324Simp 90155324Simp#define USART_IER 0x08 /* Interrupt enable register */ 91155324Simp#define USART_IDR 0x0c /* Interrupt disable register */ 92155324Simp#define USART_IMR 0x10 /* Interrupt mask register */ 93155324Simp#define USART_CSR 0x14 /* Channel status register */ 94155324Simp 95157561Simp#define USART_CSR_RXRDY (1UL << 0) /* Receiver ready */ 96157561Simp#define USART_CSR_TXRDY (1UL << 1) /* Transmitter ready */ 97157561Simp#define USART_CSR_RXBRK (1UL << 2) /* Break received */ 98157561Simp#define USART_CSR_ENDRX (1UL << 3) /* End of Transfer RX from PDC */ 99157561Simp#define USART_CSR_ENDTX (1UL << 4) /* End of Transfer TX from PDC */ 100157561Simp#define USART_CSR_OVRE (1UL << 5) /* Overrun error */ 101157561Simp#define USART_CSR_FRAME (1UL << 6) /* Framing error */ 102157561Simp#define USART_CSR_PARE (1UL << 7) /* Parity Error */ 103157561Simp#define USART_CSR_TIMEOUT (1UL << 8) /* Timeout since start-timeout */ 104157561Simp#define USART_CSR_TXEMPTY (1UL << 9) /* Transmitter empty */ 105157561Simp#define USART_CSR_ITERATION (1UL << 10) /* max repetitions since RSIT */ 106157561Simp#define USART_CSR_TXBUFE (1UL << 11) /* Buffer empty from PDC */ 107157561Simp#define USART_CSR_RXBUFF (1UL << 12) /* Buffer full from PDC */ 108157561Simp#define USART_CSR_NACK (1UL << 13) /* NACK since last RSTNACK */ 109157561Simp#define USART_CSR_RIIC (1UL << 16) /* RI delta since last csr read */ 110157561Simp#define USART_CSR_DSRIC (1UL << 17) /* DSR delta */ 111157561Simp#define USART_CSR_DCDIC (1UL << 18) /* DCD delta */ 112157561Simp#define USART_CSR_CTSIC (1UL << 19) /* CTS delta */ 113157561Simp#define USART_CSR_RI (1UL << 20) /* RI status */ 114157561Simp#define USART_CSR_DSR (1UL << 21) /* DSR status */ 115157561Simp#define USART_CSR_DCD (1UL << 22) /* DCD status */ 116157561Simp#define USART_CSR_CTS (1UL << 23) /* CTS status */ 117155324Simp 118155324Simp#define USART_RHR 0x18 /* Receiver holding register */ 119155324Simp#define USART_THR 0x1c /* Transmitter holding register */ 120155324Simp#define USART_BRGR 0x20 /* Baud rate generator register */ 121155324Simp#define USART_RTOR 0x24 /* Receiver time-out register */ 122155324Simp#define USART_TTR 0x28 /* Transmitter timeguard register */ 123155324Simp/* 0x2c to 0x3c reserved */ 124155324Simp#define USART_FDRR 0x40 /* FI DI ratio register */ 125155324Simp#define USART_NER 0x44 /* Number of errors register */ 126155324Simp/* 0x48 reserved */ 127155324Simp#define USART_IFR 0x48 /* IrDA filter register */ 128155324Simp 129155324Simp#endif /* AT91RM92REG_H_ */ 130