1119815Smarcel/*- 2119815Smarcel * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3119815Smarcel * 4119815Smarcel * Redistribution and use in source and binary forms, with or without 5119815Smarcel * modification, are permitted provided that the following conditions 6119815Smarcel * are met: 7119815Smarcel * 1. Redistributions of source code must retain the above copyright 8119815Smarcel * notice, this list of conditions and the following disclaimer. 9119815Smarcel * 2. Redistributions in binary form must reproduce the above copyright 10119815Smarcel * notice, this list of conditions and the following disclaimer in the 11119815Smarcel * documentation and/or other materials provided with the distribution. 12119815Smarcel * 13119815Smarcel * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14119815Smarcel * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15119815Smarcel * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16119815Smarcel * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17119815Smarcel * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18119815Smarcel * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19119815Smarcel * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20119815Smarcel * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21119815Smarcel * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22119815Smarcel * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23119815Smarcel * SUCH DAMAGE. 24119815Smarcel */ 25119815Smarcel 26119815Smarcel/* $FreeBSD: releng/11.0/sys/arm/at91/at91_twireg.h 234291 2012-04-14 17:09:38Z marius $ */ 27119815Smarcel 28119815Smarcel#ifndef ARM_AT91_AT91_TWIREG_H 29119815Smarcel#define ARM_AT91_AT91_TWIREG_H 30119815Smarcel 31119815Smarcel#define TWI_CR 0x00 /* TWI Control Register */ 32119815Smarcel#define TWI_MMR 0x04 /* TWI Master Mode Register */ 33119815Smarcel#define TWI_SMR 0x08 /* TWI Master Mode Register */ 34119815Smarcel#define TWI_IADR 0x0c /* TWI Internal Address Register */ 35119815Smarcel#define TWI_CWGR 0x10 /* TWI Clock Waveform Generator Reg */ 36119815Smarcel /* 0x14 reserved */ 37119815Smarcel /* 0x18 reserved */ 38119815Smarcel /* 0x1c reserved */ 39119815Smarcel#define TWI_SR 0x20 /* TWI Status Register */ 40119815Smarcel#define TWI_IER 0x24 /* TWI Interrupt Enable Register */ 41119815Smarcel#define TWI_IDR 0x28 /* TWI Interrupt Disable Register */ 42119815Smarcel#define TWI_IMR 0x2c /* TWI Interrupt Mask Register */ 43119815Smarcel#define TWI_RHR 0x30 /* TWI Receiver Holding Register */ 44119815Smarcel#define TWI_THR 0x34 /* TWI Transmit Holding Register */ 45119815Smarcel 46119815Smarcel/* TWI_CR */ 47119815Smarcel#define TWI_CR_START (1U << 0) /* Send a start */ 48119815Smarcel#define TWI_CR_STOP (1U << 1) /* Send a stop */ 49119815Smarcel#define TWI_CR_MSEN (1U << 2) /* Master Transfer Enable */ 50119815Smarcel#define TWI_CR_MSDIS (1U << 3) /* Master Transfer Disable */ 51119815Smarcel#define TWI_CR_SVEN (1U << 4) /* Slave Transfer Enable */ 52119815Smarcel#define TWI_CR_SVDIS (1U << 5) /* Slave Transfer Disable */ 53119815Smarcel#define TWI_CR_SWRST (1U << 7) /* Software Reset */ 54119815Smarcel 55119815Smarcel/* TWI_MMR */ 56119815Smarcel/* TWI_SMR */ 57119815Smarcel#define TWI_MMR_IADRSZ(n) ((n) << 8) /* Set size of transfer */ 58120452Smarcel#define TWI_MMR_MWRITE 0U /* Master Read Direction */ 59119815Smarcel#define TWI_MMR_MREAD (1U << 12) /* Master Read Direction */ 60119815Smarcel#define TWI_MMR_DADR(n) ((n) << 15) /* Device Address */ 61119815Smarcel 62119866Smarcel/* TWI_CWGR */ 63119866Smarcel#define TWI_CWGR_CKDIV(x) ((x) << 16) /* Clock Divider */ 64119866Smarcel#define TWI_CWGR_CHDIV(x) ((x) << 8) /* Clock High Divider */ 65119866Smarcel#define TWI_CWGR_CLDIV(x) ((x) << 0) /* Clock Low Divider */ 66119866Smarcel#define TWI_CWGR_DIV(rate) \ 67119866Smarcel (at91_is_sam9() || at91_is_sam9xe() ? \ 68119866Smarcel ((at91_master_clock / (4 * (rate))) - 3) : \ 69119815Smarcel ((at91_master_clock / (4 * (rate))) - 2)) 70119815Smarcel 71120009Stmm/* TWI_SR */ 72119815Smarcel/* TWI_IER */ 73119815Smarcel/* TWI_IDR */ 74120452Smarcel/* TWI_IMR */ 75119815Smarcel#define TWI_SR_TXCOMP (1U << 0) /* Transmission Completed */ 76119815Smarcel#define TWI_SR_RXRDY (1U << 1) /* Receive Holding Register Ready */ 77119815Smarcel#define TWI_SR_TXRDY (1U << 2) /* Transmit Holding Register Ready */ 78119815Smarcel#define TWI_SR_SVREAD (1U << 3) /* Slave Read */ 79119815Smarcel#define TWI_SR_SVACC (1U << 4) /* Slave Access */ 80119815Smarcel#define TWI_SR_GCACC (1U << 5) /* General Call Access */ 81119815Smarcel#define TWI_SR_OVRE (1U << 6) /* Overrun error */ 82119815Smarcel#define TWI_SR_UNRE (1U << 7) /* Underrun Error */ 83119815Smarcel#define TWI_SR_NACK (1U << 8) /* Not Acknowledged */ 84119815Smarcel#define TWI_SR_ARBLST (1U << 9) /* Arbitration Lost */ 85119815Smarcel 86119815Smarcel#endif /* ARM_AT91_AT91_TWIREG_H */ 87119815Smarcel