1163517Simp/*- 2163517Simp * Copyright (c) 2006 Berndt Walter. All rights reserved. 3163517Simp * Copyright (c) 2006 M. Warner Losh. All rights reserved. 4163517Simp * 5163517Simp * Redistribution and use in source and binary forms, with or without 6163517Simp * modification, are permitted provided that the following conditions 7163517Simp * are met: 8163517Simp * 1. Redistributions of source code must retain the above copyright 9163517Simp * notice, this list of conditions and the following disclaimer. 10163517Simp * 2. Redistributions in binary form must reproduce the above copyright 11163517Simp * notice, this list of conditions and the following disclaimer in the 12163517Simp * documentation and/or other materials provided with the distribution. 13163517Simp * 14185265Simp * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15185265Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16185265Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17185265Simp * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18185265Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19185265Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20185265Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21185265Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22185265Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23185265Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24185265Simp * SUCH DAMAGE. 25163517Simp */ 26163517Simp 27163517Simp/* $FreeBSD: releng/11.0/sys/arm/at91/at91_mcireg.h 270006 2014-08-14 23:17:33Z imp $ */ 28163517Simp 29172739Simp#ifndef ARM_AT91_AT91_MCIREG_H 30172739Simp#define ARM_AT91_AT91_MCIREG_H 31163517Simp 32163517Simp#define MMC_MAX 30 33163517Simp 34163517Simp#define MCI_CR 0x00 /* MCI Control Register */ 35163517Simp#define MCI_MR 0x04 /* MCI Mode Register */ 36163517Simp#define MCI_DTOR 0x08 /* MCI Data Timeout Register */ 37163517Simp#define MCI_SDCR 0x0c /* MCI SD Card Register */ 38163517Simp#define MCI_ARGR 0x10 /* MCI Argument Register */ 39163517Simp#define MCI_CMDR 0x14 /* MCI Command Register */ 40163517Simp#define MCI_RSPR 0x20 /* MCI Response Registers - 4 of them */ 41163517Simp#define MCI_RDR 0x30 /* MCI Receive Data Register */ 42163517Simp#define MCI_TDR 0x34 /* MCI Transmit Data Register */ 43163517Simp#define MCI_SR 0x40 /* MCI Status Register */ 44163517Simp#define MCI_IER 0x44 /* MCI Interrupt Enable Register */ 45163517Simp#define MCI_IDR 0x48 /* MCI Interrupt Disable Register */ 46163517Simp#define MCI_IMR 0x4c /* MCI Interrupt Mask Register */ 47163517Simp 48163517Simp/* -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- */ 49163517Simp#define MCI_CR_MCIEN (0x1u << 0) /* (MCI) Multimedia Interface Enable */ 50163517Simp#define MCI_CR_MCIDIS (0x1u << 1) /* (MCI) Multimedia Interface Disable */ 51163517Simp#define MCI_CR_PWSEN (0x1u << 2) /* (MCI) Power Save Mode Enable */ 52163517Simp#define MCI_CR_PWSDIS (0x1u << 3) /* (MCI) Power Save Mode Disable */ 53163517Simp#define MCI_CR_SWRST (0x1u << 7) /* (MCI) Software Reset */ 54163517Simp/* -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- */ 55163517Simp#define MCI_MR_CLKDIV (0xffu << 0) /* (MCI) Clock Divider */ 56163517Simp#define MCI_MR_PWSDIV (0x3fu << 8) /* (MCI) Power Saving Divider */ 57234560Smarius#define MCI_MR_RDPROOF (0x1u << 11) /* (MCI) Read Proof Enable */ 58234560Smarius#define MCI_MR_WRPROOF (0x1u << 12) /* (MCI) Write Proof Enable */ 59234560Smarius#define MCI_MR_PDCFBYTE (0x1u << 13) /* (MCI) PDC Force Byte Transfer */ 60163517Simp#define MCI_MR_PDCPADV (0x1u << 14) /* (MCI) PDC Padding Value */ 61163517Simp#define MCI_MR_PDCMODE (0x1u << 15) /* (MCI) PDC Oriented Mode */ 62163517Simp#define MCI_MR_BLKLEN 0x3fff0000ul /* (MCI) Data Block Length */ 63163517Simp/* -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- */ 64163517Simp#define MCI_DTOR_DTOCYC (0xfu << 0) /* (MCI) Data Timeout Cycle Number */ 65163517Simp#define MCI_DTOR_DTOMUL (0x7u << 4) /* (MCI) Data Timeout Multiplier */ 66163517Simp#define MCI_DTOR_DTOMUL_1 (0x0u << 4) /* (MCI) DTOCYC x 1 */ 67163517Simp#define MCI_DTOR_DTOMUL_16 (0x1u << 4) /* (MCI) DTOCYC x 16 */ 68163517Simp#define MCI_DTOR_DTOMUL_128 (0x2u << 4) /* (MCI) DTOCYC x 128 */ 69163517Simp#define MCI_DTOR_DTOMUL_256 (0x3u << 4) /* (MCI) DTOCYC x 256 */ 70163517Simp#define MCI_DTOR_DTOMUL_1k (0x4u << 4) /* (MCI) DTOCYC x 1024 */ 71163517Simp#define MCI_DTOR_DTOMUL_4k (0x5u << 4) /* (MCI) DTOCYC x 4096 */ 72163517Simp#define MCI_DTOR_DTOMUL_64k (0x6u << 4) /* (MCI) DTOCYC x 65536 */ 73163517Simp#define MCI_DTOR_DTOMUL_1M (0x7u << 4) /* (MCI) DTOCYC x 1048576 */ 74163517Simp/* -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- */ 75163517Simp#define MCI_SDCR_SDCSEL (0x1u << 0) /* (MCI) SD Card Selector */ 76163517Simp#define MCI_SDCR_SDCBUS (0x1u << 7) /* (MCI) SD Card Bus Width */ 77163517Simp/* -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- */ 78163517Simp#define MCI_CMDR_CMDNB (0x1Fu << 0) /* (MCI) Command Number */ 79163517Simp#define MCI_CMDR_RSPTYP (0x3u << 6) /* (MCI) Response Type */ 80163517Simp#define MCI_CMDR_RSPTYP_NO (0x0u << 6) /* (MCI) No response */ 81163517Simp#define MCI_CMDR_RSPTYP_48 (0x1u << 6) /* (MCI) 48-bit response */ 82163517Simp#define MCI_CMDR_RSPTYP_136 (0x2u << 6) /* (MCI) 136-bit response */ 83163517Simp#define MCI_CMDR_SPCMD (0x7u << 8) /* (MCI) Special CMD */ 84163517Simp#define MCI_CMDR_SPCMD_NONE (0x0u << 8) /* (MCI) Not a special CMD */ 85163517Simp#define MCI_CMDR_SPCMD_INIT (0x1u << 8) /* (MCI) Initialization CMD */ 86163517Simp#define MCI_CMDR_SPCMD_SYNC (0x2u << 8) /* (MCI) Synchronized CMD */ 87163517Simp#define MCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /* (MCI) Interrupt command */ 88163517Simp#define MCI_CMDR_SPCMD_IT_REP (0x5u << 8) /* (MCI) Interrupt response */ 89163517Simp#define MCI_CMDR_OPDCMD (0x1u << 11) /* (MCI) Open Drain Command */ 90163517Simp#define MCI_CMDR_MAXLAT (0x1u << 12) /* (MCI) Maximum Latency for Command to respond */ 91163517Simp#define MCI_CMDR_TRCMD (0x3u << 16) /* (MCI) Transfer CMD */ 92163517Simp#define MCI_CMDR_TRCMD_NO (0x0u << 16) /* (MCI) No transfer */ 93163517Simp#define MCI_CMDR_TRCMD_START (0x1u << 16) /* (MCI) Start transfer */ 94163517Simp#define MCI_CMDR_TRCMD_STOP (0x2u << 16) /* (MCI) Stop transfer */ 95163517Simp#define MCI_CMDR_TRDIR (0x1u << 18) /* (MCI) Transfer Direction */ 96163517Simp#define MCI_CMDR_TRTYP (0x3u << 19) /* (MCI) Transfer Type */ 97163517Simp#define MCI_CMDR_TRTYP_BLOCK (0x0u << 19) /* (MCI) Block Transfer type */ 98163517Simp#define MCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /* (MCI) Multiple Block transfer type */ 99163517Simp#define MCI_CMDR_TRTYP_STREAM (0x2u << 19) /* (MCI) Stream transfer type */ 100163517Simp/* -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- */ 101163517Simp#define MCI_SR_CMDRDY (0x1u << 0) /* (MCI) Command Ready flag */ 102163517Simp#define MCI_SR_RXRDY (0x1u << 1) /* (MCI) RX Ready flag */ 103163517Simp#define MCI_SR_TXRDY (0x1u << 2) /* (MCI) TX Ready flag */ 104163517Simp#define MCI_SR_BLKE (0x1u << 3) /* (MCI) Data Block Transfer Ended flag */ 105163517Simp#define MCI_SR_DTIP (0x1u << 4) /* (MCI) Data Transfer in Progress flag */ 106163517Simp#define MCI_SR_NOTBUSY (0x1u << 5) /* (MCI) Data Line Not Busy flag */ 107163517Simp#define MCI_SR_ENDRX (0x1u << 6) /* (MCI) End of RX Buffer flag */ 108163517Simp#define MCI_SR_ENDTX (0x1u << 7) /* (MCI) End of TX Buffer flag */ 109163517Simp#define MCI_SR_RXBUFF (0x1u << 14) /* (MCI) RX Buffer Full flag */ 110163517Simp#define MCI_SR_TXBUFE (0x1u << 15) /* (MCI) TX Buffer Empty flag */ 111163517Simp#define MCI_SR_RINDE (0x1u << 16) /* (MCI) Response Index Error flag */ 112163517Simp#define MCI_SR_RDIRE (0x1u << 17) /* (MCI) Response Direction Error flag */ 113163517Simp#define MCI_SR_RCRCE (0x1u << 18) /* (MCI) Response CRC Error flag */ 114163517Simp#define MCI_SR_RENDE (0x1u << 19) /* (MCI) Response End Bit Error flag */ 115163517Simp#define MCI_SR_RTOE (0x1u << 20) /* (MCI) Response Time-out Error flag */ 116163517Simp#define MCI_SR_DCRCE (0x1u << 21) /* (MCI) data CRC Error flag */ 117163517Simp#define MCI_SR_DTOE (0x1u << 22) /* (MCI) Data timeout Error flag */ 118163517Simp#define MCI_SR_OVRE (0x1u << 30) /* (MCI) Overrun flag */ 119163517Simp#define MCI_SR_UNRE (0x1u << 31) /* (MCI) Underrun flag */ 120163517Simp 121270006Simp/* TXRDY,DTIP,ENDTX,TXBUFE,RTOE */ 122270006Simp 123270006Simp#define MCI_SR_BITSTRING \ 124270006Simp "\020" \ 125270006Simp "\001CMDRDY" \ 126270006Simp "\002RXRDY" \ 127270006Simp "\003TXRDY" \ 128270006Simp "\004BLKE" \ 129270006Simp "\005DTIP" \ 130270006Simp "\006NOTBUSY" \ 131270006Simp "\007ENDRX" \ 132270006Simp "\010ENDTX" \ 133270006Simp "\017RXBUFF" \ 134270006Simp "\020TXBUFE" \ 135270006Simp "\021RINDE" \ 136270006Simp "\022RDIRE" \ 137270006Simp "\023RCRCE" \ 138270006Simp "\024RENDE" \ 139270006Simp "\025RTOE" \ 140270006Simp "\026DCRCE" \ 141270006Simp "\027DTOE" \ 142270006Simp "\037OVRE" \ 143270006Simp "\040UNRE" 144270006Simp 145163517Simp/* -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- */ 146163517Simp/* -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- */ 147163517Simp/* -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- */ 148163517Simp 149163517Simp#define MCI_SR_ERROR (MCI_SR_UNRE | MCI_SR_OVRE | MCI_SR_DTOE | \ 150163517Simp MCI_SR_DCRCE | MCI_SR_RTOE | MCI_SR_RENDE | \ 151163517Simp MCI_SR_RCRCE | MCI_SR_RDIRE | MCI_SR_RINDE) 152163517Simp 153163517Simp#define AT91C_BUS_WIDTH_1BIT 0x00 154163517Simp#define AT91C_BUS_WIDTH_4BITS 0x02 155163517Simp 156172739Simp#endif /* ARM_AT91_AT91_MCIREG_H */ 157