1271431Sbr/*-
2271431Sbr * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
3271431Sbr * All rights reserved.
4271431Sbr *
5271431Sbr * This software was developed by SRI International and the University of
6271431Sbr * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7271431Sbr * ("CTSRD"), as part of the DARPA CRASH research programme.
8271431Sbr *
9271431Sbr * Redistribution and use in source and binary forms, with or without
10271431Sbr * modification, are permitted provided that the following conditions
11271431Sbr * are met:
12271431Sbr * 1. Redistributions of source code must retain the above copyright
13271431Sbr *    notice, this list of conditions and the following disclaimer.
14271431Sbr * 2. Redistributions in binary form must reproduce the above copyright
15271431Sbr *    notice, this list of conditions and the following disclaimer in the
16271431Sbr *    documentation and/or other materials provided with the distribution.
17271431Sbr *
18271431Sbr * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19271431Sbr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20271431Sbr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21271431Sbr * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22271431Sbr * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23271431Sbr * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24271431Sbr * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25271431Sbr * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26271431Sbr * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27271431Sbr * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28271431Sbr * SUCH DAMAGE.
29271431Sbr *
30271431Sbr * $FreeBSD: releng/11.0/sys/arm/altera/socfpga/socfpga_rstmgr.h 271431 2014-09-11 18:12:28Z br $
31271431Sbr */
32271431Sbr
33271431Sbr#define	RSTMGR_STAT		0x0	/* Status */
34271431Sbr#define	RSTMGR_CTRL		0x4	/* Control */
35271431Sbr#define	 CTRL_SWWARMRSTREQ	(1 << 1) /* Trigger warm reset */
36271431Sbr#define	RSTMGR_COUNTS		0x8	/* Reset Cycles Count */
37271431Sbr#define	RSTMGR_MPUMODRST	0x10	/* MPU Module Reset */
38271431Sbr#define	RSTMGR_PERMODRST	0x14	/* Peripheral Module Reset */
39271431Sbr#define	RSTMGR_PER2MODRST	0x18	/* Peripheral 2 Module Reset */
40271431Sbr#define	RSTMGR_BRGMODRST	0x1C	/* Bridge Module Reset */
41271431Sbr#define	 BRGMODRST_FPGA2HPS	(1 << 2)
42271431Sbr#define	 BRGMODRST_LWHPS2FPGA	(1 << 1)
43271431Sbr#define	 BRGMODRST_HPS2FPGA	(1 << 0)
44271431Sbr#define	RSTMGR_MISCMODRST	0x20	/* Miscellaneous Module Reset */
45271431Sbr
46271431Sbrint rstmgr_warmreset(void);
47