1271186Sbr/*- 2271186Sbr * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3271186Sbr * All rights reserved. 4271186Sbr * 5271186Sbr * This software was developed by SRI International and the University of 6271186Sbr * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7271186Sbr * ("CTSRD"), as part of the DARPA CRASH research programme. 8271186Sbr * 9271186Sbr * Redistribution and use in source and binary forms, with or without 10271186Sbr * modification, are permitted provided that the following conditions 11271186Sbr * are met: 12271186Sbr * 1. Redistributions of source code must retain the above copyright 13271186Sbr * notice, this list of conditions and the following disclaimer. 14271186Sbr * 2. Redistributions in binary form must reproduce the above copyright 15271186Sbr * notice, this list of conditions and the following disclaimer in the 16271186Sbr * documentation and/or other materials provided with the distribution. 17271186Sbr * 18271186Sbr * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19271186Sbr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20271186Sbr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21271186Sbr * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22271186Sbr * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23271186Sbr * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24271186Sbr * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25271186Sbr * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26271186Sbr * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27271186Sbr * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28271186Sbr * SUCH DAMAGE. 29271186Sbr * 30271186Sbr * $FreeBSD: releng/11.0/sys/arm/altera/socfpga/socfpga_common.h 271200 2014-09-06 18:08:21Z br $ 31271186Sbr */ 32271186Sbr 33271200Sbr#define READ4(_sc, _reg) bus_read_4((_sc)->res[0], _reg) 34271200Sbr#define READ2(_sc, _reg) bus_read_2((_sc)->res[0], _reg) 35271200Sbr#define READ1(_sc, _reg) bus_read_1((_sc)->res[0], _reg) 36271200Sbr#define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->res[0], _reg, _val) 37271200Sbr#define WRITE2(_sc, _reg, _val) bus_write_2((_sc)->res[0], _reg, _val) 38271200Sbr#define WRITE1(_sc, _reg, _val) bus_write_1((_sc)->res[0], _reg, _val) 39