1299084Sjmcneill/*- 2299084Sjmcneill * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca> 3299084Sjmcneill * All rights reserved. 4299084Sjmcneill * 5299084Sjmcneill * Redistribution and use in source and binary forms, with or without 6299084Sjmcneill * modification, are permitted provided that the following conditions 7299084Sjmcneill * are met: 8299084Sjmcneill * 1. Redistributions of source code must retain the above copyright 9299084Sjmcneill * notice, this list of conditions and the following disclaimer. 10299084Sjmcneill * 2. Redistributions in binary form must reproduce the above copyright 11299084Sjmcneill * notice, this list of conditions and the following disclaimer in the 12299084Sjmcneill * documentation and/or other materials provided with the distribution. 13299084Sjmcneill * 14299084Sjmcneill * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15299084Sjmcneill * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16299084Sjmcneill * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17299084Sjmcneill * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18299084Sjmcneill * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 19299084Sjmcneill * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20299084Sjmcneill * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 21299084Sjmcneill * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22299084Sjmcneill * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23299084Sjmcneill * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24299084Sjmcneill * SUCH DAMAGE. 25299084Sjmcneill * 26299084Sjmcneill * $FreeBSD: releng/11.0/sys/arm/allwinner/if_awgreg.h 299084 2016-05-04 20:06:20Z jmcneill $ 27299084Sjmcneill */ 28299084Sjmcneill 29299084Sjmcneill/* 30299084Sjmcneill * Allwinner Gigabit Ethernet 31299084Sjmcneill */ 32299084Sjmcneill 33299084Sjmcneill#ifndef __IF_AWGREG_H__ 34299084Sjmcneill#define __IF_AWGREG_H__ 35299084Sjmcneill 36299084Sjmcneill#define EMAC_BASIC_CTL_0 0x00 37299084Sjmcneill#define BASIC_CTL_SPEED (0x3 << 2) 38299084Sjmcneill#define BASIC_CTL_SPEED_SHIFT 2 39299084Sjmcneill#define BASIC_CTL_SPEED_1000 0 40299084Sjmcneill#define BASIC_CTL_SPEED_10 2 41299084Sjmcneill#define BASIC_CTL_SPEED_100 3 42299084Sjmcneill#define BASIC_CTL_LOOPBACK (1 << 1) 43299084Sjmcneill#define BASIC_CTL_DUPLEX (1 << 0) 44299084Sjmcneill#define EMAC_BASIC_CTL_1 0x04 45299084Sjmcneill#define BASIC_CTL_BURST_LEN (0x3f << 24) 46299084Sjmcneill#define BASIC_CTL_BURST_LEN_SHIFT 24 47299084Sjmcneill#define BASIC_CTL_RX_TX_PRI (1 << 1) 48299084Sjmcneill#define BASIC_CTL_SOFT_RST (1 << 0) 49299084Sjmcneill#define EMAC_INT_STA 0x08 50299084Sjmcneill#define RX_BUF_UA_INT (1 << 10) 51299084Sjmcneill#define RX_INT (1 << 8) 52299084Sjmcneill#define TX_UNDERFLOW_INT (1 << 4) 53299084Sjmcneill#define TX_BUF_UA_INT (1 << 2) 54299084Sjmcneill#define TX_DMA_STOPPED_INT (1 << 1) 55299084Sjmcneill#define TX_INT (1 << 0) 56299084Sjmcneill#define EMAC_INT_EN 0x0c 57299084Sjmcneill#define RX_BUF_UA_INT_EN (1 << 10) 58299084Sjmcneill#define RX_INT_EN (1 << 8) 59299084Sjmcneill#define TX_UNDERFLOW_INT_EN (1 << 4) 60299084Sjmcneill#define TX_BUF_UA_INT_EN (1 << 2) 61299084Sjmcneill#define TX_DMA_STOPPED_INT_EN (1 << 1) 62299084Sjmcneill#define TX_INT_EN (1 << 0) 63299084Sjmcneill#define EMAC_TX_CTL_0 0x10 64299084Sjmcneill#define TX_EN (1 << 31) 65299084Sjmcneill#define EMAC_TX_CTL_1 0x14 66299084Sjmcneill#define TX_DMA_START (1 << 31) 67299084Sjmcneill#define TX_DMA_EN (1 << 30) 68299084Sjmcneill#define TX_MD (1 << 1) 69299084Sjmcneill#define FLUSH_TX_FIFO (1 << 0) 70299084Sjmcneill#define EMAC_TX_FLOW_CTL 0x1c 71299084Sjmcneill#define PAUSE_TIME (0xffff << 4) 72299084Sjmcneill#define PAUSE_TIME_SHIFT 4 73299084Sjmcneill#define TX_FLOW_CTL_EN (1 << 0) 74299084Sjmcneill#define EMAC_TX_DMA_LIST 0x20 75299084Sjmcneill#define EMAC_RX_CTL_0 0x24 76299084Sjmcneill#define RX_EN (1 << 31) 77299084Sjmcneill#define JUMBO_FRM_EN (1 << 29) 78299084Sjmcneill#define STRIP_FCS (1 << 28) 79299084Sjmcneill#define CHECK_CRC (1 << 27) 80299084Sjmcneill#define RX_FLOW_CTL_EN (1 << 16) 81299084Sjmcneill#define EMAC_RX_CTL_1 0x28 82299084Sjmcneill#define RX_DMA_START (1 << 31) 83299084Sjmcneill#define RX_DMA_EN (1 << 30) 84299084Sjmcneill#define RX_MD (1 << 1) 85299084Sjmcneill#define EMAC_RX_DMA_LIST 0x34 86299084Sjmcneill#define EMAC_RX_FRM_FLT 0x38 87299084Sjmcneill#define DIS_ADDR_FILTER (1 << 31) 88299084Sjmcneill#define DIS_BROADCAST (1 << 17) 89299084Sjmcneill#define RX_ALL_MULTICAST (1 << 16) 90299084Sjmcneill#define CTL_FRM_FILTER (0x3 << 12) 91299084Sjmcneill#define CTL_FRM_FILTER_SHIFT 12 92299084Sjmcneill#define HASH_MULTICAST (1 << 9) 93299084Sjmcneill#define HASH_UNICAST (1 << 8) 94299084Sjmcneill#define SA_FILTER_EN (1 << 6) 95299084Sjmcneill#define SA_INV_FILTER (1 << 5) 96299084Sjmcneill#define DA_INV_FILTER (1 << 4) 97299084Sjmcneill#define FLT_MD (1 << 1) 98299084Sjmcneill#define RX_ALL (1 << 0) 99299084Sjmcneill#define EMAC_RX_HASH_0 0x40 100299084Sjmcneill#define EMAC_RX_HASH_1 0x44 101299084Sjmcneill#define EMAC_MII_CMD 0x48 102299084Sjmcneill#define MDC_DIV_RATIO_M (0x7 << 20) 103299084Sjmcneill#define MDC_DIV_RATIO_M_16 0 104299084Sjmcneill#define MDC_DIV_RATIO_M_32 1 105299084Sjmcneill#define MDC_DIV_RATIO_M_64 2 106299084Sjmcneill#define MDC_DIV_RATIO_M_128 3 107299084Sjmcneill#define MDC_DIV_RATIO_M_SHIFT 20 108299084Sjmcneill#define PHY_ADDR (0x1f << 12) 109299084Sjmcneill#define PHY_ADDR_SHIFT 12 110299084Sjmcneill#define PHY_REG_ADDR (0x1f << 4) 111299084Sjmcneill#define PHY_REG_ADDR_SHIFT 4 112299084Sjmcneill#define MII_WR (1 << 1) 113299084Sjmcneill#define MII_BUSY (1 << 0) 114299084Sjmcneill#define EMAC_MII_DATA 0x4c 115299084Sjmcneill#define EMAC_ADDR_HIGH(n) (0x50 + (n) * 8) 116299084Sjmcneill#define EMAC_ADDR_LOW(n) (0x54 + (n) * 8) 117299084Sjmcneill#define EMAC_TX_DMA_STA 0x80 118299084Sjmcneill#define EMAC_TX_DMA_CUR_DESC 0x84 119299084Sjmcneill#define EMAC_TX_DMA_CUR_BUF 0x88 120299084Sjmcneill#define EMAC_RX_DMA_STA 0xc0 121299084Sjmcneill#define EMAC_RX_DMA_CUR_DESC 0xc4 122299084Sjmcneill#define EMAC_RX_DMA_CUR_BUF 0xc8 123299084Sjmcneill#define EMAC_RGMII_STA 0xd0 124299084Sjmcneill 125299084Sjmcneillstruct emac_desc { 126299084Sjmcneill uint32_t status; 127299084Sjmcneill/* Transmit */ 128299084Sjmcneill#define TX_DESC_CTL (1 << 31) 129299084Sjmcneill#define TX_HEADER_ERR (1 << 16) 130299084Sjmcneill#define TX_LENGTH_ERR (1 << 14) 131299084Sjmcneill#define TX_PAYLOAD_ERR (1 << 12) 132299084Sjmcneill#define TX_CRS_ERR (1 << 10) 133299084Sjmcneill#define TX_COL_ERR_0 (1 << 9) 134299084Sjmcneill#define TX_COL_ERR_1 (1 << 8) 135299084Sjmcneill#define TX_COL_CNT (0xf << 3) 136299084Sjmcneill#define TX_COL_CNT_SHIFT 3 137299084Sjmcneill#define TX_DEFER_ERR (1 << 2) 138299084Sjmcneill#define TX_UNDERFLOW_ERR (1 << 1) 139299084Sjmcneill#define TX_DEFER (1 << 0) 140299084Sjmcneill/* Receive */ 141299084Sjmcneill#define RX_DESC_CTL (1 << 31) 142299084Sjmcneill#define RX_DAF_FAIL (1 << 30) 143299084Sjmcneill#define RX_FRM_LEN (0x3fff << 16) 144299084Sjmcneill#define RX_FRM_LEN_SHIFT 16 145299084Sjmcneill#define RX_NO_ENOUGH_BUF_ERR (1 << 14) 146299084Sjmcneill#define RX_SAF_FAIL (1 << 13) 147299084Sjmcneill#define RX_OVERFLOW_ERR (1 << 11) 148299084Sjmcneill#define RX_FIR_DESC (1 << 9) 149299084Sjmcneill#define RX_LAST_DESC (1 << 8) 150299084Sjmcneill#define RX_HEADER_ERR (1 << 7) 151299084Sjmcneill#define RX_COL_ERR (1 << 6) 152299084Sjmcneill#define RX_FRM_TYPE (1 << 5) 153299084Sjmcneill#define RX_LENGTH_ERR (1 << 4) 154299084Sjmcneill#define RX_PHY_ERR (1 << 3) 155299084Sjmcneill#define RX_CRC_ERR (1 << 1) 156299084Sjmcneill#define RX_PAYLOAD_ERR (1 << 0) 157299084Sjmcneill 158299084Sjmcneill uint32_t size; 159299084Sjmcneill/* Transmit */ 160299084Sjmcneill#define TX_INT_CTL (1 << 31) 161299084Sjmcneill#define TX_LAST_DESC (1 << 30) 162299084Sjmcneill#define TX_FIR_DESC (1 << 29) 163299084Sjmcneill#define TX_CHECKSUM_CTL (0x3 << 27) 164299084Sjmcneill#define TX_CHECKSUM_CTL_IP 1 165299084Sjmcneill#define TX_CHECKSUM_CTL_NO_PSE 2 166299084Sjmcneill#define TX_CHECKSUM_CTL_FULL 3 167299084Sjmcneill#define TX_CHECKSUM_CTL_SHIFT 27 168299084Sjmcneill#define TX_CRC_CTL (1 << 26) 169299084Sjmcneill#define TX_BUF_SIZE (0xfff << 0) 170299084Sjmcneill#define TX_BUF_SIZE_SHIFT 0 171299084Sjmcneill/* Receive */ 172299084Sjmcneill#define RX_INT_CTL (1 << 31) 173299084Sjmcneill#define RX_BUF_SIZE (0xfff << 0) 174299084Sjmcneill#define RX_BUF_SIZE_SHIFT 0 175299084Sjmcneill 176299084Sjmcneill uint32_t addr; 177299084Sjmcneill 178299084Sjmcneill uint32_t next; 179299084Sjmcneill} __packed; 180299084Sjmcneill 181299084Sjmcneill#endif /* !__IF_AWGREG_H__ */ 182