pci_cfgreg.c revision 106357
1/* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/amd64/pci/pci_cfgreg.c 106357 2002-11-02 22:32:04Z imp $ 29 * 30 */ 31 32#include <sys/param.h> /* XXX trim includes */ 33#include <sys/systm.h> 34#include <sys/bus.h> 35#include <sys/kernel.h> 36#include <sys/module.h> 37#include <sys/malloc.h> 38#include <vm/vm.h> 39#include <vm/pmap.h> 40#include <machine/md_var.h> 41#include <dev/pci/pcivar.h> 42#include <dev/pci/pcireg.h> 43#include <isa/isavar.h> 44#include <machine/pci_cfgreg.h> 45#include <machine/segments.h> 46#include <machine/pc/bios.h> 47 48#ifdef APIC_IO 49#include <machine/smp.h> 50#endif /* APIC_IO */ 51 52#include "pcib_if.h" 53 54#define PRVERB(a) do { \ 55 if (bootverbose) \ 56 printf a ; \ 57} while(0) 58 59static int cfgmech; 60static int devmax; 61static int usebios; 62static int enable_pcibios = 0; 63 64TUNABLE_INT("hw.pci.enable_pcibios", &enable_pcibios); 65 66static int pci_cfgintr_valid(struct PIR_entry *pe, int pin, int irq); 67static int pci_cfgintr_unique(struct PIR_entry *pe, int pin); 68static int pci_cfgintr_linked(struct PIR_entry *pe, int pin); 69static int pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int pin); 70static int pci_cfgintr_virgin(struct PIR_entry *pe, int pin); 71 72static void pci_print_irqmask(u_int16_t irqs); 73static void pci_print_route_table(struct PIR_table *prt, int size); 74#ifdef USE_PCI_BIOS_FOR_READ_WRITE 75static int pcibios_cfgread(int bus, int slot, int func, int reg, int bytes); 76static void pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes); 77#endif 78static int pcibios_cfgopen(void); 79static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes); 80static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes); 81static int pcireg_cfgopen(void); 82 83static struct PIR_table *pci_route_table; 84static int pci_route_count; 85 86/* 87 * Some BIOS writers seem to want to ignore the spec and put 88 * 0 in the intline rather than 255 to indicate none. Some use 89 * numbers in the range 128-254 to indicate something strange and 90 * apparently undocumented anywhere. Assume these are completely bogus 91 * and map them to 255, which means "none". 92 */ 93static __inline__ int 94pci_i386_map_intline(int line) 95{ 96 if (line == 0 || line >= 128) 97 return (PCI_INVALID_IRQ); 98 return (line); 99} 100 101int 102pci_pcibios_active(void) 103{ 104 return (usebios); 105} 106 107int 108pci_kill_pcibios(void) 109{ 110 usebios = 0; 111 return (pcireg_cfgopen() != 0); 112} 113 114static u_int16_t 115pcibios_get_version(void) 116{ 117 struct bios_regs args; 118 119 if (PCIbios.ventry == 0) { 120 PRVERB(("pcibios: No call entry point\n")); 121 return (0); 122 } 123 args.eax = PCIBIOS_BIOS_PRESENT; 124 if (bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL))) { 125 PRVERB(("pcibios: BIOS_PRESENT call failed\n")); 126 return (0); 127 } 128 if (args.edx != 0x20494350) { 129 PRVERB(("pcibios: BIOS_PRESENT didn't return 'PCI ' in edx\n")); 130 return (0); 131 } 132 return (args.ebx & 0xffff); 133} 134 135/* 136 * Initialise access to PCI configuration space 137 */ 138int 139pci_cfgregopen(void) 140{ 141 static int opened = 0; 142 u_long sigaddr; 143 static struct PIR_table *pt; 144 u_int8_t ck, *cv; 145 int i; 146 147 if (opened) 148 return(1); 149 150 if (pcibios_cfgopen() != 0) 151 usebios = 1; 152 else if (pcireg_cfgopen() != 0) 153 usebios = 0; 154 else 155 return(0); 156 157 /* 158 * Look for the interrupt routing table. 159 * 160 * We use PCI BIOS's PIR table if it's available $PIR is the 161 * standard way to do this. Sadly, some machines are not 162 * standards conforming and have _PIR instead. We shrug and cope 163 * by looking for both. 164 */ 165 if (pcibios_get_version() >= 0x0210 && pt == NULL) { 166 sigaddr = bios_sigsearch(0, "$PIR", 4, 16, 0); 167 if (sigaddr == 0) 168 sigaddr = bios_sigsearch(0, "_PIR", 4, 16, 0); 169 if (sigaddr != 0) { 170 pt = (struct PIR_table *)(uintptr_t) 171 BIOS_PADDRTOVADDR(sigaddr); 172 for (cv = (u_int8_t *)pt, ck = 0, i = 0; 173 i < (pt->pt_header.ph_length); i++) { 174 ck += cv[i]; 175 } 176 if (ck == 0 && pt->pt_header.ph_length > 177 sizeof(struct PIR_header)) { 178 pci_route_table = pt; 179 pci_route_count = (pt->pt_header.ph_length - 180 sizeof(struct PIR_header)) / 181 sizeof(struct PIR_entry); 182 printf("Using $PIR table, %d entries at %p\n", 183 pci_route_count, pci_route_table); 184 if (bootverbose) 185 pci_print_route_table(pci_route_table, 186 pci_route_count); 187 } 188 } 189 } 190 opened = 1; 191 return(1); 192} 193 194/* 195 * Read configuration space register 196 */ 197static u_int32_t 198pci_do_cfgregread(int bus, int slot, int func, int reg, int bytes) 199{ 200#ifdef USE_PCI_BIOS_FOR_READ_WRITE 201 return(usebios ? 202 pcibios_cfgread(bus, slot, func, reg, bytes) : 203 pcireg_cfgread(bus, slot, func, reg, bytes)); 204#else 205 return (pcireg_cfgread(bus, slot, func, reg, bytes)); 206#endif 207} 208 209u_int32_t 210pci_cfgregread(int bus, int slot, int func, int reg, int bytes) 211{ 212 uint32_t line; 213#ifdef APIC_IO 214 uint32_t pin; 215 216 /* 217 * If we are using the APIC, the contents of the intline 218 * register will probably be wrong (since they are set up for 219 * use with the PIC. Rather than rewrite these registers 220 * (maybe that would be smarter) we trap attempts to read them 221 * and translate to our private vector numbers. 222 */ 223 if ((reg == PCIR_INTLINE) && (bytes == 1)) { 224 225 pin = pci_do_cfgregread(bus, slot, func, PCIR_INTPIN, 1); 226 line = pci_do_cfgregread(bus, slot, func, PCIR_INTLINE, 1); 227 228 if (pin != 0) { 229 int airq; 230 231 airq = pci_apic_irq(bus, slot, pin); 232 if (airq >= 0) { 233 /* PCI specific entry found in MP table */ 234 if (airq != line) 235 undirect_pci_irq(line); 236 return(airq); 237 } else { 238 /* 239 * PCI interrupts might be redirected 240 * to the ISA bus according to some MP 241 * tables. Use the same methods as 242 * used by the ISA devices devices to 243 * find the proper IOAPIC int pin. 244 */ 245 airq = isa_apic_irq(line); 246 if ((airq >= 0) && (airq != line)) { 247 /* XXX: undirect_pci_irq() ? */ 248 undirect_isa_irq(line); 249 return(airq); 250 } 251 } 252 } 253 return(line); 254 } 255#else 256 /* 257 * Some BIOS writers seem to want to ignore the spec and put 258 * 0 in the intline rather than 255 to indicate none. The rest of 259 * the code uses 255 as an invalid IRQ. 260 */ 261 if (reg == PCIR_INTLINE && bytes == 1) { 262 line = pci_do_cfgregread(bus, slot, func, PCIR_INTLINE, 1); 263 return pci_i386_map_intline(line); 264 } 265#endif /* APIC_IO */ 266 return(pci_do_cfgregread(bus, slot, func, reg, bytes)); 267} 268 269/* 270 * Write configuration space register 271 */ 272void 273pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes) 274{ 275#ifdef USE_PCI_BIOS_FOR_READ_WRITE 276 if (usebios) 277 pcibios_cfgwrite(bus, slot, func, reg, data, bytes); 278 else 279 pcireg_cfgwrite(bus, slot, func, reg, data, bytes); 280#else 281 pcireg_cfgwrite(bus, slot, func, reg, data, bytes); 282#endif 283} 284 285/* 286 * Route a PCI interrupt 287 */ 288int 289pci_cfgintr(int bus, int device, int pin, int oldirq) 290{ 291 struct PIR_entry *pe; 292 int i, irq; 293 struct bios_regs args; 294 u_int16_t v; 295 int already = 0; 296 297 v = pcibios_get_version(); 298 if (v < 0x0210) { 299 PRVERB(( 300 "pci_cfgintr: BIOS %x.%02x doesn't support interrupt routing\n", 301 (v & 0xff00) >> 8, v & 0xff)); 302 return (PCI_INVALID_IRQ); 303 } 304 if ((bus < 0) || (bus > 255) || (device < 0) || (device > 255) || 305 (pin < 1) || (pin > 4)) 306 return(PCI_INVALID_IRQ); 307 308 /* 309 * Scan the entry table for a contender 310 */ 311 for (i = 0, pe = &pci_route_table->pt_entry[0]; i < pci_route_count; 312 i++, pe++) { 313 if ((bus != pe->pe_bus) || (device != pe->pe_device)) 314 continue; 315 /* 316 * A link of 0 means that this intpin is not connected to 317 * any other device's interrupt pins and is not connected to 318 * any of the Interrupt Router's interrupt pins, so we can't 319 * route it. 320 */ 321 if (pe->pe_intpin[pin - 1].link == 0) 322 continue; 323 324 if (pci_cfgintr_valid(pe, pin, oldirq)) { 325 printf("pci_cfgintr: %d:%d INT%c BIOS irq %d\n", bus, 326 device, 'A' + pin - 1, oldirq); 327 return (oldirq); 328 } 329 irq = pci_cfgintr_linked(pe, pin); 330 if (irq == PCI_INVALID_IRQ) 331 irq = pci_cfgintr_unique(pe, pin); 332 if (irq == PCI_INVALID_IRQ) 333 irq = pci_cfgintr_virgin(pe, pin); 334 if (irq == PCI_INVALID_IRQ) 335 break; 336 337 /* 338 * Ask the BIOS to route the interrupt 339 */ 340 args.eax = PCIBIOS_ROUTE_INTERRUPT; 341 args.ebx = (bus << 8) | (device << 3); 342 /* pin value is 0xa - 0xd */ 343 args.ecx = (irq << 8) | (0xa + pin - 1); 344 if (!already && 345 bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL))) { 346 /* 347 * XXX if it fails, we should try to smack the router 348 * hardware directly. 349 * XXX Also, there may be other choices that we can 350 * try that will work. 351 */ 352 PRVERB(("pci_cfgintr: ROUTE_INTERRUPT failed.\n")); 353 return(PCI_INVALID_IRQ); 354 } 355 printf("pci_cfgintr: %d:%d INT%c routed to irq %d\n", bus, 356 device, 'A' + pin - 1, irq); 357 return(irq); 358 } 359 360 PRVERB(("pci_cfgintr: can't route an interrupt to %d:%d INT%c\n", bus, 361 device, 'A' + pin - 1)); 362 return(PCI_INVALID_IRQ); 363} 364 365/* 366 * Check to see if an existing IRQ setting is valid. 367 */ 368static int 369pci_cfgintr_valid(struct PIR_entry *pe, int pin, int irq) 370{ 371 uint32_t irqmask; 372 373 if (!PCI_INTERRUPT_VALID(irq)) 374 return (0); 375 irqmask = pe->pe_intpin[pin - 1].irqs; 376 if (irqmask & (1 << irq)) { 377 PRVERB(("pci_cfgintr_valid: BIOS irq %d is valid\n", irq)); 378 return (1); 379 } 380 return (0); 381} 382 383/* 384 * Look to see if the routing table claims this pin is uniquely routed. 385 */ 386static int 387pci_cfgintr_unique(struct PIR_entry *pe, int pin) 388{ 389 int irq; 390 uint32_t irqmask; 391 392 irqmask = pe->pe_intpin[pin - 1].irqs; 393 if (irqmask != 0 && powerof2(irqmask)) { 394 irq = ffs(irqmask) - 1; 395 PRVERB(("pci_cfgintr_unique: hard-routed to irq %d\n", irq)); 396 return(irq); 397 } 398 return(PCI_INVALID_IRQ); 399} 400 401/* 402 * Look for another device which shares the same link byte and 403 * already has a unique IRQ, or which has had one routed already. 404 */ 405static int 406pci_cfgintr_linked(struct PIR_entry *pe, int pin) 407{ 408 struct PIR_entry *oe; 409 struct PIR_intpin *pi; 410 int i, j, irq; 411 412 /* 413 * Scan table slots. 414 */ 415 for (i = 0, oe = &pci_route_table->pt_entry[0]; i < pci_route_count; 416 i++, oe++) { 417 /* scan interrupt pins */ 418 for (j = 0, pi = &oe->pe_intpin[0]; j < 4; j++, pi++) { 419 420 /* don't look at the entry we're trying to match */ 421 if ((pe == oe) && (i == (pin - 1))) 422 continue; 423 /* compare link bytes */ 424 if (pi->link != pe->pe_intpin[pin - 1].link) 425 continue; 426 /* link destination mapped to a unique interrupt? */ 427 if (pi->irqs != 0 && powerof2(pi->irqs)) { 428 irq = ffs(pi->irqs) - 1; 429 PRVERB(("pci_cfgintr_linked: linked (%x) to hard-routed irq %d\n", 430 pi->link, irq)); 431 return(irq); 432 } 433 434 /* 435 * look for the real PCI device that matches this 436 * table entry 437 */ 438 irq = pci_cfgintr_search(pe, oe->pe_bus, oe->pe_device, 439 j, pin); 440 if (irq != PCI_INVALID_IRQ) 441 return(irq); 442 } 443 } 444 return(PCI_INVALID_IRQ); 445} 446 447/* 448 * Scan for the real PCI device at (bus)/(device) using intpin (matchpin) and 449 * see if it has already been assigned an interrupt. 450 */ 451static int 452pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int pin) 453{ 454 devclass_t pci_devclass; 455 device_t *pci_devices; 456 int pci_count; 457 device_t *pci_children; 458 int pci_childcount; 459 device_t *busp, *childp; 460 int i, j, irq; 461 462 /* 463 * Find all the PCI busses. 464 */ 465 pci_count = 0; 466 if ((pci_devclass = devclass_find("pci")) != NULL) 467 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 468 469 /* 470 * Scan all the PCI busses/devices looking for this one. 471 */ 472 irq = PCI_INVALID_IRQ; 473 for (i = 0, busp = pci_devices; (i < pci_count) && (irq == PCI_INVALID_IRQ); 474 i++, busp++) { 475 pci_childcount = 0; 476 device_get_children(*busp, &pci_children, &pci_childcount); 477 478 for (j = 0, childp = pci_children; j < pci_childcount; j++, 479 childp++) { 480 if ((pci_get_bus(*childp) == bus) && 481 (pci_get_slot(*childp) == device) && 482 (pci_get_intpin(*childp) == matchpin)) { 483 irq = pci_i386_map_intline(pci_get_irq(*childp)); 484 if (irq != PCI_INVALID_IRQ) 485 PRVERB(("pci_cfgintr_search: linked (%x) to configured irq %d at %d:%d:%d\n", 486 pe->pe_intpin[pin - 1].link, irq, 487 pci_get_bus(*childp), 488 pci_get_slot(*childp), 489 pci_get_function(*childp))); 490 break; 491 } 492 } 493 if (pci_children != NULL) 494 free(pci_children, M_TEMP); 495 } 496 if (pci_devices != NULL) 497 free(pci_devices, M_TEMP); 498 return(irq); 499} 500 501/* 502 * Pick a suitable IRQ from those listed as routable to this device. 503 */ 504static int 505pci_cfgintr_virgin(struct PIR_entry *pe, int pin) 506{ 507 int irq, ibit; 508 509 /* 510 * first scan the set of PCI-only interrupts and see if any of these 511 * are routable 512 */ 513 for (irq = 0; irq < 16; irq++) { 514 ibit = (1 << irq); 515 516 /* can we use this interrupt? */ 517 if ((pci_route_table->pt_header.ph_pci_irqs & ibit) && 518 (pe->pe_intpin[pin - 1].irqs & ibit)) { 519 PRVERB(("pci_cfgintr_virgin: using routable PCI-only interrupt %d\n", irq)); 520 return(irq); 521 } 522 } 523 524 /* life is tough, so just pick an interrupt */ 525 for (irq = 0; irq < 16; irq++) { 526 ibit = (1 << irq); 527 if (pe->pe_intpin[pin - 1].irqs & ibit) { 528 PRVERB(("pci_cfgintr_virgin: using routable interrupt %d\n", irq)); 529 return(irq); 530 } 531 } 532 return(PCI_INVALID_IRQ); 533} 534 535static void 536pci_print_irqmask(u_int16_t irqs) 537{ 538 int i, first; 539 540 if (irqs == 0) { 541 printf("none"); 542 return; 543 } 544 first = 1; 545 for (i = 0; i < 16; i++, irqs >>= 1) 546 if (irqs & 1) { 547 if (!first) 548 printf(" "); 549 else 550 first = 0; 551 printf("%d", i); 552 } 553} 554 555/* 556 * Dump the contents of a PCI BIOS Interrupt Routing Table to the console. 557 */ 558static void 559pci_print_route_table(struct PIR_table *prt, int size) 560{ 561 struct PIR_entry *entry; 562 struct PIR_intpin *intpin; 563 int i, pin; 564 565 printf("PCI-Only Interrupts: "); 566 pci_print_irqmask(prt->pt_header.ph_pci_irqs); 567 printf("\nLocation Bus Device Pin Link IRQs\n"); 568 entry = &prt->pt_entry[0]; 569 for (i = 0; i < size; i++, entry++) { 570 intpin = &entry->pe_intpin[0]; 571 for (pin = 0; pin < 4; pin++, intpin++) 572 if (intpin->link != 0) { 573 if (entry->pe_slot == 0) 574 printf("embedded "); 575 else 576 printf("slot %-3d ", entry->pe_slot); 577 printf(" %3d %3d %c 0x%02x ", 578 entry->pe_bus, entry->pe_device, 579 'A' + pin, intpin->link); 580 pci_print_irqmask(intpin->irqs); 581 printf("\n"); 582 } 583 } 584} 585 586/* 587 * See if any interrupts for a given PCI bus are routed in the PIR. Don't 588 * even bother looking if the BIOS doesn't support routing anyways. 589 */ 590int 591pci_probe_route_table(int bus) 592{ 593 int i; 594 u_int16_t v; 595 596 v = pcibios_get_version(); 597 if (v < 0x0210) 598 return (0); 599 for (i = 0; i < pci_route_count; i++) 600 if (pci_route_table->pt_entry[i].pe_bus == bus) 601 return (1); 602 return (0); 603} 604 605#ifdef USE_PCI_BIOS_FOR_READ_WRITE 606/* 607 * Config space access using BIOS functions 608 */ 609static int 610pcibios_cfgread(int bus, int slot, int func, int reg, int bytes) 611{ 612 struct bios_regs args; 613 u_int mask; 614 615 switch(bytes) { 616 case 1: 617 args.eax = PCIBIOS_READ_CONFIG_BYTE; 618 mask = 0xff; 619 break; 620 case 2: 621 args.eax = PCIBIOS_READ_CONFIG_WORD; 622 mask = 0xffff; 623 break; 624 case 4: 625 args.eax = PCIBIOS_READ_CONFIG_DWORD; 626 mask = 0xffffffff; 627 break; 628 default: 629 return(-1); 630 } 631 args.ebx = (bus << 8) | (slot << 3) | func; 632 args.edi = reg; 633 bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL)); 634 /* check call results? */ 635 return(args.ecx & mask); 636} 637 638static void 639pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes) 640{ 641 struct bios_regs args; 642 643 switch(bytes) { 644 case 1: 645 args.eax = PCIBIOS_WRITE_CONFIG_BYTE; 646 break; 647 case 2: 648 args.eax = PCIBIOS_WRITE_CONFIG_WORD; 649 break; 650 case 4: 651 args.eax = PCIBIOS_WRITE_CONFIG_DWORD; 652 break; 653 default: 654 return; 655 } 656 args.ebx = (bus << 8) | (slot << 3) | func; 657 args.ecx = data; 658 args.edi = reg; 659 bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL)); 660} 661#endif 662 663/* 664 * Determine whether there is a PCI BIOS present 665 */ 666static int 667pcibios_cfgopen(void) 668{ 669 u_int16_t v = 0; 670 671 if (PCIbios.ventry != 0 && enable_pcibios) { 672 v = pcibios_get_version(); 673 if (v > 0) 674 printf("pcibios: BIOS version %x.%02x\n", 675 (v & 0xff00) >> 8, v & 0xff); 676 } 677 return (v > 0); 678} 679 680/* 681 * Configuration space access using direct register operations 682 */ 683 684/* enable configuration space accesses and return data port address */ 685static int 686pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes) 687{ 688 int dataport = 0; 689 690 if (bus <= PCI_BUSMAX 691 && slot < devmax 692 && func <= PCI_FUNCMAX 693 && reg <= PCI_REGMAX 694 && bytes != 3 695 && (unsigned) bytes <= 4 696 && (reg & (bytes -1)) == 0) { 697 switch (cfgmech) { 698 case 1: 699 outl(CONF1_ADDR_PORT, (1 << 31) 700 | (bus << 16) | (slot << 11) 701 | (func << 8) | (reg & ~0x03)); 702 dataport = CONF1_DATA_PORT + (reg & 0x03); 703 break; 704 case 2: 705 outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1)); 706 outb(CONF2_FORWARD_PORT, bus); 707 dataport = 0xc000 | (slot << 8) | reg; 708 break; 709 } 710 } 711 return (dataport); 712} 713 714/* disable configuration space accesses */ 715static void 716pci_cfgdisable(void) 717{ 718 switch (cfgmech) { 719 case 1: 720 outl(CONF1_ADDR_PORT, 0); 721 break; 722 case 2: 723 outb(CONF2_ENABLE_PORT, 0); 724 outb(CONF2_FORWARD_PORT, 0); 725 break; 726 } 727} 728 729static int 730pcireg_cfgread(int bus, int slot, int func, int reg, int bytes) 731{ 732 int data = -1; 733 int port; 734 735 port = pci_cfgenable(bus, slot, func, reg, bytes); 736 737 if (port != 0) { 738 switch (bytes) { 739 case 1: 740 data = inb(port); 741 break; 742 case 2: 743 data = inw(port); 744 break; 745 case 4: 746 data = inl(port); 747 break; 748 } 749 pci_cfgdisable(); 750 } 751 return (data); 752} 753 754static void 755pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes) 756{ 757 int port; 758 759 port = pci_cfgenable(bus, slot, func, reg, bytes); 760 if (port != 0) { 761 switch (bytes) { 762 case 1: 763 outb(port, data); 764 break; 765 case 2: 766 outw(port, data); 767 break; 768 case 4: 769 outl(port, data); 770 break; 771 } 772 pci_cfgdisable(); 773 } 774} 775 776/* check whether the configuration mechanism has been correctly identified */ 777static int 778pci_cfgcheck(int maxdev) 779{ 780 uint32_t id, class; 781 uint8_t header; 782 uint8_t device; 783 784 if (bootverbose) 785 printf("pci_cfgcheck:\tdevice "); 786 787 for (device = 0; device < maxdev; device++) { 788 if (bootverbose) 789 printf("%d ", device); 790 791 id = inl(pci_cfgenable(0, device, 0, 0, 4)); 792 if (id == 0 || id == 0xffffffff) 793 continue; 794 795 class = inl(pci_cfgenable(0, device, 0, 8, 4)) >> 8; 796 if (bootverbose) 797 printf("[class=%06x] ", class); 798 if (class == 0 || (class & 0xf870ff) != 0) 799 continue; 800 801 header = inb(pci_cfgenable(0, device, 0, 14, 1)); 802 if (bootverbose) 803 printf("[hdr=%02x] ", header); 804 if ((header & 0x7e) != 0) 805 continue; 806 807 if (bootverbose) 808 printf("is there (id=%08x)\n", id); 809 810 pci_cfgdisable(); 811 return (1); 812 } 813 if (bootverbose) 814 printf("-- nothing found\n"); 815 816 pci_cfgdisable(); 817 return (0); 818} 819 820static int 821pcireg_cfgopen(void) 822{ 823 uint32_t mode1res, oldval1; 824 uint8_t mode2res, oldval2; 825 826 oldval1 = inl(CONF1_ADDR_PORT); 827 828 if (bootverbose) { 829 printf("pci_open(1):\tmode 1 addr port (0x0cf8) is 0x%08x\n", 830 oldval1); 831 } 832 833 if ((oldval1 & CONF1_ENABLE_MSK) == 0) { 834 835 cfgmech = 1; 836 devmax = 32; 837 838 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK); 839 outb(CONF1_ADDR_PORT + 3, 0); 840 mode1res = inl(CONF1_ADDR_PORT); 841 outl(CONF1_ADDR_PORT, oldval1); 842 843 if (bootverbose) 844 printf("pci_open(1a):\tmode1res=0x%08x (0x%08lx)\n", 845 mode1res, CONF1_ENABLE_CHK); 846 847 if (mode1res) { 848 if (pci_cfgcheck(32)) 849 return (cfgmech); 850 } 851 852 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK1); 853 mode1res = inl(CONF1_ADDR_PORT); 854 outl(CONF1_ADDR_PORT, oldval1); 855 856 if (bootverbose) 857 printf("pci_open(1b):\tmode1res=0x%08x (0x%08lx)\n", 858 mode1res, CONF1_ENABLE_CHK1); 859 860 if ((mode1res & CONF1_ENABLE_MSK1) == CONF1_ENABLE_RES1) { 861 if (pci_cfgcheck(32)) 862 return (cfgmech); 863 } 864 } 865 866 oldval2 = inb(CONF2_ENABLE_PORT); 867 868 if (bootverbose) { 869 printf("pci_open(2):\tmode 2 enable port (0x0cf8) is 0x%02x\n", 870 oldval2); 871 } 872 873 if ((oldval2 & 0xf0) == 0) { 874 875 cfgmech = 2; 876 devmax = 16; 877 878 outb(CONF2_ENABLE_PORT, CONF2_ENABLE_CHK); 879 mode2res = inb(CONF2_ENABLE_PORT); 880 outb(CONF2_ENABLE_PORT, oldval2); 881 882 if (bootverbose) 883 printf("pci_open(2a):\tmode2res=0x%02x (0x%02x)\n", 884 mode2res, CONF2_ENABLE_CHK); 885 886 if (mode2res == CONF2_ENABLE_RES) { 887 if (bootverbose) 888 printf("pci_open(2a):\tnow trying mechanism 2\n"); 889 890 if (pci_cfgcheck(16)) 891 return (cfgmech); 892 } 893 } 894 895 cfgmech = 0; 896 devmax = 0; 897 return (cfgmech); 898} 899 900