intr_machdep.h revision 255040
1260684Skaiw/*- 2260684Skaiw * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3260684Skaiw * All rights reserved. 4260684Skaiw * 5260684Skaiw * Redistribution and use in source and binary forms, with or without 6260684Skaiw * modification, are permitted provided that the following conditions 7260684Skaiw * are met: 8260684Skaiw * 1. Redistributions of source code must retain the above copyright 9260684Skaiw * notice, this list of conditions and the following disclaimer. 10260684Skaiw * 2. Redistributions in binary form must reproduce the above copyright 11260684Skaiw * notice, this list of conditions and the following disclaimer in the 12260684Skaiw * documentation and/or other materials provided with the distribution. 13260684Skaiw * 14260684Skaiw * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15260684Skaiw * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16260684Skaiw * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17260684Skaiw * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18260684Skaiw * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19260684Skaiw * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20260684Skaiw * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21260684Skaiw * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22260684Skaiw * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23260684Skaiw * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24260684Skaiw * SUCH DAMAGE. 25260684Skaiw * 26260684Skaiw * $FreeBSD: head/sys/amd64/include/intr_machdep.h 255040 2013-08-29 19:52:18Z gibbs $ 27260684Skaiw */ 28260684Skaiw 29260684Skaiw#ifndef __MACHINE_INTR_MACHDEP_H__ 30260684Skaiw#define __MACHINE_INTR_MACHDEP_H__ 31260684Skaiw 32260684Skaiw#ifdef _KERNEL 33260684Skaiw 34260684Skaiw/* 35260684Skaiw * The maximum number of I/O interrupts we allow. This number is rather 36260684Skaiw * arbitrary as it is just the maximum IRQ resource value. The interrupt 37260684Skaiw * source for a given IRQ maps that I/O interrupt to device interrupt 38260684Skaiw * source whether it be a pin on an interrupt controller or an MSI interrupt. 39260684Skaiw * The 16 ISA IRQs are assigned fixed IDT vectors, but all other device 40260684Skaiw * interrupts allocate IDT vectors on demand. Currently we have 191 IDT 41260684Skaiw * vectors available for device interrupts. On many systems with I/O APICs, 42260684Skaiw * a lot of the IRQs are not used, so this number can be much larger than 43260684Skaiw * 191 and still be safe since only interrupt sources in actual use will 44260684Skaiw * allocate IDT vectors. 45260684Skaiw * 46260684Skaiw * The first 255 IRQs (0 - 254) are reserved for ISA IRQs and PCI intline IRQs. 47260684Skaiw * IRQ values from 256 to 767 are used by MSI. When running under the Xen 48260684Skaiw * Hypervisor, IRQ values from 768 to 4863 are available for binding to 49260684Skaiw * event channel events. We leave 255 unused to avoid confusion since 255 is 50260684Skaiw * used in PCI to indicate an invalid IRQ. 51260684Skaiw */ 52260684Skaiw#define NUM_MSI_INTS 512 53260684Skaiw#define FIRST_MSI_INT 256 54260684Skaiw#ifdef XENHVM 55260684Skaiw#include <xen/xen-os.h> 56260684Skaiw#define NUM_EVTCHN_INTS NR_EVENT_CHANNELS 57260684Skaiw#define FIRST_EVTCHN_INT \ 58260684Skaiw (FIRST_MSI_INT + NUM_MSI_INTS) 59260684Skaiw#define LAST_EVTCHN_INT \ 60260684Skaiw (FIRST_EVTCHN_INT + NUM_EVTCHN_INTS - 1) 61260684Skaiw#else 62260684Skaiw#define NUM_EVTCHN_INTS 0 63260684Skaiw#endif 64260684Skaiw#define NUM_IO_INTS (FIRST_MSI_INT + NUM_MSI_INTS + NUM_EVTCHN_INTS) 65260684Skaiw 66260684Skaiw/* 67260684Skaiw * Default base address for MSI messages on x86 platforms. 68260684Skaiw */ 69260684Skaiw#define MSI_INTEL_ADDR_BASE 0xfee00000 70260684Skaiw 71260684Skaiw/* 72260684Skaiw * - 1 ??? dummy counter. 73260684Skaiw * - 2 counters for each I/O interrupt. 74260684Skaiw * - 1 counter for each CPU for lapic timer. 75260684Skaiw * - 8 counters for each CPU for IPI counters for SMP. 76260684Skaiw */ 77260684Skaiw#ifdef SMP 78260684Skaiw#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + (1 + 8) * MAXCPU) 79260684Skaiw#else 80260684Skaiw#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + 1) 81260684Skaiw#endif 82260684Skaiw 83260684Skaiw#ifndef LOCORE 84260684Skaiw 85260684Skaiwtypedef void inthand_t(u_int cs, u_int ef, u_int esp, u_int ss); 86260684Skaiw 87260684Skaiw#define IDTVEC(name) __CONCAT(X,name) 88260684Skaiw 89260684Skaiwstruct intsrc; 90260684Skaiw 91260684Skaiw/* 92260684Skaiw * Methods that a PIC provides to mask/unmask a given interrupt source, 93260684Skaiw * "turn on" the interrupt on the CPU side by setting up an IDT entry, and 94260684Skaiw * return the vector associated with this source. 95260684Skaiw */ 96260684Skaiwstruct pic { 97260684Skaiw void (*pic_enable_source)(struct intsrc *); 98260684Skaiw void (*pic_disable_source)(struct intsrc *, int); 99260684Skaiw void (*pic_eoi_source)(struct intsrc *); 100260684Skaiw void (*pic_enable_intr)(struct intsrc *); 101260684Skaiw void (*pic_disable_intr)(struct intsrc *); 102260684Skaiw int (*pic_vector)(struct intsrc *); 103260684Skaiw int (*pic_source_pending)(struct intsrc *); 104260684Skaiw void (*pic_suspend)(struct pic *); 105260684Skaiw void (*pic_resume)(struct pic *); 106260684Skaiw int (*pic_config_intr)(struct intsrc *, enum intr_trigger, 107260684Skaiw enum intr_polarity); 108260684Skaiw int (*pic_assign_cpu)(struct intsrc *, u_int apic_id); 109260684Skaiw TAILQ_ENTRY(pic) pics; 110260684Skaiw}; 111260684Skaiw 112260684Skaiw/* Flags for pic_disable_source() */ 113260684Skaiwenum { 114260684Skaiw PIC_EOI, 115260684Skaiw PIC_NO_EOI, 116260684Skaiw}; 117260684Skaiw 118260684Skaiw/* 119260684Skaiw * An interrupt source. The upper-layer code uses the PIC methods to 120260684Skaiw * control a given source. The lower-layer PIC drivers can store additional 121260684Skaiw * private data in a given interrupt source such as an interrupt pin number 122260684Skaiw * or an I/O APIC pointer. 123260684Skaiw */ 124260684Skaiwstruct intsrc { 125260684Skaiw struct pic *is_pic; 126260684Skaiw struct intr_event *is_event; 127260684Skaiw u_long *is_count; 128260684Skaiw u_long *is_straycount; 129260684Skaiw u_int is_index; 130260684Skaiw u_int is_handlers; 131260684Skaiw}; 132260684Skaiw 133260684Skaiwstruct trapframe; 134260684Skaiw 135260684Skaiw/* 136260684Skaiw * The following data structure holds per-cpu data, and is placed just 137260684Skaiw * above the top of the space used for the NMI stack. 138260684Skaiw */ 139260684Skaiwstruct nmi_pcpu { 140260684Skaiw register_t np_pcpu; 141260684Skaiw register_t __padding; /* pad to 16 bytes */ 142260684Skaiw}; 143260684Skaiw 144260684Skaiwextern struct mtx icu_lock; 145260684Skaiwextern int elcr_found; 146260684Skaiw 147260684Skaiw#ifndef DEV_ATPIC 148260684Skaiwvoid atpic_reset(void); 149260684Skaiw#endif 150260684Skaiw/* XXX: The elcr_* prototypes probably belong somewhere else. */ 151260684Skaiwint elcr_probe(void); 152260684Skaiwenum intr_trigger elcr_read_trigger(u_int irq); 153260684Skaiwvoid elcr_resume(void); 154260684Skaiwvoid elcr_write_trigger(u_int irq, enum intr_trigger trigger); 155260684Skaiw#ifdef SMP 156260684Skaiwvoid intr_add_cpu(u_int cpu); 157260684Skaiw#endif 158260684Skaiwint intr_add_handler(const char *name, int vector, driver_filter_t filter, 159260684Skaiw driver_intr_t handler, void *arg, enum intr_type flags, 160260684Skaiw void **cookiep); 161260684Skaiw#ifdef SMP 162260684Skaiwint intr_bind(u_int vector, u_char cpu); 163260684Skaiw#endif 164260684Skaiwint intr_config_intr(int vector, enum intr_trigger trig, 165260684Skaiw enum intr_polarity pol); 166260684Skaiwint intr_describe(u_int vector, void *ih, const char *descr); 167260684Skaiwvoid intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame); 168260684Skaiwu_int intr_next_cpu(void); 169260684Skaiwstruct intsrc *intr_lookup_source(int vector); 170260684Skaiwint intr_register_pic(struct pic *pic); 171260684Skaiwint intr_register_source(struct intsrc *isrc); 172260684Skaiwint intr_remove_handler(void *cookie); 173260684Skaiwvoid intr_resume(void); 174260684Skaiwvoid intr_suspend(void); 175260684Skaiwvoid intrcnt_add(const char *name, u_long **countp); 176260684Skaiwvoid nexus_add_irq(u_long irq); 177260684Skaiwint msi_alloc(device_t dev, int count, int maxcount, int *irqs); 178260684Skaiwvoid msi_init(void); 179260684Skaiwint msi_map(int irq, uint64_t *addr, uint32_t *data); 180260684Skaiwint msi_release(int *irqs, int count); 181260684Skaiwint msix_alloc(device_t dev, int *irq); 182260684Skaiwint msix_release(int irq); 183260684Skaiw 184#endif /* !LOCORE */ 185#endif /* _KERNEL */ 186#endif /* !__MACHINE_INTR_MACHDEP_H__ */ 187