machdep.c revision 266093
1/*- 2 * Copyright (c) 2003 Peter Wemm. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 39 */ 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: head/sys/amd64/amd64/machdep.c 266093 2014-05-14 22:24:09Z neel $"); 43 44#include "opt_atpic.h" 45#include "opt_compat.h" 46#include "opt_cpu.h" 47#include "opt_ddb.h" 48#include "opt_inet.h" 49#include "opt_isa.h" 50#include "opt_kstack_pages.h" 51#include "opt_maxmem.h" 52#include "opt_mp_watchdog.h" 53#include "opt_perfmon.h" 54#include "opt_platform.h" 55#include "opt_sched.h" 56 57#include <sys/param.h> 58#include <sys/proc.h> 59#include <sys/systm.h> 60#include <sys/bio.h> 61#include <sys/buf.h> 62#include <sys/bus.h> 63#include <sys/callout.h> 64#include <sys/cons.h> 65#include <sys/cpu.h> 66#include <sys/efi.h> 67#include <sys/eventhandler.h> 68#include <sys/exec.h> 69#include <sys/imgact.h> 70#include <sys/kdb.h> 71#include <sys/kernel.h> 72#include <sys/ktr.h> 73#include <sys/linker.h> 74#include <sys/lock.h> 75#include <sys/malloc.h> 76#include <sys/memrange.h> 77#include <sys/msgbuf.h> 78#include <sys/mutex.h> 79#include <sys/pcpu.h> 80#include <sys/ptrace.h> 81#include <sys/reboot.h> 82#include <sys/rwlock.h> 83#include <sys/sched.h> 84#include <sys/signalvar.h> 85#ifdef SMP 86#include <sys/smp.h> 87#endif 88#include <sys/syscallsubr.h> 89#include <sys/sysctl.h> 90#include <sys/sysent.h> 91#include <sys/sysproto.h> 92#include <sys/ucontext.h> 93#include <sys/vmmeter.h> 94 95#include <vm/vm.h> 96#include <vm/vm_extern.h> 97#include <vm/vm_kern.h> 98#include <vm/vm_page.h> 99#include <vm/vm_map.h> 100#include <vm/vm_object.h> 101#include <vm/vm_pager.h> 102#include <vm/vm_param.h> 103 104#ifdef DDB 105#ifndef KDB 106#error KDB must be enabled in order for DDB to work! 107#endif 108#include <ddb/ddb.h> 109#include <ddb/db_sym.h> 110#endif 111 112#include <net/netisr.h> 113 114#include <machine/clock.h> 115#include <machine/cpu.h> 116#include <machine/cputypes.h> 117#include <machine/intr_machdep.h> 118#include <x86/mca.h> 119#include <machine/md_var.h> 120#include <machine/metadata.h> 121#include <machine/mp_watchdog.h> 122#include <machine/pc/bios.h> 123#include <machine/pcb.h> 124#include <machine/proc.h> 125#include <machine/reg.h> 126#include <machine/sigframe.h> 127#include <machine/specialreg.h> 128#ifdef PERFMON 129#include <machine/perfmon.h> 130#endif 131#include <machine/tss.h> 132#ifdef SMP 133#include <machine/smp.h> 134#endif 135#ifdef FDT 136#include <x86/fdt.h> 137#endif 138 139#ifdef DEV_ATPIC 140#include <x86/isa/icu.h> 141#else 142#include <x86/apicvar.h> 143#endif 144 145#include <isa/isareg.h> 146#include <isa/rtc.h> 147#include <x86/init.h> 148 149/* Sanity check for __curthread() */ 150CTASSERT(offsetof(struct pcpu, pc_curthread) == 0); 151 152extern u_int64_t hammer_time(u_int64_t, u_int64_t); 153 154extern void printcpuinfo(void); /* XXX header file */ 155extern void identify_cpu(void); 156extern void panicifcpuunsupported(void); 157 158#define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) 159#define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) 160 161static void cpu_startup(void *); 162static void get_fpcontext(struct thread *td, mcontext_t *mcp, 163 char *xfpusave, size_t xfpusave_len); 164static int set_fpcontext(struct thread *td, const mcontext_t *mcp, 165 char *xfpustate, size_t xfpustate_len); 166SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 167 168/* Preload data parse function */ 169static caddr_t native_parse_preload_data(u_int64_t); 170 171/* Native function to fetch and parse the e820 map */ 172static void native_parse_memmap(caddr_t, vm_paddr_t *, int *); 173 174/* Default init_ops implementation. */ 175struct init_ops init_ops = { 176 .parse_preload_data = native_parse_preload_data, 177 .early_clock_source_init = i8254_init, 178 .early_delay = i8254_delay, 179 .parse_memmap = native_parse_memmap, 180#ifdef SMP 181 .mp_bootaddress = mp_bootaddress, 182 .start_all_aps = native_start_all_aps, 183#endif 184}; 185 186/* 187 * The file "conf/ldscript.amd64" defines the symbol "kernphys". Its value is 188 * the physical address at which the kernel is loaded. 189 */ 190extern char kernphys[]; 191#ifdef DDB 192extern vm_offset_t ksym_start, ksym_end; 193#endif 194 195struct msgbuf *msgbufp; 196 197/* Intel ICH registers */ 198#define ICH_PMBASE 0x400 199#define ICH_SMI_EN ICH_PMBASE + 0x30 200 201int _udatasel, _ucodesel, _ucode32sel, _ufssel, _ugssel; 202 203int cold = 1; 204 205long Maxmem = 0; 206long realmem = 0; 207 208/* 209 * The number of PHYSMAP entries must be one less than the number of 210 * PHYSSEG entries because the PHYSMAP entry that spans the largest 211 * physical address that is accessible by ISA DMA is split into two 212 * PHYSSEG entries. 213 */ 214#define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1)) 215 216vm_paddr_t phys_avail[PHYSMAP_SIZE + 2]; 217vm_paddr_t dump_avail[PHYSMAP_SIZE + 2]; 218 219/* must be 2 less so 0 0 can signal end of chunks */ 220#define PHYS_AVAIL_ARRAY_END ((sizeof(phys_avail) / sizeof(phys_avail[0])) - 2) 221#define DUMP_AVAIL_ARRAY_END ((sizeof(dump_avail) / sizeof(dump_avail[0])) - 2) 222 223struct kva_md_info kmi; 224 225static struct trapframe proc0_tf; 226struct region_descriptor r_gdt, r_idt; 227 228struct pcpu __pcpu[MAXCPU]; 229 230struct mtx icu_lock; 231 232struct mem_range_softc mem_range_softc; 233 234struct mtx dt_lock; /* lock for GDT and LDT */ 235 236void (*vmm_resume_p)(void); 237 238static void 239cpu_startup(dummy) 240 void *dummy; 241{ 242 uintmax_t memsize; 243 char *sysenv; 244 245 /* 246 * On MacBooks, we need to disallow the legacy USB circuit to 247 * generate an SMI# because this can cause several problems, 248 * namely: incorrect CPU frequency detection and failure to 249 * start the APs. 250 * We do this by disabling a bit in the SMI_EN (SMI Control and 251 * Enable register) of the Intel ICH LPC Interface Bridge. 252 */ 253 sysenv = getenv("smbios.system.product"); 254 if (sysenv != NULL) { 255 if (strncmp(sysenv, "MacBook1,1", 10) == 0 || 256 strncmp(sysenv, "MacBook3,1", 10) == 0 || 257 strncmp(sysenv, "MacBookPro1,1", 13) == 0 || 258 strncmp(sysenv, "MacBookPro1,2", 13) == 0 || 259 strncmp(sysenv, "MacBookPro3,1", 13) == 0 || 260 strncmp(sysenv, "Macmini1,1", 10) == 0) { 261 if (bootverbose) 262 printf("Disabling LEGACY_USB_EN bit on " 263 "Intel ICH.\n"); 264 outl(ICH_SMI_EN, inl(ICH_SMI_EN) & ~0x8); 265 } 266 freeenv(sysenv); 267 } 268 269 /* 270 * Good {morning,afternoon,evening,night}. 271 */ 272 startrtclock(); 273 printcpuinfo(); 274 panicifcpuunsupported(); 275#ifdef PERFMON 276 perfmon_init(); 277#endif 278 279 /* 280 * Display physical memory if SMBIOS reports reasonable amount. 281 */ 282 memsize = 0; 283 sysenv = getenv("smbios.memory.enabled"); 284 if (sysenv != NULL) { 285 memsize = (uintmax_t)strtoul(sysenv, (char **)NULL, 10) << 10; 286 freeenv(sysenv); 287 } 288 if (memsize < ptoa((uintmax_t)vm_cnt.v_free_count)) 289 memsize = ptoa((uintmax_t)Maxmem); 290 printf("real memory = %ju (%ju MB)\n", memsize, memsize >> 20); 291 realmem = atop(memsize); 292 293 /* 294 * Display any holes after the first chunk of extended memory. 295 */ 296 if (bootverbose) { 297 int indx; 298 299 printf("Physical memory chunk(s):\n"); 300 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) { 301 vm_paddr_t size; 302 303 size = phys_avail[indx + 1] - phys_avail[indx]; 304 printf( 305 "0x%016jx - 0x%016jx, %ju bytes (%ju pages)\n", 306 (uintmax_t)phys_avail[indx], 307 (uintmax_t)phys_avail[indx + 1] - 1, 308 (uintmax_t)size, (uintmax_t)size / PAGE_SIZE); 309 } 310 } 311 312 vm_ksubmap_init(&kmi); 313 314 printf("avail memory = %ju (%ju MB)\n", 315 ptoa((uintmax_t)vm_cnt.v_free_count), 316 ptoa((uintmax_t)vm_cnt.v_free_count) / 1048576); 317 318 /* 319 * Set up buffers, so they can be used to read disk labels. 320 */ 321 bufinit(); 322 vm_pager_bufferinit(); 323 324 cpu_setregs(); 325} 326 327/* 328 * Send an interrupt to process. 329 * 330 * Stack is set up to allow sigcode stored 331 * at top to call routine, followed by call 332 * to sigreturn routine below. After sigreturn 333 * resets the signal mask, the stack, and the 334 * frame pointer, it returns to the user 335 * specified pc, psl. 336 */ 337void 338sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask) 339{ 340 struct sigframe sf, *sfp; 341 struct pcb *pcb; 342 struct proc *p; 343 struct thread *td; 344 struct sigacts *psp; 345 char *sp; 346 struct trapframe *regs; 347 char *xfpusave; 348 size_t xfpusave_len; 349 int sig; 350 int oonstack; 351 352 td = curthread; 353 pcb = td->td_pcb; 354 p = td->td_proc; 355 PROC_LOCK_ASSERT(p, MA_OWNED); 356 sig = ksi->ksi_signo; 357 psp = p->p_sigacts; 358 mtx_assert(&psp->ps_mtx, MA_OWNED); 359 regs = td->td_frame; 360 oonstack = sigonstack(regs->tf_rsp); 361 362 if (cpu_max_ext_state_size > sizeof(struct savefpu) && use_xsave) { 363 xfpusave_len = cpu_max_ext_state_size - sizeof(struct savefpu); 364 xfpusave = __builtin_alloca(xfpusave_len); 365 } else { 366 xfpusave_len = 0; 367 xfpusave = NULL; 368 } 369 370 /* Save user context. */ 371 bzero(&sf, sizeof(sf)); 372 sf.sf_uc.uc_sigmask = *mask; 373 sf.sf_uc.uc_stack = td->td_sigstk; 374 sf.sf_uc.uc_stack.ss_flags = (td->td_pflags & TDP_ALTSTACK) 375 ? ((oonstack) ? SS_ONSTACK : 0) : SS_DISABLE; 376 sf.sf_uc.uc_mcontext.mc_onstack = (oonstack) ? 1 : 0; 377 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(*regs)); 378 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); /* magic */ 379 get_fpcontext(td, &sf.sf_uc.uc_mcontext, xfpusave, xfpusave_len); 380 fpstate_drop(td); 381 sf.sf_uc.uc_mcontext.mc_fsbase = pcb->pcb_fsbase; 382 sf.sf_uc.uc_mcontext.mc_gsbase = pcb->pcb_gsbase; 383 bzero(sf.sf_uc.uc_mcontext.mc_spare, 384 sizeof(sf.sf_uc.uc_mcontext.mc_spare)); 385 bzero(sf.sf_uc.__spare__, sizeof(sf.sf_uc.__spare__)); 386 387 /* Allocate space for the signal handler context. */ 388 if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack && 389 SIGISMEMBER(psp->ps_sigonstack, sig)) { 390 sp = td->td_sigstk.ss_sp + td->td_sigstk.ss_size; 391#if defined(COMPAT_43) 392 td->td_sigstk.ss_flags |= SS_ONSTACK; 393#endif 394 } else 395 sp = (char *)regs->tf_rsp - 128; 396 if (xfpusave != NULL) { 397 sp -= xfpusave_len; 398 sp = (char *)((unsigned long)sp & ~0x3Ful); 399 sf.sf_uc.uc_mcontext.mc_xfpustate = (register_t)sp; 400 } 401 sp -= sizeof(struct sigframe); 402 /* Align to 16 bytes. */ 403 sfp = (struct sigframe *)((unsigned long)sp & ~0xFul); 404 405 /* Translate the signal if appropriate. */ 406 if (p->p_sysent->sv_sigtbl && sig <= p->p_sysent->sv_sigsize) 407 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; 408 409 /* Build the argument list for the signal handler. */ 410 regs->tf_rdi = sig; /* arg 1 in %rdi */ 411 regs->tf_rdx = (register_t)&sfp->sf_uc; /* arg 3 in %rdx */ 412 bzero(&sf.sf_si, sizeof(sf.sf_si)); 413 if (SIGISMEMBER(psp->ps_siginfo, sig)) { 414 /* Signal handler installed with SA_SIGINFO. */ 415 regs->tf_rsi = (register_t)&sfp->sf_si; /* arg 2 in %rsi */ 416 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; 417 418 /* Fill in POSIX parts */ 419 sf.sf_si = ksi->ksi_info; 420 sf.sf_si.si_signo = sig; /* maybe a translated signal */ 421 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 422 } else { 423 /* Old FreeBSD-style arguments. */ 424 regs->tf_rsi = ksi->ksi_code; /* arg 2 in %rsi */ 425 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 426 sf.sf_ahu.sf_handler = catcher; 427 } 428 mtx_unlock(&psp->ps_mtx); 429 PROC_UNLOCK(p); 430 431 /* 432 * Copy the sigframe out to the user's stack. 433 */ 434 if (copyout(&sf, sfp, sizeof(*sfp)) != 0 || 435 (xfpusave != NULL && copyout(xfpusave, 436 (void *)sf.sf_uc.uc_mcontext.mc_xfpustate, xfpusave_len) 437 != 0)) { 438#ifdef DEBUG 439 printf("process %ld has trashed its stack\n", (long)p->p_pid); 440#endif 441 PROC_LOCK(p); 442 sigexit(td, SIGILL); 443 } 444 445 regs->tf_rsp = (long)sfp; 446 regs->tf_rip = p->p_sysent->sv_sigcode_base; 447 regs->tf_rflags &= ~(PSL_T | PSL_D); 448 regs->tf_cs = _ucodesel; 449 regs->tf_ds = _udatasel; 450 regs->tf_es = _udatasel; 451 regs->tf_fs = _ufssel; 452 regs->tf_gs = _ugssel; 453 regs->tf_flags = TF_HASSEGS; 454 set_pcb_flags(pcb, PCB_FULL_IRET); 455 PROC_LOCK(p); 456 mtx_lock(&psp->ps_mtx); 457} 458 459/* 460 * System call to cleanup state after a signal 461 * has been taken. Reset signal mask and 462 * stack state from context left by sendsig (above). 463 * Return to previous pc and psl as specified by 464 * context left by sendsig. Check carefully to 465 * make sure that the user has not modified the 466 * state to gain improper privileges. 467 * 468 * MPSAFE 469 */ 470int 471sys_sigreturn(td, uap) 472 struct thread *td; 473 struct sigreturn_args /* { 474 const struct __ucontext *sigcntxp; 475 } */ *uap; 476{ 477 ucontext_t uc; 478 struct pcb *pcb; 479 struct proc *p; 480 struct trapframe *regs; 481 ucontext_t *ucp; 482 char *xfpustate; 483 size_t xfpustate_len; 484 long rflags; 485 int cs, error, ret; 486 ksiginfo_t ksi; 487 488 pcb = td->td_pcb; 489 p = td->td_proc; 490 491 error = copyin(uap->sigcntxp, &uc, sizeof(uc)); 492 if (error != 0) { 493 uprintf("pid %d (%s): sigreturn copyin failed\n", 494 p->p_pid, td->td_name); 495 return (error); 496 } 497 ucp = &uc; 498 if ((ucp->uc_mcontext.mc_flags & ~_MC_FLAG_MASK) != 0) { 499 uprintf("pid %d (%s): sigreturn mc_flags %x\n", p->p_pid, 500 td->td_name, ucp->uc_mcontext.mc_flags); 501 return (EINVAL); 502 } 503 regs = td->td_frame; 504 rflags = ucp->uc_mcontext.mc_rflags; 505 /* 506 * Don't allow users to change privileged or reserved flags. 507 */ 508 if (!EFL_SECURE(rflags, regs->tf_rflags)) { 509 uprintf("pid %d (%s): sigreturn rflags = 0x%lx\n", p->p_pid, 510 td->td_name, rflags); 511 return (EINVAL); 512 } 513 514 /* 515 * Don't allow users to load a valid privileged %cs. Let the 516 * hardware check for invalid selectors, excess privilege in 517 * other selectors, invalid %eip's and invalid %esp's. 518 */ 519 cs = ucp->uc_mcontext.mc_cs; 520 if (!CS_SECURE(cs)) { 521 uprintf("pid %d (%s): sigreturn cs = 0x%x\n", p->p_pid, 522 td->td_name, cs); 523 ksiginfo_init_trap(&ksi); 524 ksi.ksi_signo = SIGBUS; 525 ksi.ksi_code = BUS_OBJERR; 526 ksi.ksi_trapno = T_PROTFLT; 527 ksi.ksi_addr = (void *)regs->tf_rip; 528 trapsignal(td, &ksi); 529 return (EINVAL); 530 } 531 532 if ((uc.uc_mcontext.mc_flags & _MC_HASFPXSTATE) != 0) { 533 xfpustate_len = uc.uc_mcontext.mc_xfpustate_len; 534 if (xfpustate_len > cpu_max_ext_state_size - 535 sizeof(struct savefpu)) { 536 uprintf("pid %d (%s): sigreturn xfpusave_len = 0x%zx\n", 537 p->p_pid, td->td_name, xfpustate_len); 538 return (EINVAL); 539 } 540 xfpustate = __builtin_alloca(xfpustate_len); 541 error = copyin((const void *)uc.uc_mcontext.mc_xfpustate, 542 xfpustate, xfpustate_len); 543 if (error != 0) { 544 uprintf( 545 "pid %d (%s): sigreturn copying xfpustate failed\n", 546 p->p_pid, td->td_name); 547 return (error); 548 } 549 } else { 550 xfpustate = NULL; 551 xfpustate_len = 0; 552 } 553 ret = set_fpcontext(td, &ucp->uc_mcontext, xfpustate, xfpustate_len); 554 if (ret != 0) { 555 uprintf("pid %d (%s): sigreturn set_fpcontext err %d\n", 556 p->p_pid, td->td_name, ret); 557 return (ret); 558 } 559 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(*regs)); 560 pcb->pcb_fsbase = ucp->uc_mcontext.mc_fsbase; 561 pcb->pcb_gsbase = ucp->uc_mcontext.mc_gsbase; 562 563#if defined(COMPAT_43) 564 if (ucp->uc_mcontext.mc_onstack & 1) 565 td->td_sigstk.ss_flags |= SS_ONSTACK; 566 else 567 td->td_sigstk.ss_flags &= ~SS_ONSTACK; 568#endif 569 570 kern_sigprocmask(td, SIG_SETMASK, &ucp->uc_sigmask, NULL, 0); 571 set_pcb_flags(pcb, PCB_FULL_IRET); 572 return (EJUSTRETURN); 573} 574 575#ifdef COMPAT_FREEBSD4 576int 577freebsd4_sigreturn(struct thread *td, struct freebsd4_sigreturn_args *uap) 578{ 579 580 return sys_sigreturn(td, (struct sigreturn_args *)uap); 581} 582#endif 583 584 585/* 586 * Machine dependent boot() routine 587 * 588 * I haven't seen anything to put here yet 589 * Possibly some stuff might be grafted back here from boot() 590 */ 591void 592cpu_boot(int howto) 593{ 594} 595 596/* 597 * Flush the D-cache for non-DMA I/O so that the I-cache can 598 * be made coherent later. 599 */ 600void 601cpu_flush_dcache(void *ptr, size_t len) 602{ 603 /* Not applicable */ 604} 605 606/* Get current clock frequency for the given cpu id. */ 607int 608cpu_est_clockrate(int cpu_id, uint64_t *rate) 609{ 610 uint64_t tsc1, tsc2; 611 uint64_t acnt, mcnt, perf; 612 register_t reg; 613 614 if (pcpu_find(cpu_id) == NULL || rate == NULL) 615 return (EINVAL); 616 617 /* 618 * If TSC is P-state invariant and APERF/MPERF MSRs do not exist, 619 * DELAY(9) based logic fails. 620 */ 621 if (tsc_is_invariant && !tsc_perf_stat) 622 return (EOPNOTSUPP); 623 624#ifdef SMP 625 if (smp_cpus > 1) { 626 /* Schedule ourselves on the indicated cpu. */ 627 thread_lock(curthread); 628 sched_bind(curthread, cpu_id); 629 thread_unlock(curthread); 630 } 631#endif 632 633 /* Calibrate by measuring a short delay. */ 634 reg = intr_disable(); 635 if (tsc_is_invariant) { 636 wrmsr(MSR_MPERF, 0); 637 wrmsr(MSR_APERF, 0); 638 tsc1 = rdtsc(); 639 DELAY(1000); 640 mcnt = rdmsr(MSR_MPERF); 641 acnt = rdmsr(MSR_APERF); 642 tsc2 = rdtsc(); 643 intr_restore(reg); 644 perf = 1000 * acnt / mcnt; 645 *rate = (tsc2 - tsc1) * perf; 646 } else { 647 tsc1 = rdtsc(); 648 DELAY(1000); 649 tsc2 = rdtsc(); 650 intr_restore(reg); 651 *rate = (tsc2 - tsc1) * 1000; 652 } 653 654#ifdef SMP 655 if (smp_cpus > 1) { 656 thread_lock(curthread); 657 sched_unbind(curthread); 658 thread_unlock(curthread); 659 } 660#endif 661 662 return (0); 663} 664 665/* 666 * Shutdown the CPU as much as possible 667 */ 668void 669cpu_halt(void) 670{ 671 for (;;) 672 halt(); 673} 674 675void (*cpu_idle_hook)(sbintime_t) = NULL; /* ACPI idle hook. */ 676static int cpu_ident_amdc1e = 0; /* AMD C1E supported. */ 677static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */ 678TUNABLE_INT("machdep.idle_mwait", &idle_mwait); 679SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RW, &idle_mwait, 680 0, "Use MONITOR/MWAIT for short idle"); 681 682#define STATE_RUNNING 0x0 683#define STATE_MWAIT 0x1 684#define STATE_SLEEPING 0x2 685 686static void 687cpu_idle_acpi(sbintime_t sbt) 688{ 689 int *state; 690 691 state = (int *)PCPU_PTR(monitorbuf); 692 *state = STATE_SLEEPING; 693 694 /* See comments in cpu_idle_hlt(). */ 695 disable_intr(); 696 if (sched_runnable()) 697 enable_intr(); 698 else if (cpu_idle_hook) 699 cpu_idle_hook(sbt); 700 else 701 __asm __volatile("sti; hlt"); 702 *state = STATE_RUNNING; 703} 704 705static void 706cpu_idle_hlt(sbintime_t sbt) 707{ 708 int *state; 709 710 state = (int *)PCPU_PTR(monitorbuf); 711 *state = STATE_SLEEPING; 712 713 /* 714 * Since we may be in a critical section from cpu_idle(), if 715 * an interrupt fires during that critical section we may have 716 * a pending preemption. If the CPU halts, then that thread 717 * may not execute until a later interrupt awakens the CPU. 718 * To handle this race, check for a runnable thread after 719 * disabling interrupts and immediately return if one is 720 * found. Also, we must absolutely guarentee that hlt is 721 * the next instruction after sti. This ensures that any 722 * interrupt that fires after the call to disable_intr() will 723 * immediately awaken the CPU from hlt. Finally, please note 724 * that on x86 this works fine because of interrupts enabled only 725 * after the instruction following sti takes place, while IF is set 726 * to 1 immediately, allowing hlt instruction to acknowledge the 727 * interrupt. 728 */ 729 disable_intr(); 730 if (sched_runnable()) 731 enable_intr(); 732 else 733 __asm __volatile("sti; hlt"); 734 *state = STATE_RUNNING; 735} 736 737/* 738 * MWAIT cpu power states. Lower 4 bits are sub-states. 739 */ 740#define MWAIT_C0 0xf0 741#define MWAIT_C1 0x00 742#define MWAIT_C2 0x10 743#define MWAIT_C3 0x20 744#define MWAIT_C4 0x30 745 746static void 747cpu_idle_mwait(sbintime_t sbt) 748{ 749 int *state; 750 751 state = (int *)PCPU_PTR(monitorbuf); 752 *state = STATE_MWAIT; 753 754 /* See comments in cpu_idle_hlt(). */ 755 disable_intr(); 756 if (sched_runnable()) { 757 enable_intr(); 758 *state = STATE_RUNNING; 759 return; 760 } 761 cpu_monitor(state, 0, 0); 762 if (*state == STATE_MWAIT) 763 __asm __volatile("sti; mwait" : : "a" (MWAIT_C1), "c" (0)); 764 else 765 enable_intr(); 766 *state = STATE_RUNNING; 767} 768 769static void 770cpu_idle_spin(sbintime_t sbt) 771{ 772 int *state; 773 int i; 774 775 state = (int *)PCPU_PTR(monitorbuf); 776 *state = STATE_RUNNING; 777 778 /* 779 * The sched_runnable() call is racy but as long as there is 780 * a loop missing it one time will have just a little impact if any 781 * (and it is much better than missing the check at all). 782 */ 783 for (i = 0; i < 1000; i++) { 784 if (sched_runnable()) 785 return; 786 cpu_spinwait(); 787 } 788} 789 790/* 791 * C1E renders the local APIC timer dead, so we disable it by 792 * reading the Interrupt Pending Message register and clearing 793 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27). 794 * 795 * Reference: 796 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" 797 * #32559 revision 3.00+ 798 */ 799#define MSR_AMDK8_IPM 0xc0010055 800#define AMDK8_SMIONCMPHALT (1ULL << 27) 801#define AMDK8_C1EONCMPHALT (1ULL << 28) 802#define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT) 803 804static void 805cpu_probe_amdc1e(void) 806{ 807 808 /* 809 * Detect the presence of C1E capability mostly on latest 810 * dual-cores (or future) k8 family. 811 */ 812 if (cpu_vendor_id == CPU_VENDOR_AMD && 813 (cpu_id & 0x00000f00) == 0x00000f00 && 814 (cpu_id & 0x0fff0000) >= 0x00040000) { 815 cpu_ident_amdc1e = 1; 816 } 817} 818 819void (*cpu_idle_fn)(sbintime_t) = cpu_idle_acpi; 820 821void 822cpu_idle(int busy) 823{ 824 uint64_t msr; 825 sbintime_t sbt = -1; 826 827 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d", 828 busy, curcpu); 829#ifdef MP_WATCHDOG 830 ap_watchdog(PCPU_GET(cpuid)); 831#endif 832 /* If we are busy - try to use fast methods. */ 833 if (busy) { 834 if ((cpu_feature2 & CPUID2_MON) && idle_mwait) { 835 cpu_idle_mwait(busy); 836 goto out; 837 } 838 } 839 840 /* If we have time - switch timers into idle mode. */ 841 if (!busy) { 842 critical_enter(); 843 sbt = cpu_idleclock(); 844 } 845 846 /* Apply AMD APIC timer C1E workaround. */ 847 if (cpu_ident_amdc1e && cpu_disable_deep_sleep) { 848 msr = rdmsr(MSR_AMDK8_IPM); 849 if (msr & AMDK8_CMPHALT) 850 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT); 851 } 852 853 /* Call main idle method. */ 854 cpu_idle_fn(sbt); 855 856 /* Switch timers back into active mode. */ 857 if (!busy) { 858 cpu_activeclock(); 859 critical_exit(); 860 } 861out: 862 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done", 863 busy, curcpu); 864} 865 866int 867cpu_idle_wakeup(int cpu) 868{ 869 struct pcpu *pcpu; 870 int *state; 871 872 pcpu = pcpu_find(cpu); 873 state = (int *)pcpu->pc_monitorbuf; 874 /* 875 * This doesn't need to be atomic since missing the race will 876 * simply result in unnecessary IPIs. 877 */ 878 if (*state == STATE_SLEEPING) 879 return (0); 880 if (*state == STATE_MWAIT) 881 *state = STATE_RUNNING; 882 return (1); 883} 884 885/* 886 * Ordered by speed/power consumption. 887 */ 888struct { 889 void *id_fn; 890 char *id_name; 891} idle_tbl[] = { 892 { cpu_idle_spin, "spin" }, 893 { cpu_idle_mwait, "mwait" }, 894 { cpu_idle_hlt, "hlt" }, 895 { cpu_idle_acpi, "acpi" }, 896 { NULL, NULL } 897}; 898 899static int 900idle_sysctl_available(SYSCTL_HANDLER_ARGS) 901{ 902 char *avail, *p; 903 int error; 904 int i; 905 906 avail = malloc(256, M_TEMP, M_WAITOK); 907 p = avail; 908 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 909 if (strstr(idle_tbl[i].id_name, "mwait") && 910 (cpu_feature2 & CPUID2_MON) == 0) 911 continue; 912 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 913 cpu_idle_hook == NULL) 914 continue; 915 p += sprintf(p, "%s%s", p != avail ? ", " : "", 916 idle_tbl[i].id_name); 917 } 918 error = sysctl_handle_string(oidp, avail, 0, req); 919 free(avail, M_TEMP); 920 return (error); 921} 922 923SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD, 924 0, 0, idle_sysctl_available, "A", "list of available idle functions"); 925 926static int 927idle_sysctl(SYSCTL_HANDLER_ARGS) 928{ 929 char buf[16]; 930 int error; 931 char *p; 932 int i; 933 934 p = "unknown"; 935 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 936 if (idle_tbl[i].id_fn == cpu_idle_fn) { 937 p = idle_tbl[i].id_name; 938 break; 939 } 940 } 941 strncpy(buf, p, sizeof(buf)); 942 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 943 if (error != 0 || req->newptr == NULL) 944 return (error); 945 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 946 if (strstr(idle_tbl[i].id_name, "mwait") && 947 (cpu_feature2 & CPUID2_MON) == 0) 948 continue; 949 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 950 cpu_idle_hook == NULL) 951 continue; 952 if (strcmp(idle_tbl[i].id_name, buf)) 953 continue; 954 cpu_idle_fn = idle_tbl[i].id_fn; 955 return (0); 956 } 957 return (EINVAL); 958} 959 960SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0, 961 idle_sysctl, "A", "currently selected idle function"); 962 963/* 964 * Reset registers to default values on exec. 965 */ 966void 967exec_setregs(struct thread *td, struct image_params *imgp, u_long stack) 968{ 969 struct trapframe *regs = td->td_frame; 970 struct pcb *pcb = td->td_pcb; 971 972 mtx_lock(&dt_lock); 973 if (td->td_proc->p_md.md_ldt != NULL) 974 user_ldt_free(td); 975 else 976 mtx_unlock(&dt_lock); 977 978 pcb->pcb_fsbase = 0; 979 pcb->pcb_gsbase = 0; 980 clear_pcb_flags(pcb, PCB_32BIT); 981 pcb->pcb_initial_fpucw = __INITIAL_FPUCW__; 982 set_pcb_flags(pcb, PCB_FULL_IRET); 983 984 bzero((char *)regs, sizeof(struct trapframe)); 985 regs->tf_rip = imgp->entry_addr; 986 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; 987 regs->tf_rdi = stack; /* argv */ 988 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T); 989 regs->tf_ss = _udatasel; 990 regs->tf_cs = _ucodesel; 991 regs->tf_ds = _udatasel; 992 regs->tf_es = _udatasel; 993 regs->tf_fs = _ufssel; 994 regs->tf_gs = _ugssel; 995 regs->tf_flags = TF_HASSEGS; 996 td->td_retval[1] = 0; 997 998 /* 999 * Reset the hardware debug registers if they were in use. 1000 * They won't have any meaning for the newly exec'd process. 1001 */ 1002 if (pcb->pcb_flags & PCB_DBREGS) { 1003 pcb->pcb_dr0 = 0; 1004 pcb->pcb_dr1 = 0; 1005 pcb->pcb_dr2 = 0; 1006 pcb->pcb_dr3 = 0; 1007 pcb->pcb_dr6 = 0; 1008 pcb->pcb_dr7 = 0; 1009 if (pcb == curpcb) { 1010 /* 1011 * Clear the debug registers on the running 1012 * CPU, otherwise they will end up affecting 1013 * the next process we switch to. 1014 */ 1015 reset_dbregs(); 1016 } 1017 clear_pcb_flags(pcb, PCB_DBREGS); 1018 } 1019 1020 /* 1021 * Drop the FP state if we hold it, so that the process gets a 1022 * clean FP state if it uses the FPU again. 1023 */ 1024 fpstate_drop(td); 1025} 1026 1027void 1028cpu_setregs(void) 1029{ 1030 register_t cr0; 1031 1032 cr0 = rcr0(); 1033 /* 1034 * CR0_MP, CR0_NE and CR0_TS are also set by npx_probe() for the 1035 * BSP. See the comments there about why we set them. 1036 */ 1037 cr0 |= CR0_MP | CR0_NE | CR0_TS | CR0_WP | CR0_AM; 1038 load_cr0(cr0); 1039} 1040 1041/* 1042 * Initialize amd64 and configure to run kernel 1043 */ 1044 1045/* 1046 * Initialize segments & interrupt table 1047 */ 1048 1049struct user_segment_descriptor gdt[NGDT * MAXCPU];/* global descriptor tables */ 1050static struct gate_descriptor idt0[NIDT]; 1051struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */ 1052 1053static char dblfault_stack[PAGE_SIZE] __aligned(16); 1054 1055static char nmi0_stack[PAGE_SIZE] __aligned(16); 1056CTASSERT(sizeof(struct nmi_pcpu) == 16); 1057 1058struct amd64tss common_tss[MAXCPU]; 1059 1060/* 1061 * Software prototypes -- in more palatable form. 1062 * 1063 * Keep GUFS32, GUGS32, GUCODE32 and GUDATA at the same 1064 * slots as corresponding segments for i386 kernel. 1065 */ 1066struct soft_segment_descriptor gdt_segs[] = { 1067/* GNULL_SEL 0 Null Descriptor */ 1068{ .ssd_base = 0x0, 1069 .ssd_limit = 0x0, 1070 .ssd_type = 0, 1071 .ssd_dpl = 0, 1072 .ssd_p = 0, 1073 .ssd_long = 0, 1074 .ssd_def32 = 0, 1075 .ssd_gran = 0 }, 1076/* GNULL2_SEL 1 Null Descriptor */ 1077{ .ssd_base = 0x0, 1078 .ssd_limit = 0x0, 1079 .ssd_type = 0, 1080 .ssd_dpl = 0, 1081 .ssd_p = 0, 1082 .ssd_long = 0, 1083 .ssd_def32 = 0, 1084 .ssd_gran = 0 }, 1085/* GUFS32_SEL 2 32 bit %gs Descriptor for user */ 1086{ .ssd_base = 0x0, 1087 .ssd_limit = 0xfffff, 1088 .ssd_type = SDT_MEMRWA, 1089 .ssd_dpl = SEL_UPL, 1090 .ssd_p = 1, 1091 .ssd_long = 0, 1092 .ssd_def32 = 1, 1093 .ssd_gran = 1 }, 1094/* GUGS32_SEL 3 32 bit %fs Descriptor for user */ 1095{ .ssd_base = 0x0, 1096 .ssd_limit = 0xfffff, 1097 .ssd_type = SDT_MEMRWA, 1098 .ssd_dpl = SEL_UPL, 1099 .ssd_p = 1, 1100 .ssd_long = 0, 1101 .ssd_def32 = 1, 1102 .ssd_gran = 1 }, 1103/* GCODE_SEL 4 Code Descriptor for kernel */ 1104{ .ssd_base = 0x0, 1105 .ssd_limit = 0xfffff, 1106 .ssd_type = SDT_MEMERA, 1107 .ssd_dpl = SEL_KPL, 1108 .ssd_p = 1, 1109 .ssd_long = 1, 1110 .ssd_def32 = 0, 1111 .ssd_gran = 1 }, 1112/* GDATA_SEL 5 Data Descriptor for kernel */ 1113{ .ssd_base = 0x0, 1114 .ssd_limit = 0xfffff, 1115 .ssd_type = SDT_MEMRWA, 1116 .ssd_dpl = SEL_KPL, 1117 .ssd_p = 1, 1118 .ssd_long = 1, 1119 .ssd_def32 = 0, 1120 .ssd_gran = 1 }, 1121/* GUCODE32_SEL 6 32 bit Code Descriptor for user */ 1122{ .ssd_base = 0x0, 1123 .ssd_limit = 0xfffff, 1124 .ssd_type = SDT_MEMERA, 1125 .ssd_dpl = SEL_UPL, 1126 .ssd_p = 1, 1127 .ssd_long = 0, 1128 .ssd_def32 = 1, 1129 .ssd_gran = 1 }, 1130/* GUDATA_SEL 7 32/64 bit Data Descriptor for user */ 1131{ .ssd_base = 0x0, 1132 .ssd_limit = 0xfffff, 1133 .ssd_type = SDT_MEMRWA, 1134 .ssd_dpl = SEL_UPL, 1135 .ssd_p = 1, 1136 .ssd_long = 0, 1137 .ssd_def32 = 1, 1138 .ssd_gran = 1 }, 1139/* GUCODE_SEL 8 64 bit Code Descriptor for user */ 1140{ .ssd_base = 0x0, 1141 .ssd_limit = 0xfffff, 1142 .ssd_type = SDT_MEMERA, 1143 .ssd_dpl = SEL_UPL, 1144 .ssd_p = 1, 1145 .ssd_long = 1, 1146 .ssd_def32 = 0, 1147 .ssd_gran = 1 }, 1148/* GPROC0_SEL 9 Proc 0 Tss Descriptor */ 1149{ .ssd_base = 0x0, 1150 .ssd_limit = sizeof(struct amd64tss) + IOPERM_BITMAP_SIZE - 1, 1151 .ssd_type = SDT_SYSTSS, 1152 .ssd_dpl = SEL_KPL, 1153 .ssd_p = 1, 1154 .ssd_long = 0, 1155 .ssd_def32 = 0, 1156 .ssd_gran = 0 }, 1157/* Actually, the TSS is a system descriptor which is double size */ 1158{ .ssd_base = 0x0, 1159 .ssd_limit = 0x0, 1160 .ssd_type = 0, 1161 .ssd_dpl = 0, 1162 .ssd_p = 0, 1163 .ssd_long = 0, 1164 .ssd_def32 = 0, 1165 .ssd_gran = 0 }, 1166/* GUSERLDT_SEL 11 LDT Descriptor */ 1167{ .ssd_base = 0x0, 1168 .ssd_limit = 0x0, 1169 .ssd_type = 0, 1170 .ssd_dpl = 0, 1171 .ssd_p = 0, 1172 .ssd_long = 0, 1173 .ssd_def32 = 0, 1174 .ssd_gran = 0 }, 1175/* GUSERLDT_SEL 12 LDT Descriptor, double size */ 1176{ .ssd_base = 0x0, 1177 .ssd_limit = 0x0, 1178 .ssd_type = 0, 1179 .ssd_dpl = 0, 1180 .ssd_p = 0, 1181 .ssd_long = 0, 1182 .ssd_def32 = 0, 1183 .ssd_gran = 0 }, 1184}; 1185 1186void 1187setidt(idx, func, typ, dpl, ist) 1188 int idx; 1189 inthand_t *func; 1190 int typ; 1191 int dpl; 1192 int ist; 1193{ 1194 struct gate_descriptor *ip; 1195 1196 ip = idt + idx; 1197 ip->gd_looffset = (uintptr_t)func; 1198 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1199 ip->gd_ist = ist; 1200 ip->gd_xx = 0; 1201 ip->gd_type = typ; 1202 ip->gd_dpl = dpl; 1203 ip->gd_p = 1; 1204 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1205} 1206 1207extern inthand_t 1208 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 1209 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 1210 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 1211 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 1212 IDTVEC(xmm), IDTVEC(dblfault), 1213#ifdef KDTRACE_HOOKS 1214 IDTVEC(dtrace_ret), 1215#endif 1216#ifdef XENHVM 1217 IDTVEC(xen_intr_upcall), 1218#endif 1219 IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 1220 1221#ifdef DDB 1222/* 1223 * Display the index and function name of any IDT entries that don't use 1224 * the default 'rsvd' entry point. 1225 */ 1226DB_SHOW_COMMAND(idt, db_show_idt) 1227{ 1228 struct gate_descriptor *ip; 1229 int idx; 1230 uintptr_t func; 1231 1232 ip = idt; 1233 for (idx = 0; idx < NIDT && !db_pager_quit; idx++) { 1234 func = ((long)ip->gd_hioffset << 16 | ip->gd_looffset); 1235 if (func != (uintptr_t)&IDTVEC(rsvd)) { 1236 db_printf("%3d\t", idx); 1237 db_printsym(func, DB_STGY_PROC); 1238 db_printf("\n"); 1239 } 1240 ip++; 1241 } 1242} 1243 1244/* Show privileged registers. */ 1245DB_SHOW_COMMAND(sysregs, db_show_sysregs) 1246{ 1247 struct { 1248 uint16_t limit; 1249 uint64_t base; 1250 } __packed idtr, gdtr; 1251 uint16_t ldt, tr; 1252 1253 __asm __volatile("sidt %0" : "=m" (idtr)); 1254 db_printf("idtr\t0x%016lx/%04x\n", 1255 (u_long)idtr.base, (u_int)idtr.limit); 1256 __asm __volatile("sgdt %0" : "=m" (gdtr)); 1257 db_printf("gdtr\t0x%016lx/%04x\n", 1258 (u_long)gdtr.base, (u_int)gdtr.limit); 1259 __asm __volatile("sldt %0" : "=r" (ldt)); 1260 db_printf("ldtr\t0x%04x\n", ldt); 1261 __asm __volatile("str %0" : "=r" (tr)); 1262 db_printf("tr\t0x%04x\n", tr); 1263 db_printf("cr0\t0x%016lx\n", rcr0()); 1264 db_printf("cr2\t0x%016lx\n", rcr2()); 1265 db_printf("cr3\t0x%016lx\n", rcr3()); 1266 db_printf("cr4\t0x%016lx\n", rcr4()); 1267 db_printf("EFER\t%016lx\n", rdmsr(MSR_EFER)); 1268 db_printf("FEATURES_CTL\t%016lx\n", rdmsr(MSR_IA32_FEATURE_CONTROL)); 1269 db_printf("DEBUG_CTL\t%016lx\n", rdmsr(MSR_DEBUGCTLMSR)); 1270 db_printf("PAT\t%016lx\n", rdmsr(MSR_PAT)); 1271 db_printf("GSBASE\t%016lx\n", rdmsr(MSR_GSBASE)); 1272} 1273#endif 1274 1275void 1276sdtossd(sd, ssd) 1277 struct user_segment_descriptor *sd; 1278 struct soft_segment_descriptor *ssd; 1279{ 1280 1281 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 1282 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 1283 ssd->ssd_type = sd->sd_type; 1284 ssd->ssd_dpl = sd->sd_dpl; 1285 ssd->ssd_p = sd->sd_p; 1286 ssd->ssd_long = sd->sd_long; 1287 ssd->ssd_def32 = sd->sd_def32; 1288 ssd->ssd_gran = sd->sd_gran; 1289} 1290 1291void 1292ssdtosd(ssd, sd) 1293 struct soft_segment_descriptor *ssd; 1294 struct user_segment_descriptor *sd; 1295{ 1296 1297 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1298 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff; 1299 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1300 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1301 sd->sd_type = ssd->ssd_type; 1302 sd->sd_dpl = ssd->ssd_dpl; 1303 sd->sd_p = ssd->ssd_p; 1304 sd->sd_long = ssd->ssd_long; 1305 sd->sd_def32 = ssd->ssd_def32; 1306 sd->sd_gran = ssd->ssd_gran; 1307} 1308 1309void 1310ssdtosyssd(ssd, sd) 1311 struct soft_segment_descriptor *ssd; 1312 struct system_segment_descriptor *sd; 1313{ 1314 1315 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1316 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful; 1317 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1318 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1319 sd->sd_type = ssd->ssd_type; 1320 sd->sd_dpl = ssd->ssd_dpl; 1321 sd->sd_p = ssd->ssd_p; 1322 sd->sd_gran = ssd->ssd_gran; 1323} 1324 1325#if !defined(DEV_ATPIC) && defined(DEV_ISA) 1326#include <isa/isavar.h> 1327#include <isa/isareg.h> 1328/* 1329 * Return a bitmap of the current interrupt requests. This is 8259-specific 1330 * and is only suitable for use at probe time. 1331 * This is only here to pacify sio. It is NOT FATAL if this doesn't work. 1332 * It shouldn't be here. There should probably be an APIC centric 1333 * implementation in the apic driver code, if at all. 1334 */ 1335intrmask_t 1336isa_irq_pending(void) 1337{ 1338 u_char irr1; 1339 u_char irr2; 1340 1341 irr1 = inb(IO_ICU1); 1342 irr2 = inb(IO_ICU2); 1343 return ((irr2 << 8) | irr1); 1344} 1345#endif 1346 1347u_int basemem; 1348 1349static int 1350add_physmap_entry(uint64_t base, uint64_t length, vm_paddr_t *physmap, 1351 int *physmap_idxp) 1352{ 1353 int i, insert_idx, physmap_idx; 1354 1355 physmap_idx = *physmap_idxp; 1356 1357 if (length == 0) 1358 return (1); 1359 1360 /* 1361 * Find insertion point while checking for overlap. Start off by 1362 * assuming the new entry will be added to the end. 1363 */ 1364 insert_idx = physmap_idx + 2; 1365 for (i = 0; i <= physmap_idx; i += 2) { 1366 if (base < physmap[i + 1]) { 1367 if (base + length <= physmap[i]) { 1368 insert_idx = i; 1369 break; 1370 } 1371 if (boothowto & RB_VERBOSE) 1372 printf( 1373 "Overlapping memory regions, ignoring second region\n"); 1374 return (1); 1375 } 1376 } 1377 1378 /* See if we can prepend to the next entry. */ 1379 if (insert_idx <= physmap_idx && base + length == physmap[insert_idx]) { 1380 physmap[insert_idx] = base; 1381 return (1); 1382 } 1383 1384 /* See if we can append to the previous entry. */ 1385 if (insert_idx > 0 && base == physmap[insert_idx - 1]) { 1386 physmap[insert_idx - 1] += length; 1387 return (1); 1388 } 1389 1390 physmap_idx += 2; 1391 *physmap_idxp = physmap_idx; 1392 if (physmap_idx == PHYSMAP_SIZE) { 1393 printf( 1394 "Too many segments in the physical address map, giving up\n"); 1395 return (0); 1396 } 1397 1398 /* 1399 * Move the last 'N' entries down to make room for the new 1400 * entry if needed. 1401 */ 1402 for (i = physmap_idx; i > insert_idx; i -= 2) { 1403 physmap[i] = physmap[i - 2]; 1404 physmap[i + 1] = physmap[i - 1]; 1405 } 1406 1407 /* Insert the new entry. */ 1408 physmap[insert_idx] = base; 1409 physmap[insert_idx + 1] = base + length; 1410 return (1); 1411} 1412 1413void 1414bios_add_smap_entries(struct bios_smap *smapbase, u_int32_t smapsize, 1415 vm_paddr_t *physmap, int *physmap_idx) 1416{ 1417 struct bios_smap *smap, *smapend; 1418 1419 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 1420 1421 for (smap = smapbase; smap < smapend; smap++) { 1422 if (boothowto & RB_VERBOSE) 1423 printf("SMAP type=%02x base=%016lx len=%016lx\n", 1424 smap->type, smap->base, smap->length); 1425 1426 if (smap->type != SMAP_TYPE_MEMORY) 1427 continue; 1428 1429 if (!add_physmap_entry(smap->base, smap->length, physmap, 1430 physmap_idx)) 1431 break; 1432 } 1433} 1434 1435#define efi_next_descriptor(ptr, size) \ 1436 ((struct efi_md *)(((uint8_t *) ptr) + size)) 1437 1438static void 1439add_efi_map_entries(struct efi_map_header *efihdr, vm_paddr_t *physmap, 1440 int *physmap_idx) 1441{ 1442 struct efi_md *map, *p; 1443 const char *type; 1444 size_t efisz; 1445 int ndesc, i; 1446 1447 static const char *types[] = { 1448 "Reserved", 1449 "LoaderCode", 1450 "LoaderData", 1451 "BootServicesCode", 1452 "BootServicesData", 1453 "RuntimeServicesCode", 1454 "RuntimeServicesData", 1455 "ConventionalMemory", 1456 "UnusableMemory", 1457 "ACPIReclaimMemory", 1458 "ACPIMemoryNVS", 1459 "MemoryMappedIO", 1460 "MemoryMappedIOPortSpace", 1461 "PalCode" 1462 }; 1463 1464 /* 1465 * Memory map data provided by UEFI via the GetMemoryMap 1466 * Boot Services API. 1467 */ 1468 efisz = (sizeof(struct efi_map_header) + 0xf) & ~0xf; 1469 map = (struct efi_md *)((uint8_t *)efihdr + efisz); 1470 1471 if (efihdr->descriptor_size == 0) 1472 return; 1473 ndesc = efihdr->memory_size / efihdr->descriptor_size; 1474 1475 if (boothowto & RB_VERBOSE) 1476 printf("%23s %12s %12s %8s %4s\n", 1477 "Type", "Physical", "Virtual", "#Pages", "Attr"); 1478 1479 for (i = 0, p = map; i < ndesc; i++, 1480 p = efi_next_descriptor(p, efihdr->descriptor_size)) { 1481 if (boothowto & RB_VERBOSE) { 1482 if (p->md_type <= EFI_MD_TYPE_PALCODE) 1483 type = types[p->md_type]; 1484 else 1485 type = "<INVALID>"; 1486 printf("%23s %012lx %12p %08lx ", type, p->md_phys, 1487 p->md_virt, p->md_pages); 1488 if (p->md_attr & EFI_MD_ATTR_UC) 1489 printf("UC "); 1490 if (p->md_attr & EFI_MD_ATTR_WC) 1491 printf("WC "); 1492 if (p->md_attr & EFI_MD_ATTR_WT) 1493 printf("WT "); 1494 if (p->md_attr & EFI_MD_ATTR_WB) 1495 printf("WB "); 1496 if (p->md_attr & EFI_MD_ATTR_UCE) 1497 printf("UCE "); 1498 if (p->md_attr & EFI_MD_ATTR_WP) 1499 printf("WP "); 1500 if (p->md_attr & EFI_MD_ATTR_RP) 1501 printf("RP "); 1502 if (p->md_attr & EFI_MD_ATTR_XP) 1503 printf("XP "); 1504 if (p->md_attr & EFI_MD_ATTR_RT) 1505 printf("RUNTIME"); 1506 printf("\n"); 1507 } 1508 1509 switch (p->md_type) { 1510 case EFI_MD_TYPE_CODE: 1511 case EFI_MD_TYPE_DATA: 1512 case EFI_MD_TYPE_BS_CODE: 1513 case EFI_MD_TYPE_BS_DATA: 1514 case EFI_MD_TYPE_FREE: 1515 /* 1516 * We're allowed to use any entry with these types. 1517 */ 1518 break; 1519 default: 1520 continue; 1521 } 1522 1523 if (!add_physmap_entry(p->md_phys, (p->md_pages * PAGE_SIZE), 1524 physmap, physmap_idx)) 1525 break; 1526 } 1527} 1528 1529static char bootmethod[16] = ""; 1530SYSCTL_STRING(_machdep, OID_AUTO, bootmethod, CTLFLAG_RD, bootmethod, 0, 1531 "System firmware boot method"); 1532 1533static void 1534native_parse_memmap(caddr_t kmdp, vm_paddr_t *physmap, int *physmap_idx) 1535{ 1536 struct bios_smap *smap; 1537 struct efi_map_header *efihdr; 1538 u_int32_t size; 1539 1540 /* 1541 * Memory map from INT 15:E820. 1542 * 1543 * subr_module.c says: 1544 * "Consumer may safely assume that size value precedes data." 1545 * ie: an int32_t immediately precedes smap. 1546 */ 1547 1548 efihdr = (struct efi_map_header *)preload_search_info(kmdp, 1549 MODINFO_METADATA | MODINFOMD_EFI_MAP); 1550 smap = (struct bios_smap *)preload_search_info(kmdp, 1551 MODINFO_METADATA | MODINFOMD_SMAP); 1552 if (efihdr == NULL && smap == NULL) 1553 panic("No BIOS smap or EFI map info from loader!"); 1554 1555 if (efihdr != NULL) { 1556 add_efi_map_entries(efihdr, physmap, physmap_idx); 1557 strlcpy(bootmethod, "UEFI", sizeof(bootmethod)); 1558 } else { 1559 size = *((u_int32_t *)smap - 1); 1560 bios_add_smap_entries(smap, size, physmap, physmap_idx); 1561 strlcpy(bootmethod, "BIOS", sizeof(bootmethod)); 1562 } 1563} 1564 1565/* 1566 * Populate the (physmap) array with base/bound pairs describing the 1567 * available physical memory in the system, then test this memory and 1568 * build the phys_avail array describing the actually-available memory. 1569 * 1570 * Total memory size may be set by the kernel environment variable 1571 * hw.physmem or the compile-time define MAXMEM. 1572 * 1573 * XXX first should be vm_paddr_t. 1574 */ 1575static void 1576getmemsize(caddr_t kmdp, u_int64_t first) 1577{ 1578 int i, physmap_idx, pa_indx, da_indx; 1579 vm_paddr_t pa, physmap[PHYSMAP_SIZE]; 1580 u_long physmem_start, physmem_tunable, memtest; 1581 pt_entry_t *pte; 1582 quad_t dcons_addr, dcons_size; 1583 1584 bzero(physmap, sizeof(physmap)); 1585 basemem = 0; 1586 physmap_idx = 0; 1587 1588 init_ops.parse_memmap(kmdp, physmap, &physmap_idx); 1589 1590 /* 1591 * Find the 'base memory' segment for SMP 1592 */ 1593 basemem = 0; 1594 for (i = 0; i <= physmap_idx; i += 2) { 1595 if (physmap[i] == 0x00000000) { 1596 basemem = physmap[i + 1] / 1024; 1597 break; 1598 } 1599 } 1600 if (basemem == 0) 1601 panic("BIOS smap did not include a basemem segment!"); 1602 1603 /* 1604 * Make hole for "AP -> long mode" bootstrap code. The 1605 * mp_bootaddress vector is only available when the kernel 1606 * is configured to support APs and APs for the system start 1607 * in 32bit mode (e.g. SMP bare metal). 1608 */ 1609 if (init_ops.mp_bootaddress) 1610 physmap[1] = init_ops.mp_bootaddress(physmap[1] / 1024); 1611 1612 /* 1613 * Maxmem isn't the "maximum memory", it's one larger than the 1614 * highest page of the physical address space. It should be 1615 * called something like "Maxphyspage". We may adjust this 1616 * based on ``hw.physmem'' and the results of the memory test. 1617 */ 1618 Maxmem = atop(physmap[physmap_idx + 1]); 1619 1620#ifdef MAXMEM 1621 Maxmem = MAXMEM / 4; 1622#endif 1623 1624 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable)) 1625 Maxmem = atop(physmem_tunable); 1626 1627 /* 1628 * The boot memory test is disabled by default, as it takes a 1629 * significant amount of time on large-memory systems, and is 1630 * unfriendly to virtual machines as it unnecessarily touches all 1631 * pages. 1632 * 1633 * A general name is used as the code may be extended to support 1634 * additional tests beyond the current "page present" test. 1635 */ 1636 memtest = 0; 1637 TUNABLE_ULONG_FETCH("hw.memtest.tests", &memtest); 1638 1639 /* 1640 * Don't allow MAXMEM or hw.physmem to extend the amount of memory 1641 * in the system. 1642 */ 1643 if (Maxmem > atop(physmap[physmap_idx + 1])) 1644 Maxmem = atop(physmap[physmap_idx + 1]); 1645 1646 if (atop(physmap[physmap_idx + 1]) != Maxmem && 1647 (boothowto & RB_VERBOSE)) 1648 printf("Physical memory use set to %ldK\n", Maxmem * 4); 1649 1650 /* call pmap initialization to make new kernel address space */ 1651 pmap_bootstrap(&first); 1652 1653 /* 1654 * Size up each available chunk of physical memory. 1655 * 1656 * XXX Some BIOSes corrupt low 64KB between suspend and resume. 1657 * By default, mask off the first 16 pages unless we appear to be 1658 * running in a VM. 1659 */ 1660 physmem_start = (vm_guest > VM_GUEST_NO ? 1 : 16) << PAGE_SHIFT; 1661 TUNABLE_ULONG_FETCH("hw.physmem.start", &physmem_start); 1662 if (physmem_start < PAGE_SIZE) 1663 physmap[0] = PAGE_SIZE; 1664 else if (physmem_start >= physmap[1]) 1665 physmap[0] = round_page(physmap[1] - PAGE_SIZE); 1666 else 1667 physmap[0] = round_page(physmem_start); 1668 pa_indx = 0; 1669 da_indx = 1; 1670 phys_avail[pa_indx++] = physmap[0]; 1671 phys_avail[pa_indx] = physmap[0]; 1672 dump_avail[da_indx] = physmap[0]; 1673 pte = CMAP1; 1674 1675 /* 1676 * Get dcons buffer address 1677 */ 1678 if (getenv_quad("dcons.addr", &dcons_addr) == 0 || 1679 getenv_quad("dcons.size", &dcons_size) == 0) 1680 dcons_addr = 0; 1681 1682 /* 1683 * physmap is in bytes, so when converting to page boundaries, 1684 * round up the start address and round down the end address. 1685 */ 1686 for (i = 0; i <= physmap_idx; i += 2) { 1687 vm_paddr_t end; 1688 1689 end = ptoa((vm_paddr_t)Maxmem); 1690 if (physmap[i + 1] < end) 1691 end = trunc_page(physmap[i + 1]); 1692 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) { 1693 int tmp, page_bad, full; 1694 int *ptr = (int *)CADDR1; 1695 1696 full = FALSE; 1697 /* 1698 * block out kernel memory as not available. 1699 */ 1700 if (pa >= (vm_paddr_t)kernphys && pa < first) 1701 goto do_dump_avail; 1702 1703 /* 1704 * block out dcons buffer 1705 */ 1706 if (dcons_addr > 0 1707 && pa >= trunc_page(dcons_addr) 1708 && pa < dcons_addr + dcons_size) 1709 goto do_dump_avail; 1710 1711 page_bad = FALSE; 1712 if (memtest == 0) 1713 goto skip_memtest; 1714 1715 /* 1716 * map page into kernel: valid, read/write,non-cacheable 1717 */ 1718 *pte = pa | PG_V | PG_RW | PG_NC_PWT | PG_NC_PCD; 1719 invltlb(); 1720 1721 tmp = *(int *)ptr; 1722 /* 1723 * Test for alternating 1's and 0's 1724 */ 1725 *(volatile int *)ptr = 0xaaaaaaaa; 1726 if (*(volatile int *)ptr != 0xaaaaaaaa) 1727 page_bad = TRUE; 1728 /* 1729 * Test for alternating 0's and 1's 1730 */ 1731 *(volatile int *)ptr = 0x55555555; 1732 if (*(volatile int *)ptr != 0x55555555) 1733 page_bad = TRUE; 1734 /* 1735 * Test for all 1's 1736 */ 1737 *(volatile int *)ptr = 0xffffffff; 1738 if (*(volatile int *)ptr != 0xffffffff) 1739 page_bad = TRUE; 1740 /* 1741 * Test for all 0's 1742 */ 1743 *(volatile int *)ptr = 0x0; 1744 if (*(volatile int *)ptr != 0x0) 1745 page_bad = TRUE; 1746 /* 1747 * Restore original value. 1748 */ 1749 *(int *)ptr = tmp; 1750 1751skip_memtest: 1752 /* 1753 * Adjust array of valid/good pages. 1754 */ 1755 if (page_bad == TRUE) 1756 continue; 1757 /* 1758 * If this good page is a continuation of the 1759 * previous set of good pages, then just increase 1760 * the end pointer. Otherwise start a new chunk. 1761 * Note that "end" points one higher than end, 1762 * making the range >= start and < end. 1763 * If we're also doing a speculative memory 1764 * test and we at or past the end, bump up Maxmem 1765 * so that we keep going. The first bad page 1766 * will terminate the loop. 1767 */ 1768 if (phys_avail[pa_indx] == pa) { 1769 phys_avail[pa_indx] += PAGE_SIZE; 1770 } else { 1771 pa_indx++; 1772 if (pa_indx == PHYS_AVAIL_ARRAY_END) { 1773 printf( 1774 "Too many holes in the physical address space, giving up\n"); 1775 pa_indx--; 1776 full = TRUE; 1777 goto do_dump_avail; 1778 } 1779 phys_avail[pa_indx++] = pa; /* start */ 1780 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */ 1781 } 1782 physmem++; 1783do_dump_avail: 1784 if (dump_avail[da_indx] == pa) { 1785 dump_avail[da_indx] += PAGE_SIZE; 1786 } else { 1787 da_indx++; 1788 if (da_indx == DUMP_AVAIL_ARRAY_END) { 1789 da_indx--; 1790 goto do_next; 1791 } 1792 dump_avail[da_indx++] = pa; /* start */ 1793 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */ 1794 } 1795do_next: 1796 if (full) 1797 break; 1798 } 1799 } 1800 *pte = 0; 1801 invltlb(); 1802 1803 /* 1804 * XXX 1805 * The last chunk must contain at least one page plus the message 1806 * buffer to avoid complicating other code (message buffer address 1807 * calculation, etc.). 1808 */ 1809 while (phys_avail[pa_indx - 1] + PAGE_SIZE + 1810 round_page(msgbufsize) >= phys_avail[pa_indx]) { 1811 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]); 1812 phys_avail[pa_indx--] = 0; 1813 phys_avail[pa_indx--] = 0; 1814 } 1815 1816 Maxmem = atop(phys_avail[pa_indx]); 1817 1818 /* Trim off space for the message buffer. */ 1819 phys_avail[pa_indx] -= round_page(msgbufsize); 1820 1821 /* Map the message buffer. */ 1822 msgbufp = (struct msgbuf *)PHYS_TO_DMAP(phys_avail[pa_indx]); 1823} 1824 1825static caddr_t 1826native_parse_preload_data(u_int64_t modulep) 1827{ 1828 caddr_t kmdp; 1829 1830 preload_metadata = (caddr_t)(uintptr_t)(modulep + KERNBASE); 1831 preload_bootstrap_relocate(KERNBASE); 1832 kmdp = preload_search_by_type("elf kernel"); 1833 if (kmdp == NULL) 1834 kmdp = preload_search_by_type("elf64 kernel"); 1835 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 1836 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + KERNBASE; 1837#ifdef DDB 1838 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 1839 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 1840#endif 1841 1842 return (kmdp); 1843} 1844 1845u_int64_t 1846hammer_time(u_int64_t modulep, u_int64_t physfree) 1847{ 1848 caddr_t kmdp; 1849 int gsel_tss, x; 1850 struct pcpu *pc; 1851 struct nmi_pcpu *np; 1852 struct xstate_hdr *xhdr; 1853 u_int64_t msr; 1854 char *env; 1855 size_t kstack0_sz; 1856 1857 thread0.td_kstack = physfree + KERNBASE; 1858 thread0.td_kstack_pages = KSTACK_PAGES; 1859 kstack0_sz = thread0.td_kstack_pages * PAGE_SIZE; 1860 bzero((void *)thread0.td_kstack, kstack0_sz); 1861 physfree += kstack0_sz; 1862 1863 /* 1864 * This may be done better later if it gets more high level 1865 * components in it. If so just link td->td_proc here. 1866 */ 1867 proc_linkup0(&proc0, &thread0); 1868 1869 kmdp = init_ops.parse_preload_data(modulep); 1870 1871 /* Init basic tunables, hz etc */ 1872 init_param1(); 1873 1874 /* 1875 * make gdt memory segments 1876 */ 1877 for (x = 0; x < NGDT; x++) { 1878 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) && 1879 x != GUSERLDT_SEL && x != (GUSERLDT_SEL) + 1) 1880 ssdtosd(&gdt_segs[x], &gdt[x]); 1881 } 1882 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&common_tss[0]; 1883 ssdtosyssd(&gdt_segs[GPROC0_SEL], 1884 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1885 1886 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 1887 r_gdt.rd_base = (long) gdt; 1888 lgdt(&r_gdt); 1889 pc = &__pcpu[0]; 1890 1891 wrmsr(MSR_FSBASE, 0); /* User value */ 1892 wrmsr(MSR_GSBASE, (u_int64_t)pc); 1893 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ 1894 1895 pcpu_init(pc, 0, sizeof(struct pcpu)); 1896 dpcpu_init((void *)(physfree + KERNBASE), 0); 1897 physfree += DPCPU_SIZE; 1898 PCPU_SET(prvspace, pc); 1899 PCPU_SET(curthread, &thread0); 1900 PCPU_SET(tssp, &common_tss[0]); 1901 PCPU_SET(commontssp, &common_tss[0]); 1902 PCPU_SET(tss, (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1903 PCPU_SET(ldt, (struct system_segment_descriptor *)&gdt[GUSERLDT_SEL]); 1904 PCPU_SET(fs32p, &gdt[GUFS32_SEL]); 1905 PCPU_SET(gs32p, &gdt[GUGS32_SEL]); 1906 1907 /* 1908 * Initialize mutexes. 1909 * 1910 * icu_lock: in order to allow an interrupt to occur in a critical 1911 * section, to set pcpu->ipending (etc...) properly, we 1912 * must be able to get the icu lock, so it can't be 1913 * under witness. 1914 */ 1915 mutex_init(); 1916 mtx_init(&icu_lock, "icu", NULL, MTX_SPIN | MTX_NOWITNESS); 1917 mtx_init(&dt_lock, "descriptor tables", NULL, MTX_DEF); 1918 1919 /* exceptions */ 1920 for (x = 0; x < NIDT; x++) 1921 setidt(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 1922 setidt(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0); 1923 setidt(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0); 1924 setidt(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 2); 1925 setidt(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0); 1926 setidt(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0); 1927 setidt(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0); 1928 setidt(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0); 1929 setidt(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0); 1930 setidt(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1); 1931 setidt(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0); 1932 setidt(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0); 1933 setidt(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0); 1934 setidt(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0); 1935 setidt(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0); 1936 setidt(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0); 1937 setidt(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0); 1938 setidt(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0); 1939 setidt(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0); 1940 setidt(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0); 1941#ifdef KDTRACE_HOOKS 1942 setidt(IDT_DTRACE_RET, &IDTVEC(dtrace_ret), SDT_SYSIGT, SEL_UPL, 0); 1943#endif 1944#ifdef XENHVM 1945 setidt(IDT_EVTCHN, &IDTVEC(xen_intr_upcall), SDT_SYSIGT, SEL_UPL, 0); 1946#endif 1947 1948 r_idt.rd_limit = sizeof(idt0) - 1; 1949 r_idt.rd_base = (long) idt; 1950 lidt(&r_idt); 1951 1952 /* 1953 * Initialize the clock before the console so that console 1954 * initialization can use DELAY(). 1955 */ 1956 clock_init(); 1957 1958 /* 1959 * Initialize the console before we print anything out. 1960 */ 1961 cninit(); 1962 1963#ifdef DEV_ISA 1964#ifdef DEV_ATPIC 1965 elcr_probe(); 1966 atpic_startup(); 1967#else 1968 /* Reset and mask the atpics and leave them shut down. */ 1969 atpic_reset(); 1970 1971 /* 1972 * Point the ICU spurious interrupt vectors at the APIC spurious 1973 * interrupt handler. 1974 */ 1975 setidt(IDT_IO_INTS + 7, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1976 setidt(IDT_IO_INTS + 15, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1977#endif 1978#else 1979#error "have you forgotten the isa device?"; 1980#endif 1981 1982 kdb_init(); 1983 1984#ifdef KDB 1985 if (boothowto & RB_KDB) 1986 kdb_enter(KDB_WHY_BOOTFLAGS, 1987 "Boot flags requested debugger"); 1988#endif 1989 1990 identify_cpu(); /* Final stage of CPU initialization */ 1991 initializecpu(); /* Initialize CPU registers */ 1992 initializecpucache(); 1993 1994 /* doublefault stack space, runs on ist1 */ 1995 common_tss[0].tss_ist1 = (long)&dblfault_stack[sizeof(dblfault_stack)]; 1996 1997 /* 1998 * NMI stack, runs on ist2. The pcpu pointer is stored just 1999 * above the start of the ist2 stack. 2000 */ 2001 np = ((struct nmi_pcpu *) &nmi0_stack[sizeof(nmi0_stack)]) - 1; 2002 np->np_pcpu = (register_t) pc; 2003 common_tss[0].tss_ist2 = (long) np; 2004 2005 /* Set the IO permission bitmap (empty due to tss seg limit) */ 2006 common_tss[0].tss_iobase = sizeof(struct amd64tss) + IOPERM_BITMAP_SIZE; 2007 2008 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 2009 ltr(gsel_tss); 2010 2011 /* Set up the fast syscall stuff */ 2012 msr = rdmsr(MSR_EFER) | EFER_SCE; 2013 wrmsr(MSR_EFER, msr); 2014 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 2015 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 2016 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 2017 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 2018 wrmsr(MSR_STAR, msr); 2019 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D); 2020 2021 getmemsize(kmdp, physfree); 2022 init_param2(physmem); 2023 2024 /* now running on new page tables, configured,and u/iom is accessible */ 2025 2026 msgbufinit(msgbufp, msgbufsize); 2027 fpuinit(); 2028 2029 /* 2030 * Set up thread0 pcb after fpuinit calculated pcb + fpu save 2031 * area size. Zero out the extended state header in fpu save 2032 * area. 2033 */ 2034 thread0.td_pcb = get_pcb_td(&thread0); 2035 bzero(get_pcb_user_save_td(&thread0), cpu_max_ext_state_size); 2036 if (use_xsave) { 2037 xhdr = (struct xstate_hdr *)(get_pcb_user_save_td(&thread0) + 2038 1); 2039 xhdr->xstate_bv = xsave_mask; 2040 } 2041 /* make an initial tss so cpu can get interrupt stack on syscall! */ 2042 common_tss[0].tss_rsp0 = (vm_offset_t)thread0.td_pcb; 2043 /* Ensure the stack is aligned to 16 bytes */ 2044 common_tss[0].tss_rsp0 &= ~0xFul; 2045 PCPU_SET(rsp0, common_tss[0].tss_rsp0); 2046 PCPU_SET(curpcb, thread0.td_pcb); 2047 2048 /* transfer to user mode */ 2049 2050 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 2051 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 2052 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL); 2053 _ufssel = GSEL(GUFS32_SEL, SEL_UPL); 2054 _ugssel = GSEL(GUGS32_SEL, SEL_UPL); 2055 2056 load_ds(_udatasel); 2057 load_es(_udatasel); 2058 load_fs(_ufssel); 2059 2060 /* setup proc 0's pcb */ 2061 thread0.td_pcb->pcb_flags = 0; 2062 thread0.td_pcb->pcb_cr3 = KPML4phys; /* PCID 0 is reserved for kernel */ 2063 thread0.td_frame = &proc0_tf; 2064 2065 env = getenv("kernelname"); 2066 if (env != NULL) 2067 strlcpy(kernelname, env, sizeof(kernelname)); 2068 2069 cpu_probe_amdc1e(); 2070 2071#ifdef FDT 2072 x86_init_fdt(); 2073#endif 2074 2075 /* Location of kernel stack for locore */ 2076 return ((u_int64_t)thread0.td_pcb); 2077} 2078 2079void 2080cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size) 2081{ 2082 2083 pcpu->pc_acpi_id = 0xffffffff; 2084} 2085 2086void 2087spinlock_enter(void) 2088{ 2089 struct thread *td; 2090 register_t flags; 2091 2092 td = curthread; 2093 if (td->td_md.md_spinlock_count == 0) { 2094 flags = intr_disable(); 2095 td->td_md.md_spinlock_count = 1; 2096 td->td_md.md_saved_flags = flags; 2097 } else 2098 td->td_md.md_spinlock_count++; 2099 critical_enter(); 2100} 2101 2102void 2103spinlock_exit(void) 2104{ 2105 struct thread *td; 2106 register_t flags; 2107 2108 td = curthread; 2109 critical_exit(); 2110 flags = td->td_md.md_saved_flags; 2111 td->td_md.md_spinlock_count--; 2112 if (td->td_md.md_spinlock_count == 0) 2113 intr_restore(flags); 2114} 2115 2116/* 2117 * Construct a PCB from a trapframe. This is called from kdb_trap() where 2118 * we want to start a backtrace from the function that caused us to enter 2119 * the debugger. We have the context in the trapframe, but base the trace 2120 * on the PCB. The PCB doesn't have to be perfect, as long as it contains 2121 * enough for a backtrace. 2122 */ 2123void 2124makectx(struct trapframe *tf, struct pcb *pcb) 2125{ 2126 2127 pcb->pcb_r12 = tf->tf_r12; 2128 pcb->pcb_r13 = tf->tf_r13; 2129 pcb->pcb_r14 = tf->tf_r14; 2130 pcb->pcb_r15 = tf->tf_r15; 2131 pcb->pcb_rbp = tf->tf_rbp; 2132 pcb->pcb_rbx = tf->tf_rbx; 2133 pcb->pcb_rip = tf->tf_rip; 2134 pcb->pcb_rsp = tf->tf_rsp; 2135} 2136 2137int 2138ptrace_set_pc(struct thread *td, unsigned long addr) 2139{ 2140 td->td_frame->tf_rip = addr; 2141 return (0); 2142} 2143 2144int 2145ptrace_single_step(struct thread *td) 2146{ 2147 td->td_frame->tf_rflags |= PSL_T; 2148 return (0); 2149} 2150 2151int 2152ptrace_clear_single_step(struct thread *td) 2153{ 2154 td->td_frame->tf_rflags &= ~PSL_T; 2155 return (0); 2156} 2157 2158int 2159fill_regs(struct thread *td, struct reg *regs) 2160{ 2161 struct trapframe *tp; 2162 2163 tp = td->td_frame; 2164 return (fill_frame_regs(tp, regs)); 2165} 2166 2167int 2168fill_frame_regs(struct trapframe *tp, struct reg *regs) 2169{ 2170 regs->r_r15 = tp->tf_r15; 2171 regs->r_r14 = tp->tf_r14; 2172 regs->r_r13 = tp->tf_r13; 2173 regs->r_r12 = tp->tf_r12; 2174 regs->r_r11 = tp->tf_r11; 2175 regs->r_r10 = tp->tf_r10; 2176 regs->r_r9 = tp->tf_r9; 2177 regs->r_r8 = tp->tf_r8; 2178 regs->r_rdi = tp->tf_rdi; 2179 regs->r_rsi = tp->tf_rsi; 2180 regs->r_rbp = tp->tf_rbp; 2181 regs->r_rbx = tp->tf_rbx; 2182 regs->r_rdx = tp->tf_rdx; 2183 regs->r_rcx = tp->tf_rcx; 2184 regs->r_rax = tp->tf_rax; 2185 regs->r_rip = tp->tf_rip; 2186 regs->r_cs = tp->tf_cs; 2187 regs->r_rflags = tp->tf_rflags; 2188 regs->r_rsp = tp->tf_rsp; 2189 regs->r_ss = tp->tf_ss; 2190 if (tp->tf_flags & TF_HASSEGS) { 2191 regs->r_ds = tp->tf_ds; 2192 regs->r_es = tp->tf_es; 2193 regs->r_fs = tp->tf_fs; 2194 regs->r_gs = tp->tf_gs; 2195 } else { 2196 regs->r_ds = 0; 2197 regs->r_es = 0; 2198 regs->r_fs = 0; 2199 regs->r_gs = 0; 2200 } 2201 return (0); 2202} 2203 2204int 2205set_regs(struct thread *td, struct reg *regs) 2206{ 2207 struct trapframe *tp; 2208 register_t rflags; 2209 2210 tp = td->td_frame; 2211 rflags = regs->r_rflags & 0xffffffff; 2212 if (!EFL_SECURE(rflags, tp->tf_rflags) || !CS_SECURE(regs->r_cs)) 2213 return (EINVAL); 2214 tp->tf_r15 = regs->r_r15; 2215 tp->tf_r14 = regs->r_r14; 2216 tp->tf_r13 = regs->r_r13; 2217 tp->tf_r12 = regs->r_r12; 2218 tp->tf_r11 = regs->r_r11; 2219 tp->tf_r10 = regs->r_r10; 2220 tp->tf_r9 = regs->r_r9; 2221 tp->tf_r8 = regs->r_r8; 2222 tp->tf_rdi = regs->r_rdi; 2223 tp->tf_rsi = regs->r_rsi; 2224 tp->tf_rbp = regs->r_rbp; 2225 tp->tf_rbx = regs->r_rbx; 2226 tp->tf_rdx = regs->r_rdx; 2227 tp->tf_rcx = regs->r_rcx; 2228 tp->tf_rax = regs->r_rax; 2229 tp->tf_rip = regs->r_rip; 2230 tp->tf_cs = regs->r_cs; 2231 tp->tf_rflags = rflags; 2232 tp->tf_rsp = regs->r_rsp; 2233 tp->tf_ss = regs->r_ss; 2234 if (0) { /* XXXKIB */ 2235 tp->tf_ds = regs->r_ds; 2236 tp->tf_es = regs->r_es; 2237 tp->tf_fs = regs->r_fs; 2238 tp->tf_gs = regs->r_gs; 2239 tp->tf_flags = TF_HASSEGS; 2240 set_pcb_flags(td->td_pcb, PCB_FULL_IRET); 2241 } 2242 return (0); 2243} 2244 2245/* XXX check all this stuff! */ 2246/* externalize from sv_xmm */ 2247static void 2248fill_fpregs_xmm(struct savefpu *sv_xmm, struct fpreg *fpregs) 2249{ 2250 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 2251 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2252 int i; 2253 2254 /* pcb -> fpregs */ 2255 bzero(fpregs, sizeof(*fpregs)); 2256 2257 /* FPU control/status */ 2258 penv_fpreg->en_cw = penv_xmm->en_cw; 2259 penv_fpreg->en_sw = penv_xmm->en_sw; 2260 penv_fpreg->en_tw = penv_xmm->en_tw; 2261 penv_fpreg->en_opcode = penv_xmm->en_opcode; 2262 penv_fpreg->en_rip = penv_xmm->en_rip; 2263 penv_fpreg->en_rdp = penv_xmm->en_rdp; 2264 penv_fpreg->en_mxcsr = penv_xmm->en_mxcsr; 2265 penv_fpreg->en_mxcsr_mask = penv_xmm->en_mxcsr_mask; 2266 2267 /* FPU registers */ 2268 for (i = 0; i < 8; ++i) 2269 bcopy(sv_xmm->sv_fp[i].fp_acc.fp_bytes, fpregs->fpr_acc[i], 10); 2270 2271 /* SSE registers */ 2272 for (i = 0; i < 16; ++i) 2273 bcopy(sv_xmm->sv_xmm[i].xmm_bytes, fpregs->fpr_xacc[i], 16); 2274} 2275 2276/* internalize from fpregs into sv_xmm */ 2277static void 2278set_fpregs_xmm(struct fpreg *fpregs, struct savefpu *sv_xmm) 2279{ 2280 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2281 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 2282 int i; 2283 2284 /* fpregs -> pcb */ 2285 /* FPU control/status */ 2286 penv_xmm->en_cw = penv_fpreg->en_cw; 2287 penv_xmm->en_sw = penv_fpreg->en_sw; 2288 penv_xmm->en_tw = penv_fpreg->en_tw; 2289 penv_xmm->en_opcode = penv_fpreg->en_opcode; 2290 penv_xmm->en_rip = penv_fpreg->en_rip; 2291 penv_xmm->en_rdp = penv_fpreg->en_rdp; 2292 penv_xmm->en_mxcsr = penv_fpreg->en_mxcsr; 2293 penv_xmm->en_mxcsr_mask = penv_fpreg->en_mxcsr_mask & cpu_mxcsr_mask; 2294 2295 /* FPU registers */ 2296 for (i = 0; i < 8; ++i) 2297 bcopy(fpregs->fpr_acc[i], sv_xmm->sv_fp[i].fp_acc.fp_bytes, 10); 2298 2299 /* SSE registers */ 2300 for (i = 0; i < 16; ++i) 2301 bcopy(fpregs->fpr_xacc[i], sv_xmm->sv_xmm[i].xmm_bytes, 16); 2302} 2303 2304/* externalize from td->pcb */ 2305int 2306fill_fpregs(struct thread *td, struct fpreg *fpregs) 2307{ 2308 2309 KASSERT(td == curthread || TD_IS_SUSPENDED(td) || 2310 P_SHOULDSTOP(td->td_proc), 2311 ("not suspended thread %p", td)); 2312 fpugetregs(td); 2313 fill_fpregs_xmm(get_pcb_user_save_td(td), fpregs); 2314 return (0); 2315} 2316 2317/* internalize to td->pcb */ 2318int 2319set_fpregs(struct thread *td, struct fpreg *fpregs) 2320{ 2321 2322 set_fpregs_xmm(fpregs, get_pcb_user_save_td(td)); 2323 fpuuserinited(td); 2324 return (0); 2325} 2326 2327/* 2328 * Get machine context. 2329 */ 2330int 2331get_mcontext(struct thread *td, mcontext_t *mcp, int flags) 2332{ 2333 struct pcb *pcb; 2334 struct trapframe *tp; 2335 2336 pcb = td->td_pcb; 2337 tp = td->td_frame; 2338 PROC_LOCK(curthread->td_proc); 2339 mcp->mc_onstack = sigonstack(tp->tf_rsp); 2340 PROC_UNLOCK(curthread->td_proc); 2341 mcp->mc_r15 = tp->tf_r15; 2342 mcp->mc_r14 = tp->tf_r14; 2343 mcp->mc_r13 = tp->tf_r13; 2344 mcp->mc_r12 = tp->tf_r12; 2345 mcp->mc_r11 = tp->tf_r11; 2346 mcp->mc_r10 = tp->tf_r10; 2347 mcp->mc_r9 = tp->tf_r9; 2348 mcp->mc_r8 = tp->tf_r8; 2349 mcp->mc_rdi = tp->tf_rdi; 2350 mcp->mc_rsi = tp->tf_rsi; 2351 mcp->mc_rbp = tp->tf_rbp; 2352 mcp->mc_rbx = tp->tf_rbx; 2353 mcp->mc_rcx = tp->tf_rcx; 2354 mcp->mc_rflags = tp->tf_rflags; 2355 if (flags & GET_MC_CLEAR_RET) { 2356 mcp->mc_rax = 0; 2357 mcp->mc_rdx = 0; 2358 mcp->mc_rflags &= ~PSL_C; 2359 } else { 2360 mcp->mc_rax = tp->tf_rax; 2361 mcp->mc_rdx = tp->tf_rdx; 2362 } 2363 mcp->mc_rip = tp->tf_rip; 2364 mcp->mc_cs = tp->tf_cs; 2365 mcp->mc_rsp = tp->tf_rsp; 2366 mcp->mc_ss = tp->tf_ss; 2367 mcp->mc_ds = tp->tf_ds; 2368 mcp->mc_es = tp->tf_es; 2369 mcp->mc_fs = tp->tf_fs; 2370 mcp->mc_gs = tp->tf_gs; 2371 mcp->mc_flags = tp->tf_flags; 2372 mcp->mc_len = sizeof(*mcp); 2373 get_fpcontext(td, mcp, NULL, 0); 2374 mcp->mc_fsbase = pcb->pcb_fsbase; 2375 mcp->mc_gsbase = pcb->pcb_gsbase; 2376 mcp->mc_xfpustate = 0; 2377 mcp->mc_xfpustate_len = 0; 2378 bzero(mcp->mc_spare, sizeof(mcp->mc_spare)); 2379 return (0); 2380} 2381 2382/* 2383 * Set machine context. 2384 * 2385 * However, we don't set any but the user modifiable flags, and we won't 2386 * touch the cs selector. 2387 */ 2388int 2389set_mcontext(struct thread *td, const mcontext_t *mcp) 2390{ 2391 struct pcb *pcb; 2392 struct trapframe *tp; 2393 char *xfpustate; 2394 long rflags; 2395 int ret; 2396 2397 pcb = td->td_pcb; 2398 tp = td->td_frame; 2399 if (mcp->mc_len != sizeof(*mcp) || 2400 (mcp->mc_flags & ~_MC_FLAG_MASK) != 0) 2401 return (EINVAL); 2402 rflags = (mcp->mc_rflags & PSL_USERCHANGE) | 2403 (tp->tf_rflags & ~PSL_USERCHANGE); 2404 if (mcp->mc_flags & _MC_HASFPXSTATE) { 2405 if (mcp->mc_xfpustate_len > cpu_max_ext_state_size - 2406 sizeof(struct savefpu)) 2407 return (EINVAL); 2408 xfpustate = __builtin_alloca(mcp->mc_xfpustate_len); 2409 ret = copyin((void *)mcp->mc_xfpustate, xfpustate, 2410 mcp->mc_xfpustate_len); 2411 if (ret != 0) 2412 return (ret); 2413 } else 2414 xfpustate = NULL; 2415 ret = set_fpcontext(td, mcp, xfpustate, mcp->mc_xfpustate_len); 2416 if (ret != 0) 2417 return (ret); 2418 tp->tf_r15 = mcp->mc_r15; 2419 tp->tf_r14 = mcp->mc_r14; 2420 tp->tf_r13 = mcp->mc_r13; 2421 tp->tf_r12 = mcp->mc_r12; 2422 tp->tf_r11 = mcp->mc_r11; 2423 tp->tf_r10 = mcp->mc_r10; 2424 tp->tf_r9 = mcp->mc_r9; 2425 tp->tf_r8 = mcp->mc_r8; 2426 tp->tf_rdi = mcp->mc_rdi; 2427 tp->tf_rsi = mcp->mc_rsi; 2428 tp->tf_rbp = mcp->mc_rbp; 2429 tp->tf_rbx = mcp->mc_rbx; 2430 tp->tf_rdx = mcp->mc_rdx; 2431 tp->tf_rcx = mcp->mc_rcx; 2432 tp->tf_rax = mcp->mc_rax; 2433 tp->tf_rip = mcp->mc_rip; 2434 tp->tf_rflags = rflags; 2435 tp->tf_rsp = mcp->mc_rsp; 2436 tp->tf_ss = mcp->mc_ss; 2437 tp->tf_flags = mcp->mc_flags; 2438 if (tp->tf_flags & TF_HASSEGS) { 2439 tp->tf_ds = mcp->mc_ds; 2440 tp->tf_es = mcp->mc_es; 2441 tp->tf_fs = mcp->mc_fs; 2442 tp->tf_gs = mcp->mc_gs; 2443 } 2444 if (mcp->mc_flags & _MC_HASBASES) { 2445 pcb->pcb_fsbase = mcp->mc_fsbase; 2446 pcb->pcb_gsbase = mcp->mc_gsbase; 2447 } 2448 set_pcb_flags(pcb, PCB_FULL_IRET); 2449 return (0); 2450} 2451 2452static void 2453get_fpcontext(struct thread *td, mcontext_t *mcp, char *xfpusave, 2454 size_t xfpusave_len) 2455{ 2456 size_t max_len, len; 2457 2458 mcp->mc_ownedfp = fpugetregs(td); 2459 bcopy(get_pcb_user_save_td(td), &mcp->mc_fpstate[0], 2460 sizeof(mcp->mc_fpstate)); 2461 mcp->mc_fpformat = fpuformat(); 2462 if (!use_xsave || xfpusave_len == 0) 2463 return; 2464 max_len = cpu_max_ext_state_size - sizeof(struct savefpu); 2465 len = xfpusave_len; 2466 if (len > max_len) { 2467 len = max_len; 2468 bzero(xfpusave + max_len, len - max_len); 2469 } 2470 mcp->mc_flags |= _MC_HASFPXSTATE; 2471 mcp->mc_xfpustate_len = len; 2472 bcopy(get_pcb_user_save_td(td) + 1, xfpusave, len); 2473} 2474 2475static int 2476set_fpcontext(struct thread *td, const mcontext_t *mcp, char *xfpustate, 2477 size_t xfpustate_len) 2478{ 2479 struct savefpu *fpstate; 2480 int error; 2481 2482 if (mcp->mc_fpformat == _MC_FPFMT_NODEV) 2483 return (0); 2484 else if (mcp->mc_fpformat != _MC_FPFMT_XMM) 2485 return (EINVAL); 2486 else if (mcp->mc_ownedfp == _MC_FPOWNED_NONE) { 2487 /* We don't care what state is left in the FPU or PCB. */ 2488 fpstate_drop(td); 2489 error = 0; 2490 } else if (mcp->mc_ownedfp == _MC_FPOWNED_FPU || 2491 mcp->mc_ownedfp == _MC_FPOWNED_PCB) { 2492 fpstate = (struct savefpu *)&mcp->mc_fpstate; 2493 fpstate->sv_env.en_mxcsr &= cpu_mxcsr_mask; 2494 error = fpusetregs(td, fpstate, xfpustate, xfpustate_len); 2495 } else 2496 return (EINVAL); 2497 return (error); 2498} 2499 2500void 2501fpstate_drop(struct thread *td) 2502{ 2503 2504 KASSERT(PCB_USER_FPU(td->td_pcb), ("fpstate_drop: kernel-owned fpu")); 2505 critical_enter(); 2506 if (PCPU_GET(fpcurthread) == td) 2507 fpudrop(); 2508 /* 2509 * XXX force a full drop of the fpu. The above only drops it if we 2510 * owned it. 2511 * 2512 * XXX I don't much like fpugetuserregs()'s semantics of doing a full 2513 * drop. Dropping only to the pcb matches fnsave's behaviour. 2514 * We only need to drop to !PCB_INITDONE in sendsig(). But 2515 * sendsig() is the only caller of fpugetuserregs()... perhaps we just 2516 * have too many layers. 2517 */ 2518 clear_pcb_flags(curthread->td_pcb, 2519 PCB_FPUINITDONE | PCB_USERFPUINITDONE); 2520 critical_exit(); 2521} 2522 2523int 2524fill_dbregs(struct thread *td, struct dbreg *dbregs) 2525{ 2526 struct pcb *pcb; 2527 2528 if (td == NULL) { 2529 dbregs->dr[0] = rdr0(); 2530 dbregs->dr[1] = rdr1(); 2531 dbregs->dr[2] = rdr2(); 2532 dbregs->dr[3] = rdr3(); 2533 dbregs->dr[6] = rdr6(); 2534 dbregs->dr[7] = rdr7(); 2535 } else { 2536 pcb = td->td_pcb; 2537 dbregs->dr[0] = pcb->pcb_dr0; 2538 dbregs->dr[1] = pcb->pcb_dr1; 2539 dbregs->dr[2] = pcb->pcb_dr2; 2540 dbregs->dr[3] = pcb->pcb_dr3; 2541 dbregs->dr[6] = pcb->pcb_dr6; 2542 dbregs->dr[7] = pcb->pcb_dr7; 2543 } 2544 dbregs->dr[4] = 0; 2545 dbregs->dr[5] = 0; 2546 dbregs->dr[8] = 0; 2547 dbregs->dr[9] = 0; 2548 dbregs->dr[10] = 0; 2549 dbregs->dr[11] = 0; 2550 dbregs->dr[12] = 0; 2551 dbregs->dr[13] = 0; 2552 dbregs->dr[14] = 0; 2553 dbregs->dr[15] = 0; 2554 return (0); 2555} 2556 2557int 2558set_dbregs(struct thread *td, struct dbreg *dbregs) 2559{ 2560 struct pcb *pcb; 2561 int i; 2562 2563 if (td == NULL) { 2564 load_dr0(dbregs->dr[0]); 2565 load_dr1(dbregs->dr[1]); 2566 load_dr2(dbregs->dr[2]); 2567 load_dr3(dbregs->dr[3]); 2568 load_dr6(dbregs->dr[6]); 2569 load_dr7(dbregs->dr[7]); 2570 } else { 2571 /* 2572 * Don't let an illegal value for dr7 get set. Specifically, 2573 * check for undefined settings. Setting these bit patterns 2574 * result in undefined behaviour and can lead to an unexpected 2575 * TRCTRAP or a general protection fault right here. 2576 * Upper bits of dr6 and dr7 must not be set 2577 */ 2578 for (i = 0; i < 4; i++) { 2579 if (DBREG_DR7_ACCESS(dbregs->dr[7], i) == 0x02) 2580 return (EINVAL); 2581 if (td->td_frame->tf_cs == _ucode32sel && 2582 DBREG_DR7_LEN(dbregs->dr[7], i) == DBREG_DR7_LEN_8) 2583 return (EINVAL); 2584 } 2585 if ((dbregs->dr[6] & 0xffffffff00000000ul) != 0 || 2586 (dbregs->dr[7] & 0xffffffff00000000ul) != 0) 2587 return (EINVAL); 2588 2589 pcb = td->td_pcb; 2590 2591 /* 2592 * Don't let a process set a breakpoint that is not within the 2593 * process's address space. If a process could do this, it 2594 * could halt the system by setting a breakpoint in the kernel 2595 * (if ddb was enabled). Thus, we need to check to make sure 2596 * that no breakpoints are being enabled for addresses outside 2597 * process's address space. 2598 * 2599 * XXX - what about when the watched area of the user's 2600 * address space is written into from within the kernel 2601 * ... wouldn't that still cause a breakpoint to be generated 2602 * from within kernel mode? 2603 */ 2604 2605 if (DBREG_DR7_ENABLED(dbregs->dr[7], 0)) { 2606 /* dr0 is enabled */ 2607 if (dbregs->dr[0] >= VM_MAXUSER_ADDRESS) 2608 return (EINVAL); 2609 } 2610 if (DBREG_DR7_ENABLED(dbregs->dr[7], 1)) { 2611 /* dr1 is enabled */ 2612 if (dbregs->dr[1] >= VM_MAXUSER_ADDRESS) 2613 return (EINVAL); 2614 } 2615 if (DBREG_DR7_ENABLED(dbregs->dr[7], 2)) { 2616 /* dr2 is enabled */ 2617 if (dbregs->dr[2] >= VM_MAXUSER_ADDRESS) 2618 return (EINVAL); 2619 } 2620 if (DBREG_DR7_ENABLED(dbregs->dr[7], 3)) { 2621 /* dr3 is enabled */ 2622 if (dbregs->dr[3] >= VM_MAXUSER_ADDRESS) 2623 return (EINVAL); 2624 } 2625 2626 pcb->pcb_dr0 = dbregs->dr[0]; 2627 pcb->pcb_dr1 = dbregs->dr[1]; 2628 pcb->pcb_dr2 = dbregs->dr[2]; 2629 pcb->pcb_dr3 = dbregs->dr[3]; 2630 pcb->pcb_dr6 = dbregs->dr[6]; 2631 pcb->pcb_dr7 = dbregs->dr[7]; 2632 2633 set_pcb_flags(pcb, PCB_DBREGS); 2634 } 2635 2636 return (0); 2637} 2638 2639void 2640reset_dbregs(void) 2641{ 2642 2643 load_dr7(0); /* Turn off the control bits first */ 2644 load_dr0(0); 2645 load_dr1(0); 2646 load_dr2(0); 2647 load_dr3(0); 2648 load_dr6(0); 2649} 2650 2651/* 2652 * Return > 0 if a hardware breakpoint has been hit, and the 2653 * breakpoint was in user space. Return 0, otherwise. 2654 */ 2655int 2656user_dbreg_trap(void) 2657{ 2658 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */ 2659 u_int64_t bp; /* breakpoint bits extracted from dr6 */ 2660 int nbp; /* number of breakpoints that triggered */ 2661 caddr_t addr[4]; /* breakpoint addresses */ 2662 int i; 2663 2664 dr7 = rdr7(); 2665 if ((dr7 & 0x000000ff) == 0) { 2666 /* 2667 * all GE and LE bits in the dr7 register are zero, 2668 * thus the trap couldn't have been caused by the 2669 * hardware debug registers 2670 */ 2671 return 0; 2672 } 2673 2674 nbp = 0; 2675 dr6 = rdr6(); 2676 bp = dr6 & 0x0000000f; 2677 2678 if (!bp) { 2679 /* 2680 * None of the breakpoint bits are set meaning this 2681 * trap was not caused by any of the debug registers 2682 */ 2683 return 0; 2684 } 2685 2686 /* 2687 * at least one of the breakpoints were hit, check to see 2688 * which ones and if any of them are user space addresses 2689 */ 2690 2691 if (bp & 0x01) { 2692 addr[nbp++] = (caddr_t)rdr0(); 2693 } 2694 if (bp & 0x02) { 2695 addr[nbp++] = (caddr_t)rdr1(); 2696 } 2697 if (bp & 0x04) { 2698 addr[nbp++] = (caddr_t)rdr2(); 2699 } 2700 if (bp & 0x08) { 2701 addr[nbp++] = (caddr_t)rdr3(); 2702 } 2703 2704 for (i = 0; i < nbp; i++) { 2705 if (addr[i] < (caddr_t)VM_MAXUSER_ADDRESS) { 2706 /* 2707 * addr[i] is in user space 2708 */ 2709 return nbp; 2710 } 2711 } 2712 2713 /* 2714 * None of the breakpoints are in user space. 2715 */ 2716 return 0; 2717} 2718 2719#ifdef KDB 2720 2721/* 2722 * Provide inb() and outb() as functions. They are normally only available as 2723 * inline functions, thus cannot be called from the debugger. 2724 */ 2725 2726/* silence compiler warnings */ 2727u_char inb_(u_short); 2728void outb_(u_short, u_char); 2729 2730u_char 2731inb_(u_short port) 2732{ 2733 return inb(port); 2734} 2735 2736void 2737outb_(u_short port, u_char data) 2738{ 2739 outb(port, data); 2740} 2741 2742#endif /* KDB */ 2743