machdep.c revision 206553
1/*- 2 * Copyright (c) 2003 Peter Wemm. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 39 */ 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: head/sys/amd64/amd64/machdep.c 206553 2010-04-13 10:12:58Z kib $"); 43 44#include "opt_atalk.h" 45#include "opt_atpic.h" 46#include "opt_compat.h" 47#include "opt_cpu.h" 48#include "opt_ddb.h" 49#include "opt_inet.h" 50#include "opt_ipx.h" 51#include "opt_isa.h" 52#include "opt_kstack_pages.h" 53#include "opt_maxmem.h" 54#include "opt_msgbuf.h" 55#include "opt_perfmon.h" 56#include "opt_sched.h" 57 58#include <sys/param.h> 59#include <sys/proc.h> 60#include <sys/systm.h> 61#include <sys/bio.h> 62#include <sys/buf.h> 63#include <sys/bus.h> 64#include <sys/callout.h> 65#include <sys/cons.h> 66#include <sys/cpu.h> 67#include <sys/eventhandler.h> 68#include <sys/exec.h> 69#include <sys/imgact.h> 70#include <sys/kdb.h> 71#include <sys/kernel.h> 72#include <sys/ktr.h> 73#include <sys/linker.h> 74#include <sys/lock.h> 75#include <sys/malloc.h> 76#include <sys/memrange.h> 77#include <sys/msgbuf.h> 78#include <sys/mutex.h> 79#include <sys/pcpu.h> 80#include <sys/ptrace.h> 81#include <sys/reboot.h> 82#include <sys/sched.h> 83#include <sys/signalvar.h> 84#include <sys/sysctl.h> 85#include <sys/sysent.h> 86#include <sys/sysproto.h> 87#include <sys/ucontext.h> 88#include <sys/vmmeter.h> 89 90#include <vm/vm.h> 91#include <vm/vm_extern.h> 92#include <vm/vm_kern.h> 93#include <vm/vm_page.h> 94#include <vm/vm_map.h> 95#include <vm/vm_object.h> 96#include <vm/vm_pager.h> 97#include <vm/vm_param.h> 98 99#ifdef DDB 100#ifndef KDB 101#error KDB must be enabled in order for DDB to work! 102#endif 103#include <ddb/ddb.h> 104#include <ddb/db_sym.h> 105#endif 106 107#include <net/netisr.h> 108 109#include <machine/clock.h> 110#include <machine/cpu.h> 111#include <machine/cputypes.h> 112#include <machine/intr_machdep.h> 113#include <machine/mca.h> 114#include <machine/md_var.h> 115#include <machine/metadata.h> 116#include <machine/pc/bios.h> 117#include <machine/pcb.h> 118#include <machine/proc.h> 119#include <machine/reg.h> 120#include <machine/sigframe.h> 121#include <machine/specialreg.h> 122#ifdef PERFMON 123#include <machine/perfmon.h> 124#endif 125#include <machine/tss.h> 126#ifdef SMP 127#include <machine/smp.h> 128#endif 129 130#ifdef DEV_ATPIC 131#include <x86/isa/icu.h> 132#else 133#include <machine/apicvar.h> 134#endif 135 136#include <isa/isareg.h> 137#include <isa/rtc.h> 138 139/* Sanity check for __curthread() */ 140CTASSERT(offsetof(struct pcpu, pc_curthread) == 0); 141 142extern u_int64_t hammer_time(u_int64_t, u_int64_t); 143 144extern void printcpuinfo(void); /* XXX header file */ 145extern void identify_cpu(void); 146extern void panicifcpuunsupported(void); 147 148#define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) 149#define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) 150 151static void cpu_startup(void *); 152static void get_fpcontext(struct thread *td, mcontext_t *mcp); 153static int set_fpcontext(struct thread *td, const mcontext_t *mcp); 154SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 155 156#ifdef DDB 157extern vm_offset_t ksym_start, ksym_end; 158#endif 159 160struct msgbuf *msgbufp; 161 162/* Intel ICH registers */ 163#define ICH_PMBASE 0x400 164#define ICH_SMI_EN ICH_PMBASE + 0x30 165 166int _udatasel, _ucodesel, _ucode32sel, _ufssel, _ugssel; 167 168int cold = 1; 169 170long Maxmem = 0; 171long realmem = 0; 172 173/* 174 * The number of PHYSMAP entries must be one less than the number of 175 * PHYSSEG entries because the PHYSMAP entry that spans the largest 176 * physical address that is accessible by ISA DMA is split into two 177 * PHYSSEG entries. 178 */ 179#define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1)) 180 181vm_paddr_t phys_avail[PHYSMAP_SIZE + 2]; 182vm_paddr_t dump_avail[PHYSMAP_SIZE + 2]; 183 184/* must be 2 less so 0 0 can signal end of chunks */ 185#define PHYS_AVAIL_ARRAY_END ((sizeof(phys_avail) / sizeof(phys_avail[0])) - 2) 186#define DUMP_AVAIL_ARRAY_END ((sizeof(dump_avail) / sizeof(dump_avail[0])) - 2) 187 188struct kva_md_info kmi; 189 190static struct trapframe proc0_tf; 191struct region_descriptor r_gdt, r_idt; 192 193struct pcpu __pcpu[MAXCPU]; 194 195struct mtx icu_lock; 196 197struct mem_range_softc mem_range_softc; 198 199struct mtx dt_lock; /* lock for GDT and LDT */ 200 201static void 202cpu_startup(dummy) 203 void *dummy; 204{ 205 uintmax_t memsize; 206 char *sysenv; 207 208 /* 209 * On MacBooks, we need to disallow the legacy USB circuit to 210 * generate an SMI# because this can cause several problems, 211 * namely: incorrect CPU frequency detection and failure to 212 * start the APs. 213 * We do this by disabling a bit in the SMI_EN (SMI Control and 214 * Enable register) of the Intel ICH LPC Interface Bridge. 215 */ 216 sysenv = getenv("smbios.system.product"); 217 if (sysenv != NULL) { 218 if (strncmp(sysenv, "MacBook1,1", 10) == 0 || 219 strncmp(sysenv, "MacBook3,1", 10) == 0 || 220 strncmp(sysenv, "MacBookPro1,1", 13) == 0 || 221 strncmp(sysenv, "MacBookPro1,2", 13) == 0 || 222 strncmp(sysenv, "MacBookPro3,1", 13) == 0 || 223 strncmp(sysenv, "Macmini1,1", 10) == 0) { 224 if (bootverbose) 225 printf("Disabling LEGACY_USB_EN bit on " 226 "Intel ICH.\n"); 227 outl(ICH_SMI_EN, inl(ICH_SMI_EN) & ~0x8); 228 } 229 freeenv(sysenv); 230 } 231 232 /* 233 * Good {morning,afternoon,evening,night}. 234 */ 235 startrtclock(); 236 printcpuinfo(); 237 panicifcpuunsupported(); 238#ifdef PERFMON 239 perfmon_init(); 240#endif 241 realmem = Maxmem; 242 243 /* 244 * Display physical memory if SMBIOS reports reasonable amount. 245 */ 246 memsize = 0; 247 sysenv = getenv("smbios.memory.enabled"); 248 if (sysenv != NULL) { 249 memsize = (uintmax_t)strtoul(sysenv, (char **)NULL, 10) << 10; 250 freeenv(sysenv); 251 } 252 if (memsize < ptoa((uintmax_t)cnt.v_free_count)) 253 memsize = ptoa((uintmax_t)Maxmem); 254 printf("real memory = %ju (%ju MB)\n", memsize, memsize >> 20); 255 256 /* 257 * Display any holes after the first chunk of extended memory. 258 */ 259 if (bootverbose) { 260 int indx; 261 262 printf("Physical memory chunk(s):\n"); 263 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) { 264 vm_paddr_t size; 265 266 size = phys_avail[indx + 1] - phys_avail[indx]; 267 printf( 268 "0x%016jx - 0x%016jx, %ju bytes (%ju pages)\n", 269 (uintmax_t)phys_avail[indx], 270 (uintmax_t)phys_avail[indx + 1] - 1, 271 (uintmax_t)size, (uintmax_t)size / PAGE_SIZE); 272 } 273 } 274 275 vm_ksubmap_init(&kmi); 276 277 printf("avail memory = %ju (%ju MB)\n", 278 ptoa((uintmax_t)cnt.v_free_count), 279 ptoa((uintmax_t)cnt.v_free_count) / 1048576); 280 281 /* 282 * Set up buffers, so they can be used to read disk labels. 283 */ 284 bufinit(); 285 vm_pager_bufferinit(); 286 287 cpu_setregs(); 288 mca_init(); 289} 290 291/* 292 * Send an interrupt to process. 293 * 294 * Stack is set up to allow sigcode stored 295 * at top to call routine, followed by call 296 * to sigreturn routine below. After sigreturn 297 * resets the signal mask, the stack, and the 298 * frame pointer, it returns to the user 299 * specified pc, psl. 300 */ 301void 302sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask) 303{ 304 struct sigframe sf, *sfp; 305 struct proc *p; 306 struct thread *td; 307 struct sigacts *psp; 308 char *sp; 309 struct trapframe *regs; 310 int sig; 311 int oonstack; 312 313 td = curthread; 314 p = td->td_proc; 315 PROC_LOCK_ASSERT(p, MA_OWNED); 316 sig = ksi->ksi_signo; 317 psp = p->p_sigacts; 318 mtx_assert(&psp->ps_mtx, MA_OWNED); 319 regs = td->td_frame; 320 oonstack = sigonstack(regs->tf_rsp); 321 322 /* Save user context. */ 323 bzero(&sf, sizeof(sf)); 324 sf.sf_uc.uc_sigmask = *mask; 325 sf.sf_uc.uc_stack = td->td_sigstk; 326 sf.sf_uc.uc_stack.ss_flags = (td->td_pflags & TDP_ALTSTACK) 327 ? ((oonstack) ? SS_ONSTACK : 0) : SS_DISABLE; 328 sf.sf_uc.uc_mcontext.mc_onstack = (oonstack) ? 1 : 0; 329 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(*regs)); 330 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); /* magic */ 331 get_fpcontext(td, &sf.sf_uc.uc_mcontext); 332 fpstate_drop(td); 333 sf.sf_uc.uc_mcontext.mc_fsbase = td->td_pcb->pcb_fsbase; 334 sf.sf_uc.uc_mcontext.mc_gsbase = td->td_pcb->pcb_gsbase; 335 336 /* Allocate space for the signal handler context. */ 337 if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack && 338 SIGISMEMBER(psp->ps_sigonstack, sig)) { 339 sp = td->td_sigstk.ss_sp + 340 td->td_sigstk.ss_size - sizeof(struct sigframe); 341#if defined(COMPAT_43) 342 td->td_sigstk.ss_flags |= SS_ONSTACK; 343#endif 344 } else 345 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128; 346 /* Align to 16 bytes. */ 347 sfp = (struct sigframe *)((unsigned long)sp & ~0xFul); 348 349 /* Translate the signal if appropriate. */ 350 if (p->p_sysent->sv_sigtbl && sig <= p->p_sysent->sv_sigsize) 351 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; 352 353 /* Build the argument list for the signal handler. */ 354 regs->tf_rdi = sig; /* arg 1 in %rdi */ 355 regs->tf_rdx = (register_t)&sfp->sf_uc; /* arg 3 in %rdx */ 356 if (SIGISMEMBER(psp->ps_siginfo, sig)) { 357 /* Signal handler installed with SA_SIGINFO. */ 358 regs->tf_rsi = (register_t)&sfp->sf_si; /* arg 2 in %rsi */ 359 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; 360 361 /* Fill in POSIX parts */ 362 sf.sf_si = ksi->ksi_info; 363 sf.sf_si.si_signo = sig; /* maybe a translated signal */ 364 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 365 } else { 366 /* Old FreeBSD-style arguments. */ 367 regs->tf_rsi = ksi->ksi_code; /* arg 2 in %rsi */ 368 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 369 sf.sf_ahu.sf_handler = catcher; 370 } 371 mtx_unlock(&psp->ps_mtx); 372 PROC_UNLOCK(p); 373 374 /* 375 * Copy the sigframe out to the user's stack. 376 */ 377 if (copyout(&sf, sfp, sizeof(*sfp)) != 0) { 378#ifdef DEBUG 379 printf("process %ld has trashed its stack\n", (long)p->p_pid); 380#endif 381 PROC_LOCK(p); 382 sigexit(td, SIGILL); 383 } 384 385 regs->tf_rsp = (long)sfp; 386 regs->tf_rip = PS_STRINGS - *(p->p_sysent->sv_szsigcode); 387 regs->tf_rflags &= ~(PSL_T | PSL_D); 388 regs->tf_cs = _ucodesel; 389 regs->tf_ds = _udatasel; 390 regs->tf_es = _udatasel; 391 regs->tf_fs = _ufssel; 392 regs->tf_gs = _ugssel; 393 regs->tf_flags = TF_HASSEGS; 394 td->td_pcb->pcb_full_iret = 1; 395 PROC_LOCK(p); 396 mtx_lock(&psp->ps_mtx); 397} 398 399/* 400 * System call to cleanup state after a signal 401 * has been taken. Reset signal mask and 402 * stack state from context left by sendsig (above). 403 * Return to previous pc and psl as specified by 404 * context left by sendsig. Check carefully to 405 * make sure that the user has not modified the 406 * state to gain improper privileges. 407 * 408 * MPSAFE 409 */ 410int 411sigreturn(td, uap) 412 struct thread *td; 413 struct sigreturn_args /* { 414 const struct __ucontext *sigcntxp; 415 } */ *uap; 416{ 417 ucontext_t uc; 418 struct proc *p = td->td_proc; 419 struct trapframe *regs; 420 ucontext_t *ucp; 421 long rflags; 422 int cs, error, ret; 423 ksiginfo_t ksi; 424 425 error = copyin(uap->sigcntxp, &uc, sizeof(uc)); 426 if (error != 0) { 427 uprintf("pid %d (%s): sigreturn copyin failed\n", 428 p->p_pid, td->td_name); 429 return (error); 430 } 431 ucp = &uc; 432 if ((ucp->uc_mcontext.mc_flags & ~_MC_FLAG_MASK) != 0) { 433 uprintf("pid %d (%s): sigreturn mc_flags %x\n", p->p_pid, 434 td->td_name, ucp->uc_mcontext.mc_flags); 435 return (EINVAL); 436 } 437 regs = td->td_frame; 438 rflags = ucp->uc_mcontext.mc_rflags; 439 /* 440 * Don't allow users to change privileged or reserved flags. 441 */ 442 /* 443 * XXX do allow users to change the privileged flag PSL_RF. 444 * The cpu sets PSL_RF in tf_rflags for faults. Debuggers 445 * should sometimes set it there too. tf_rflags is kept in 446 * the signal context during signal handling and there is no 447 * other place to remember it, so the PSL_RF bit may be 448 * corrupted by the signal handler without us knowing. 449 * Corruption of the PSL_RF bit at worst causes one more or 450 * one less debugger trap, so allowing it is fairly harmless. 451 */ 452 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) { 453 uprintf("pid %d (%s): sigreturn rflags = 0x%lx\n", p->p_pid, 454 td->td_name, rflags); 455 return (EINVAL); 456 } 457 458 /* 459 * Don't allow users to load a valid privileged %cs. Let the 460 * hardware check for invalid selectors, excess privilege in 461 * other selectors, invalid %eip's and invalid %esp's. 462 */ 463 cs = ucp->uc_mcontext.mc_cs; 464 if (!CS_SECURE(cs)) { 465 uprintf("pid %d (%s): sigreturn cs = 0x%x\n", p->p_pid, 466 td->td_name, cs); 467 ksiginfo_init_trap(&ksi); 468 ksi.ksi_signo = SIGBUS; 469 ksi.ksi_code = BUS_OBJERR; 470 ksi.ksi_trapno = T_PROTFLT; 471 ksi.ksi_addr = (void *)regs->tf_rip; 472 trapsignal(td, &ksi); 473 return (EINVAL); 474 } 475 476 ret = set_fpcontext(td, &ucp->uc_mcontext); 477 if (ret != 0) { 478 uprintf("pid %d (%s): sigreturn set_fpcontext err %d\n", 479 p->p_pid, td->td_name, ret); 480 return (ret); 481 } 482 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(*regs)); 483 td->td_pcb->pcb_fsbase = ucp->uc_mcontext.mc_fsbase; 484 td->td_pcb->pcb_gsbase = ucp->uc_mcontext.mc_gsbase; 485 486#if defined(COMPAT_43) 487 if (ucp->uc_mcontext.mc_onstack & 1) 488 td->td_sigstk.ss_flags |= SS_ONSTACK; 489 else 490 td->td_sigstk.ss_flags &= ~SS_ONSTACK; 491#endif 492 493 kern_sigprocmask(td, SIG_SETMASK, &ucp->uc_sigmask, NULL, 0); 494 td->td_pcb->pcb_flags |= PCB_FULLCTX; 495 td->td_pcb->pcb_full_iret = 1; 496 return (EJUSTRETURN); 497} 498 499#ifdef COMPAT_FREEBSD4 500int 501freebsd4_sigreturn(struct thread *td, struct freebsd4_sigreturn_args *uap) 502{ 503 504 return sigreturn(td, (struct sigreturn_args *)uap); 505} 506#endif 507 508 509/* 510 * Machine dependent boot() routine 511 * 512 * I haven't seen anything to put here yet 513 * Possibly some stuff might be grafted back here from boot() 514 */ 515void 516cpu_boot(int howto) 517{ 518} 519 520/* 521 * Flush the D-cache for non-DMA I/O so that the I-cache can 522 * be made coherent later. 523 */ 524void 525cpu_flush_dcache(void *ptr, size_t len) 526{ 527 /* Not applicable */ 528} 529 530/* Get current clock frequency for the given cpu id. */ 531int 532cpu_est_clockrate(int cpu_id, uint64_t *rate) 533{ 534 register_t reg; 535 uint64_t tsc1, tsc2; 536 537 if (pcpu_find(cpu_id) == NULL || rate == NULL) 538 return (EINVAL); 539 540 /* If we're booting, trust the rate calibrated moments ago. */ 541 if (cold) { 542 *rate = tsc_freq; 543 return (0); 544 } 545 546#ifdef SMP 547 /* Schedule ourselves on the indicated cpu. */ 548 thread_lock(curthread); 549 sched_bind(curthread, cpu_id); 550 thread_unlock(curthread); 551#endif 552 553 /* Calibrate by measuring a short delay. */ 554 reg = intr_disable(); 555 tsc1 = rdtsc(); 556 DELAY(1000); 557 tsc2 = rdtsc(); 558 intr_restore(reg); 559 560#ifdef SMP 561 thread_lock(curthread); 562 sched_unbind(curthread); 563 thread_unlock(curthread); 564#endif 565 566 /* 567 * Calculate the difference in readings, convert to Mhz, and 568 * subtract 0.5% of the total. Empirical testing has shown that 569 * overhead in DELAY() works out to approximately this value. 570 */ 571 tsc2 -= tsc1; 572 *rate = tsc2 * 1000 - tsc2 * 5; 573 return (0); 574} 575 576/* 577 * Shutdown the CPU as much as possible 578 */ 579void 580cpu_halt(void) 581{ 582 for (;;) 583 __asm__ ("hlt"); 584} 585 586void (*cpu_idle_hook)(void) = NULL; /* ACPI idle hook. */ 587 588static void 589cpu_idle_hlt(int busy) 590{ 591 /* 592 * we must absolutely guarentee that hlt is the next instruction 593 * after sti or we introduce a timing window. 594 */ 595 disable_intr(); 596 if (sched_runnable()) 597 enable_intr(); 598 else 599 __asm __volatile("sti; hlt"); 600} 601 602static void 603cpu_idle_acpi(int busy) 604{ 605 disable_intr(); 606 if (sched_runnable()) 607 enable_intr(); 608 else if (cpu_idle_hook) 609 cpu_idle_hook(); 610 else 611 __asm __volatile("sti; hlt"); 612} 613 614static int cpu_ident_amdc1e = 0; 615 616static int 617cpu_probe_amdc1e(void) 618{ 619 int i; 620 621 /* 622 * Forget it, if we're not using local APIC timer. 623 */ 624 if (resource_disabled("apic", 0) || 625 (resource_int_value("apic", 0, "clock", &i) == 0 && i == 0)) 626 return (0); 627 628 /* 629 * Detect the presence of C1E capability mostly on latest 630 * dual-cores (or future) k8 family. 631 */ 632 if (cpu_vendor_id == CPU_VENDOR_AMD && 633 (cpu_id & 0x00000f00) == 0x00000f00 && 634 (cpu_id & 0x0fff0000) >= 0x00040000) { 635 cpu_ident_amdc1e = 1; 636 return (1); 637 } 638 639 return (0); 640} 641 642/* 643 * C1E renders the local APIC timer dead, so we disable it by 644 * reading the Interrupt Pending Message register and clearing 645 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27). 646 * 647 * Reference: 648 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" 649 * #32559 revision 3.00+ 650 */ 651#define MSR_AMDK8_IPM 0xc0010055 652#define AMDK8_SMIONCMPHALT (1ULL << 27) 653#define AMDK8_C1EONCMPHALT (1ULL << 28) 654#define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT) 655 656static void 657cpu_idle_amdc1e(int busy) 658{ 659 660 disable_intr(); 661 if (sched_runnable()) 662 enable_intr(); 663 else { 664 uint64_t msr; 665 666 msr = rdmsr(MSR_AMDK8_IPM); 667 if (msr & AMDK8_CMPHALT) 668 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT); 669 670 if (cpu_idle_hook) 671 cpu_idle_hook(); 672 else 673 __asm __volatile("sti; hlt"); 674 } 675} 676 677static void 678cpu_idle_spin(int busy) 679{ 680 return; 681} 682 683void (*cpu_idle_fn)(int) = cpu_idle_acpi; 684 685void 686cpu_idle(int busy) 687{ 688#ifdef SMP 689 if (mp_grab_cpu_hlt()) 690 return; 691#endif 692 cpu_idle_fn(busy); 693} 694 695/* 696 * mwait cpu power states. Lower 4 bits are sub-states. 697 */ 698#define MWAIT_C0 0xf0 699#define MWAIT_C1 0x00 700#define MWAIT_C2 0x10 701#define MWAIT_C3 0x20 702#define MWAIT_C4 0x30 703 704#define MWAIT_DISABLED 0x0 705#define MWAIT_WOKEN 0x1 706#define MWAIT_WAITING 0x2 707 708static void 709cpu_idle_mwait(int busy) 710{ 711 int *mwait; 712 713 mwait = (int *)PCPU_PTR(monitorbuf); 714 *mwait = MWAIT_WAITING; 715 if (sched_runnable()) 716 return; 717 cpu_monitor(mwait, 0, 0); 718 if (*mwait == MWAIT_WAITING) 719 cpu_mwait(0, MWAIT_C1); 720} 721 722static void 723cpu_idle_mwait_hlt(int busy) 724{ 725 int *mwait; 726 727 mwait = (int *)PCPU_PTR(monitorbuf); 728 if (busy == 0) { 729 *mwait = MWAIT_DISABLED; 730 cpu_idle_hlt(busy); 731 return; 732 } 733 *mwait = MWAIT_WAITING; 734 if (sched_runnable()) 735 return; 736 cpu_monitor(mwait, 0, 0); 737 if (*mwait == MWAIT_WAITING) 738 cpu_mwait(0, MWAIT_C1); 739} 740 741int 742cpu_idle_wakeup(int cpu) 743{ 744 struct pcpu *pcpu; 745 int *mwait; 746 747 if (cpu_idle_fn == cpu_idle_spin) 748 return (1); 749 if (cpu_idle_fn != cpu_idle_mwait && cpu_idle_fn != cpu_idle_mwait_hlt) 750 return (0); 751 pcpu = pcpu_find(cpu); 752 mwait = (int *)pcpu->pc_monitorbuf; 753 /* 754 * This doesn't need to be atomic since missing the race will 755 * simply result in unnecessary IPIs. 756 */ 757 if (cpu_idle_fn == cpu_idle_mwait_hlt && *mwait == MWAIT_DISABLED) 758 return (0); 759 *mwait = MWAIT_WOKEN; 760 761 return (1); 762} 763 764/* 765 * Ordered by speed/power consumption. 766 */ 767struct { 768 void *id_fn; 769 char *id_name; 770} idle_tbl[] = { 771 { cpu_idle_spin, "spin" }, 772 { cpu_idle_mwait, "mwait" }, 773 { cpu_idle_mwait_hlt, "mwait_hlt" }, 774 { cpu_idle_amdc1e, "amdc1e" }, 775 { cpu_idle_hlt, "hlt" }, 776 { cpu_idle_acpi, "acpi" }, 777 { NULL, NULL } 778}; 779 780static int 781idle_sysctl_available(SYSCTL_HANDLER_ARGS) 782{ 783 char *avail, *p; 784 int error; 785 int i; 786 787 avail = malloc(256, M_TEMP, M_WAITOK); 788 p = avail; 789 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 790 if (strstr(idle_tbl[i].id_name, "mwait") && 791 (cpu_feature2 & CPUID2_MON) == 0) 792 continue; 793 if (strcmp(idle_tbl[i].id_name, "amdc1e") == 0 && 794 cpu_ident_amdc1e == 0) 795 continue; 796 p += sprintf(p, "%s, ", idle_tbl[i].id_name); 797 } 798 error = sysctl_handle_string(oidp, avail, 0, req); 799 free(avail, M_TEMP); 800 return (error); 801} 802 803static int 804idle_sysctl(SYSCTL_HANDLER_ARGS) 805{ 806 char buf[16]; 807 int error; 808 char *p; 809 int i; 810 811 p = "unknown"; 812 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 813 if (idle_tbl[i].id_fn == cpu_idle_fn) { 814 p = idle_tbl[i].id_name; 815 break; 816 } 817 } 818 strncpy(buf, p, sizeof(buf)); 819 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 820 if (error != 0 || req->newptr == NULL) 821 return (error); 822 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 823 if (strstr(idle_tbl[i].id_name, "mwait") && 824 (cpu_feature2 & CPUID2_MON) == 0) 825 continue; 826 if (strcmp(idle_tbl[i].id_name, "amdc1e") == 0 && 827 cpu_ident_amdc1e == 0) 828 continue; 829 if (strcmp(idle_tbl[i].id_name, buf)) 830 continue; 831 cpu_idle_fn = idle_tbl[i].id_fn; 832 return (0); 833 } 834 return (EINVAL); 835} 836 837SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD, 838 0, 0, idle_sysctl_available, "A", "list of available idle functions"); 839 840SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0, 841 idle_sysctl, "A", "currently selected idle function"); 842 843/* 844 * Reset registers to default values on exec. 845 */ 846void 847exec_setregs(struct thread *td, struct image_params *imgp, u_long stack) 848{ 849 struct trapframe *regs = td->td_frame; 850 struct pcb *pcb = td->td_pcb; 851 852 mtx_lock(&dt_lock); 853 if (td->td_proc->p_md.md_ldt != NULL) 854 user_ldt_free(td); 855 else 856 mtx_unlock(&dt_lock); 857 858 pcb->pcb_fsbase = 0; 859 pcb->pcb_gsbase = 0; 860 pcb->pcb_flags &= ~(PCB_32BIT | PCB_GS32BIT); 861 pcb->pcb_initial_fpucw = __INITIAL_FPUCW__; 862 pcb->pcb_full_iret = 1; 863 864 bzero((char *)regs, sizeof(struct trapframe)); 865 regs->tf_rip = imgp->entry_addr; 866 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; 867 regs->tf_rdi = stack; /* argv */ 868 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T); 869 regs->tf_ss = _udatasel; 870 regs->tf_cs = _ucodesel; 871 regs->tf_ds = _udatasel; 872 regs->tf_es = _udatasel; 873 regs->tf_fs = _ufssel; 874 regs->tf_gs = _ugssel; 875 regs->tf_flags = TF_HASSEGS; 876 877 /* 878 * Reset the hardware debug registers if they were in use. 879 * They won't have any meaning for the newly exec'd process. 880 */ 881 if (pcb->pcb_flags & PCB_DBREGS) { 882 pcb->pcb_dr0 = 0; 883 pcb->pcb_dr1 = 0; 884 pcb->pcb_dr2 = 0; 885 pcb->pcb_dr3 = 0; 886 pcb->pcb_dr6 = 0; 887 pcb->pcb_dr7 = 0; 888 if (pcb == PCPU_GET(curpcb)) { 889 /* 890 * Clear the debug registers on the running 891 * CPU, otherwise they will end up affecting 892 * the next process we switch to. 893 */ 894 reset_dbregs(); 895 } 896 pcb->pcb_flags &= ~PCB_DBREGS; 897 } 898 899 /* 900 * Drop the FP state if we hold it, so that the process gets a 901 * clean FP state if it uses the FPU again. 902 */ 903 fpstate_drop(td); 904} 905 906void 907cpu_setregs(void) 908{ 909 register_t cr0; 910 911 cr0 = rcr0(); 912 /* 913 * CR0_MP, CR0_NE and CR0_TS are also set by npx_probe() for the 914 * BSP. See the comments there about why we set them. 915 */ 916 cr0 |= CR0_MP | CR0_NE | CR0_TS | CR0_WP | CR0_AM; 917 load_cr0(cr0); 918} 919 920/* 921 * Initialize amd64 and configure to run kernel 922 */ 923 924/* 925 * Initialize segments & interrupt table 926 */ 927 928struct user_segment_descriptor gdt[NGDT * MAXCPU];/* global descriptor tables */ 929static struct gate_descriptor idt0[NIDT]; 930struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */ 931 932static char dblfault_stack[PAGE_SIZE] __aligned(16); 933 934static char nmi0_stack[PAGE_SIZE] __aligned(16); 935CTASSERT(sizeof(struct nmi_pcpu) == 16); 936 937struct amd64tss common_tss[MAXCPU]; 938 939/* 940 * Software prototypes -- in more palatable form. 941 * 942 * Keep GUFS32, GUGS32, GUCODE32 and GUDATA at the same 943 * slots as corresponding segments for i386 kernel. 944 */ 945struct soft_segment_descriptor gdt_segs[] = { 946/* GNULL_SEL 0 Null Descriptor */ 947{ .ssd_base = 0x0, 948 .ssd_limit = 0x0, 949 .ssd_type = 0, 950 .ssd_dpl = 0, 951 .ssd_p = 0, 952 .ssd_long = 0, 953 .ssd_def32 = 0, 954 .ssd_gran = 0 }, 955/* GNULL2_SEL 1 Null Descriptor */ 956{ .ssd_base = 0x0, 957 .ssd_limit = 0x0, 958 .ssd_type = 0, 959 .ssd_dpl = 0, 960 .ssd_p = 0, 961 .ssd_long = 0, 962 .ssd_def32 = 0, 963 .ssd_gran = 0 }, 964/* GUFS32_SEL 2 32 bit %gs Descriptor for user */ 965{ .ssd_base = 0x0, 966 .ssd_limit = 0xfffff, 967 .ssd_type = SDT_MEMRWA, 968 .ssd_dpl = SEL_UPL, 969 .ssd_p = 1, 970 .ssd_long = 0, 971 .ssd_def32 = 1, 972 .ssd_gran = 1 }, 973/* GUGS32_SEL 3 32 bit %fs Descriptor for user */ 974{ .ssd_base = 0x0, 975 .ssd_limit = 0xfffff, 976 .ssd_type = SDT_MEMRWA, 977 .ssd_dpl = SEL_UPL, 978 .ssd_p = 1, 979 .ssd_long = 0, 980 .ssd_def32 = 1, 981 .ssd_gran = 1 }, 982/* GCODE_SEL 4 Code Descriptor for kernel */ 983{ .ssd_base = 0x0, 984 .ssd_limit = 0xfffff, 985 .ssd_type = SDT_MEMERA, 986 .ssd_dpl = SEL_KPL, 987 .ssd_p = 1, 988 .ssd_long = 1, 989 .ssd_def32 = 0, 990 .ssd_gran = 1 }, 991/* GDATA_SEL 5 Data Descriptor for kernel */ 992{ .ssd_base = 0x0, 993 .ssd_limit = 0xfffff, 994 .ssd_type = SDT_MEMRWA, 995 .ssd_dpl = SEL_KPL, 996 .ssd_p = 1, 997 .ssd_long = 1, 998 .ssd_def32 = 0, 999 .ssd_gran = 1 }, 1000/* GUCODE32_SEL 6 32 bit Code Descriptor for user */ 1001{ .ssd_base = 0x0, 1002 .ssd_limit = 0xfffff, 1003 .ssd_type = SDT_MEMERA, 1004 .ssd_dpl = SEL_UPL, 1005 .ssd_p = 1, 1006 .ssd_long = 0, 1007 .ssd_def32 = 1, 1008 .ssd_gran = 1 }, 1009/* GUDATA_SEL 7 32/64 bit Data Descriptor for user */ 1010{ .ssd_base = 0x0, 1011 .ssd_limit = 0xfffff, 1012 .ssd_type = SDT_MEMRWA, 1013 .ssd_dpl = SEL_UPL, 1014 .ssd_p = 1, 1015 .ssd_long = 0, 1016 .ssd_def32 = 1, 1017 .ssd_gran = 1 }, 1018/* GUCODE_SEL 8 64 bit Code Descriptor for user */ 1019{ .ssd_base = 0x0, 1020 .ssd_limit = 0xfffff, 1021 .ssd_type = SDT_MEMERA, 1022 .ssd_dpl = SEL_UPL, 1023 .ssd_p = 1, 1024 .ssd_long = 1, 1025 .ssd_def32 = 0, 1026 .ssd_gran = 1 }, 1027/* GPROC0_SEL 9 Proc 0 Tss Descriptor */ 1028{ .ssd_base = 0x0, 1029 .ssd_limit = sizeof(struct amd64tss) + IOPAGES * PAGE_SIZE - 1, 1030 .ssd_type = SDT_SYSTSS, 1031 .ssd_dpl = SEL_KPL, 1032 .ssd_p = 1, 1033 .ssd_long = 0, 1034 .ssd_def32 = 0, 1035 .ssd_gran = 0 }, 1036/* Actually, the TSS is a system descriptor which is double size */ 1037{ .ssd_base = 0x0, 1038 .ssd_limit = 0x0, 1039 .ssd_type = 0, 1040 .ssd_dpl = 0, 1041 .ssd_p = 0, 1042 .ssd_long = 0, 1043 .ssd_def32 = 0, 1044 .ssd_gran = 0 }, 1045/* GUSERLDT_SEL 11 LDT Descriptor */ 1046{ .ssd_base = 0x0, 1047 .ssd_limit = 0x0, 1048 .ssd_type = 0, 1049 .ssd_dpl = 0, 1050 .ssd_p = 0, 1051 .ssd_long = 0, 1052 .ssd_def32 = 0, 1053 .ssd_gran = 0 }, 1054/* GUSERLDT_SEL 12 LDT Descriptor, double size */ 1055{ .ssd_base = 0x0, 1056 .ssd_limit = 0x0, 1057 .ssd_type = 0, 1058 .ssd_dpl = 0, 1059 .ssd_p = 0, 1060 .ssd_long = 0, 1061 .ssd_def32 = 0, 1062 .ssd_gran = 0 }, 1063}; 1064 1065void 1066setidt(idx, func, typ, dpl, ist) 1067 int idx; 1068 inthand_t *func; 1069 int typ; 1070 int dpl; 1071 int ist; 1072{ 1073 struct gate_descriptor *ip; 1074 1075 ip = idt + idx; 1076 ip->gd_looffset = (uintptr_t)func; 1077 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1078 ip->gd_ist = ist; 1079 ip->gd_xx = 0; 1080 ip->gd_type = typ; 1081 ip->gd_dpl = dpl; 1082 ip->gd_p = 1; 1083 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1084} 1085 1086extern inthand_t 1087 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 1088 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 1089 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 1090 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 1091 IDTVEC(xmm), IDTVEC(dblfault), 1092 IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 1093 1094#ifdef DDB 1095/* 1096 * Display the index and function name of any IDT entries that don't use 1097 * the default 'rsvd' entry point. 1098 */ 1099DB_SHOW_COMMAND(idt, db_show_idt) 1100{ 1101 struct gate_descriptor *ip; 1102 int idx; 1103 uintptr_t func; 1104 1105 ip = idt; 1106 for (idx = 0; idx < NIDT && !db_pager_quit; idx++) { 1107 func = ((long)ip->gd_hioffset << 16 | ip->gd_looffset); 1108 if (func != (uintptr_t)&IDTVEC(rsvd)) { 1109 db_printf("%3d\t", idx); 1110 db_printsym(func, DB_STGY_PROC); 1111 db_printf("\n"); 1112 } 1113 ip++; 1114 } 1115} 1116#endif 1117 1118void 1119sdtossd(sd, ssd) 1120 struct user_segment_descriptor *sd; 1121 struct soft_segment_descriptor *ssd; 1122{ 1123 1124 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 1125 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 1126 ssd->ssd_type = sd->sd_type; 1127 ssd->ssd_dpl = sd->sd_dpl; 1128 ssd->ssd_p = sd->sd_p; 1129 ssd->ssd_long = sd->sd_long; 1130 ssd->ssd_def32 = sd->sd_def32; 1131 ssd->ssd_gran = sd->sd_gran; 1132} 1133 1134void 1135ssdtosd(ssd, sd) 1136 struct soft_segment_descriptor *ssd; 1137 struct user_segment_descriptor *sd; 1138{ 1139 1140 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1141 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff; 1142 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1143 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1144 sd->sd_type = ssd->ssd_type; 1145 sd->sd_dpl = ssd->ssd_dpl; 1146 sd->sd_p = ssd->ssd_p; 1147 sd->sd_long = ssd->ssd_long; 1148 sd->sd_def32 = ssd->ssd_def32; 1149 sd->sd_gran = ssd->ssd_gran; 1150} 1151 1152void 1153ssdtosyssd(ssd, sd) 1154 struct soft_segment_descriptor *ssd; 1155 struct system_segment_descriptor *sd; 1156{ 1157 1158 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1159 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful; 1160 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1161 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1162 sd->sd_type = ssd->ssd_type; 1163 sd->sd_dpl = ssd->ssd_dpl; 1164 sd->sd_p = ssd->ssd_p; 1165 sd->sd_gran = ssd->ssd_gran; 1166} 1167 1168#if !defined(DEV_ATPIC) && defined(DEV_ISA) 1169#include <isa/isavar.h> 1170#include <isa/isareg.h> 1171/* 1172 * Return a bitmap of the current interrupt requests. This is 8259-specific 1173 * and is only suitable for use at probe time. 1174 * This is only here to pacify sio. It is NOT FATAL if this doesn't work. 1175 * It shouldn't be here. There should probably be an APIC centric 1176 * implementation in the apic driver code, if at all. 1177 */ 1178intrmask_t 1179isa_irq_pending(void) 1180{ 1181 u_char irr1; 1182 u_char irr2; 1183 1184 irr1 = inb(IO_ICU1); 1185 irr2 = inb(IO_ICU2); 1186 return ((irr2 << 8) | irr1); 1187} 1188#endif 1189 1190u_int basemem; 1191 1192static int 1193add_smap_entry(struct bios_smap *smap, vm_paddr_t *physmap, int *physmap_idxp) 1194{ 1195 int i, insert_idx, physmap_idx; 1196 1197 physmap_idx = *physmap_idxp; 1198 1199 if (boothowto & RB_VERBOSE) 1200 printf("SMAP type=%02x base=%016lx len=%016lx\n", 1201 smap->type, smap->base, smap->length); 1202 1203 if (smap->type != SMAP_TYPE_MEMORY) 1204 return (1); 1205 1206 if (smap->length == 0) 1207 return (0); 1208 1209 /* 1210 * Find insertion point while checking for overlap. Start off by 1211 * assuming the new entry will be added to the end. 1212 */ 1213 insert_idx = physmap_idx + 2; 1214 for (i = 0; i <= physmap_idx; i += 2) { 1215 if (smap->base < physmap[i + 1]) { 1216 if (smap->base + smap->length <= physmap[i]) { 1217 insert_idx = i; 1218 break; 1219 } 1220 if (boothowto & RB_VERBOSE) 1221 printf( 1222 "Overlapping memory regions, ignoring second region\n"); 1223 return (1); 1224 } 1225 } 1226 1227 /* See if we can prepend to the next entry. */ 1228 if (insert_idx <= physmap_idx && 1229 smap->base + smap->length == physmap[insert_idx]) { 1230 physmap[insert_idx] = smap->base; 1231 return (1); 1232 } 1233 1234 /* See if we can append to the previous entry. */ 1235 if (insert_idx > 0 && smap->base == physmap[insert_idx - 1]) { 1236 physmap[insert_idx - 1] += smap->length; 1237 return (1); 1238 } 1239 1240 physmap_idx += 2; 1241 *physmap_idxp = physmap_idx; 1242 if (physmap_idx == PHYSMAP_SIZE) { 1243 printf( 1244 "Too many segments in the physical address map, giving up\n"); 1245 return (0); 1246 } 1247 1248 /* 1249 * Move the last 'N' entries down to make room for the new 1250 * entry if needed. 1251 */ 1252 for (i = physmap_idx; i > insert_idx; i -= 2) { 1253 physmap[i] = physmap[i - 2]; 1254 physmap[i + 1] = physmap[i - 1]; 1255 } 1256 1257 /* Insert the new entry. */ 1258 physmap[insert_idx] = smap->base; 1259 physmap[insert_idx + 1] = smap->base + smap->length; 1260 return (1); 1261} 1262 1263/* 1264 * Populate the (physmap) array with base/bound pairs describing the 1265 * available physical memory in the system, then test this memory and 1266 * build the phys_avail array describing the actually-available memory. 1267 * 1268 * If we cannot accurately determine the physical memory map, then use 1269 * value from the 0xE801 call, and failing that, the RTC. 1270 * 1271 * Total memory size may be set by the kernel environment variable 1272 * hw.physmem or the compile-time define MAXMEM. 1273 * 1274 * XXX first should be vm_paddr_t. 1275 */ 1276static void 1277getmemsize(caddr_t kmdp, u_int64_t first) 1278{ 1279 int i, physmap_idx, pa_indx, da_indx; 1280 vm_paddr_t pa, physmap[PHYSMAP_SIZE]; 1281 u_long physmem_tunable; 1282 pt_entry_t *pte; 1283 struct bios_smap *smapbase, *smap, *smapend; 1284 u_int32_t smapsize; 1285 quad_t dcons_addr, dcons_size; 1286 1287 bzero(physmap, sizeof(physmap)); 1288 basemem = 0; 1289 physmap_idx = 0; 1290 1291 /* 1292 * get memory map from INT 15:E820, kindly supplied by the loader. 1293 * 1294 * subr_module.c says: 1295 * "Consumer may safely assume that size value precedes data." 1296 * ie: an int32_t immediately precedes smap. 1297 */ 1298 smapbase = (struct bios_smap *)preload_search_info(kmdp, 1299 MODINFO_METADATA | MODINFOMD_SMAP); 1300 if (smapbase == NULL) 1301 panic("No BIOS smap info from loader!"); 1302 1303 smapsize = *((u_int32_t *)smapbase - 1); 1304 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 1305 1306 for (smap = smapbase; smap < smapend; smap++) 1307 if (!add_smap_entry(smap, physmap, &physmap_idx)) 1308 break; 1309 1310 /* 1311 * Find the 'base memory' segment for SMP 1312 */ 1313 basemem = 0; 1314 for (i = 0; i <= physmap_idx; i += 2) { 1315 if (physmap[i] == 0x00000000) { 1316 basemem = physmap[i + 1] / 1024; 1317 break; 1318 } 1319 } 1320 if (basemem == 0) 1321 panic("BIOS smap did not include a basemem segment!"); 1322 1323#ifdef SMP 1324 /* make hole for AP bootstrap code */ 1325 physmap[1] = mp_bootaddress(physmap[1] / 1024); 1326#endif 1327 1328 /* 1329 * Maxmem isn't the "maximum memory", it's one larger than the 1330 * highest page of the physical address space. It should be 1331 * called something like "Maxphyspage". We may adjust this 1332 * based on ``hw.physmem'' and the results of the memory test. 1333 */ 1334 Maxmem = atop(physmap[physmap_idx + 1]); 1335 1336#ifdef MAXMEM 1337 Maxmem = MAXMEM / 4; 1338#endif 1339 1340 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable)) 1341 Maxmem = atop(physmem_tunable); 1342 1343 /* 1344 * Don't allow MAXMEM or hw.physmem to extend the amount of memory 1345 * in the system. 1346 */ 1347 if (Maxmem > atop(physmap[physmap_idx + 1])) 1348 Maxmem = atop(physmap[physmap_idx + 1]); 1349 1350 if (atop(physmap[physmap_idx + 1]) != Maxmem && 1351 (boothowto & RB_VERBOSE)) 1352 printf("Physical memory use set to %ldK\n", Maxmem * 4); 1353 1354 /* call pmap initialization to make new kernel address space */ 1355 pmap_bootstrap(&first); 1356 1357 /* 1358 * Size up each available chunk of physical memory. 1359 */ 1360 physmap[0] = PAGE_SIZE; /* mask off page 0 */ 1361 pa_indx = 0; 1362 da_indx = 1; 1363 phys_avail[pa_indx++] = physmap[0]; 1364 phys_avail[pa_indx] = physmap[0]; 1365 dump_avail[da_indx] = physmap[0]; 1366 pte = CMAP1; 1367 1368 /* 1369 * Get dcons buffer address 1370 */ 1371 if (getenv_quad("dcons.addr", &dcons_addr) == 0 || 1372 getenv_quad("dcons.size", &dcons_size) == 0) 1373 dcons_addr = 0; 1374 1375 /* 1376 * physmap is in bytes, so when converting to page boundaries, 1377 * round up the start address and round down the end address. 1378 */ 1379 for (i = 0; i <= physmap_idx; i += 2) { 1380 vm_paddr_t end; 1381 1382 end = ptoa((vm_paddr_t)Maxmem); 1383 if (physmap[i + 1] < end) 1384 end = trunc_page(physmap[i + 1]); 1385 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) { 1386 int tmp, page_bad, full; 1387 int *ptr = (int *)CADDR1; 1388 1389 full = FALSE; 1390 /* 1391 * block out kernel memory as not available. 1392 */ 1393 if (pa >= 0x100000 && pa < first) 1394 goto do_dump_avail; 1395 1396 /* 1397 * block out dcons buffer 1398 */ 1399 if (dcons_addr > 0 1400 && pa >= trunc_page(dcons_addr) 1401 && pa < dcons_addr + dcons_size) 1402 goto do_dump_avail; 1403 1404 page_bad = FALSE; 1405 1406 /* 1407 * map page into kernel: valid, read/write,non-cacheable 1408 */ 1409 *pte = pa | PG_V | PG_RW | PG_N; 1410 invltlb(); 1411 1412 tmp = *(int *)ptr; 1413 /* 1414 * Test for alternating 1's and 0's 1415 */ 1416 *(volatile int *)ptr = 0xaaaaaaaa; 1417 if (*(volatile int *)ptr != 0xaaaaaaaa) 1418 page_bad = TRUE; 1419 /* 1420 * Test for alternating 0's and 1's 1421 */ 1422 *(volatile int *)ptr = 0x55555555; 1423 if (*(volatile int *)ptr != 0x55555555) 1424 page_bad = TRUE; 1425 /* 1426 * Test for all 1's 1427 */ 1428 *(volatile int *)ptr = 0xffffffff; 1429 if (*(volatile int *)ptr != 0xffffffff) 1430 page_bad = TRUE; 1431 /* 1432 * Test for all 0's 1433 */ 1434 *(volatile int *)ptr = 0x0; 1435 if (*(volatile int *)ptr != 0x0) 1436 page_bad = TRUE; 1437 /* 1438 * Restore original value. 1439 */ 1440 *(int *)ptr = tmp; 1441 1442 /* 1443 * Adjust array of valid/good pages. 1444 */ 1445 if (page_bad == TRUE) 1446 continue; 1447 /* 1448 * If this good page is a continuation of the 1449 * previous set of good pages, then just increase 1450 * the end pointer. Otherwise start a new chunk. 1451 * Note that "end" points one higher than end, 1452 * making the range >= start and < end. 1453 * If we're also doing a speculative memory 1454 * test and we at or past the end, bump up Maxmem 1455 * so that we keep going. The first bad page 1456 * will terminate the loop. 1457 */ 1458 if (phys_avail[pa_indx] == pa) { 1459 phys_avail[pa_indx] += PAGE_SIZE; 1460 } else { 1461 pa_indx++; 1462 if (pa_indx == PHYS_AVAIL_ARRAY_END) { 1463 printf( 1464 "Too many holes in the physical address space, giving up\n"); 1465 pa_indx--; 1466 full = TRUE; 1467 goto do_dump_avail; 1468 } 1469 phys_avail[pa_indx++] = pa; /* start */ 1470 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */ 1471 } 1472 physmem++; 1473do_dump_avail: 1474 if (dump_avail[da_indx] == pa) { 1475 dump_avail[da_indx] += PAGE_SIZE; 1476 } else { 1477 da_indx++; 1478 if (da_indx == DUMP_AVAIL_ARRAY_END) { 1479 da_indx--; 1480 goto do_next; 1481 } 1482 dump_avail[da_indx++] = pa; /* start */ 1483 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */ 1484 } 1485do_next: 1486 if (full) 1487 break; 1488 } 1489 } 1490 *pte = 0; 1491 invltlb(); 1492 1493 /* 1494 * XXX 1495 * The last chunk must contain at least one page plus the message 1496 * buffer to avoid complicating other code (message buffer address 1497 * calculation, etc.). 1498 */ 1499 while (phys_avail[pa_indx - 1] + PAGE_SIZE + 1500 round_page(MSGBUF_SIZE) >= phys_avail[pa_indx]) { 1501 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]); 1502 phys_avail[pa_indx--] = 0; 1503 phys_avail[pa_indx--] = 0; 1504 } 1505 1506 Maxmem = atop(phys_avail[pa_indx]); 1507 1508 /* Trim off space for the message buffer. */ 1509 phys_avail[pa_indx] -= round_page(MSGBUF_SIZE); 1510 1511 /* Map the message buffer. */ 1512 msgbufp = (struct msgbuf *)PHYS_TO_DMAP(phys_avail[pa_indx]); 1513} 1514 1515u_int64_t 1516hammer_time(u_int64_t modulep, u_int64_t physfree) 1517{ 1518 caddr_t kmdp; 1519 int gsel_tss, x; 1520 struct pcpu *pc; 1521 struct nmi_pcpu *np; 1522 u_int64_t msr; 1523 char *env; 1524 1525 thread0.td_kstack = physfree + KERNBASE; 1526 bzero((void *)thread0.td_kstack, KSTACK_PAGES * PAGE_SIZE); 1527 physfree += KSTACK_PAGES * PAGE_SIZE; 1528 thread0.td_pcb = (struct pcb *) 1529 (thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1; 1530 1531 /* 1532 * This may be done better later if it gets more high level 1533 * components in it. If so just link td->td_proc here. 1534 */ 1535 proc_linkup0(&proc0, &thread0); 1536 1537 preload_metadata = (caddr_t)(uintptr_t)(modulep + KERNBASE); 1538 preload_bootstrap_relocate(KERNBASE); 1539 kmdp = preload_search_by_type("elf kernel"); 1540 if (kmdp == NULL) 1541 kmdp = preload_search_by_type("elf64 kernel"); 1542 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 1543 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + KERNBASE; 1544#ifdef DDB 1545 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 1546 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 1547#endif 1548 1549 /* Init basic tunables, hz etc */ 1550 init_param1(); 1551 1552 /* 1553 * make gdt memory segments 1554 */ 1555 for (x = 0; x < NGDT; x++) { 1556 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) && 1557 x != GUSERLDT_SEL && x != (GUSERLDT_SEL) + 1) 1558 ssdtosd(&gdt_segs[x], &gdt[x]); 1559 } 1560 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&common_tss[0]; 1561 ssdtosyssd(&gdt_segs[GPROC0_SEL], 1562 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1563 1564 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 1565 r_gdt.rd_base = (long) gdt; 1566 lgdt(&r_gdt); 1567 pc = &__pcpu[0]; 1568 1569 wrmsr(MSR_FSBASE, 0); /* User value */ 1570 wrmsr(MSR_GSBASE, (u_int64_t)pc); 1571 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ 1572 1573 pcpu_init(pc, 0, sizeof(struct pcpu)); 1574 dpcpu_init((void *)(physfree + KERNBASE), 0); 1575 physfree += DPCPU_SIZE; 1576 PCPU_SET(prvspace, pc); 1577 PCPU_SET(curthread, &thread0); 1578 PCPU_SET(curpcb, thread0.td_pcb); 1579 PCPU_SET(tssp, &common_tss[0]); 1580 PCPU_SET(commontssp, &common_tss[0]); 1581 PCPU_SET(tss, (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1582 PCPU_SET(ldt, (struct system_segment_descriptor *)&gdt[GUSERLDT_SEL]); 1583 PCPU_SET(fs32p, &gdt[GUFS32_SEL]); 1584 PCPU_SET(gs32p, &gdt[GUGS32_SEL]); 1585 1586 /* 1587 * Initialize mutexes. 1588 * 1589 * icu_lock: in order to allow an interrupt to occur in a critical 1590 * section, to set pcpu->ipending (etc...) properly, we 1591 * must be able to get the icu lock, so it can't be 1592 * under witness. 1593 */ 1594 mutex_init(); 1595 mtx_init(&icu_lock, "icu", NULL, MTX_SPIN | MTX_NOWITNESS); 1596 mtx_init(&dt_lock, "descriptor tables", NULL, MTX_DEF); 1597 1598 /* exceptions */ 1599 for (x = 0; x < NIDT; x++) 1600 setidt(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 1601 setidt(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0); 1602 setidt(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0); 1603 setidt(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 2); 1604 setidt(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0); 1605 setidt(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0); 1606 setidt(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0); 1607 setidt(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0); 1608 setidt(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0); 1609 setidt(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1); 1610 setidt(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0); 1611 setidt(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0); 1612 setidt(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0); 1613 setidt(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0); 1614 setidt(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0); 1615 setidt(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0); 1616 setidt(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0); 1617 setidt(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0); 1618 setidt(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0); 1619 setidt(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0); 1620 1621 r_idt.rd_limit = sizeof(idt0) - 1; 1622 r_idt.rd_base = (long) idt; 1623 lidt(&r_idt); 1624 1625 /* 1626 * Initialize the i8254 before the console so that console 1627 * initialization can use DELAY(). 1628 */ 1629 i8254_init(); 1630 1631 /* 1632 * Initialize the console before we print anything out. 1633 */ 1634 cninit(); 1635 1636#ifdef DEV_ISA 1637#ifdef DEV_ATPIC 1638 elcr_probe(); 1639 atpic_startup(); 1640#else 1641 /* Reset and mask the atpics and leave them shut down. */ 1642 atpic_reset(); 1643 1644 /* 1645 * Point the ICU spurious interrupt vectors at the APIC spurious 1646 * interrupt handler. 1647 */ 1648 setidt(IDT_IO_INTS + 7, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1649 setidt(IDT_IO_INTS + 15, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1650#endif 1651#else 1652#error "have you forgotten the isa device?"; 1653#endif 1654 1655 kdb_init(); 1656 1657#ifdef KDB 1658 if (boothowto & RB_KDB) 1659 kdb_enter(KDB_WHY_BOOTFLAGS, 1660 "Boot flags requested debugger"); 1661#endif 1662 1663 identify_cpu(); /* Final stage of CPU initialization */ 1664 initializecpu(); /* Initialize CPU registers */ 1665 initializecpucache(); 1666 1667 /* make an initial tss so cpu can get interrupt stack on syscall! */ 1668 common_tss[0].tss_rsp0 = thread0.td_kstack + \ 1669 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb); 1670 /* Ensure the stack is aligned to 16 bytes */ 1671 common_tss[0].tss_rsp0 &= ~0xFul; 1672 PCPU_SET(rsp0, common_tss[0].tss_rsp0); 1673 1674 /* doublefault stack space, runs on ist1 */ 1675 common_tss[0].tss_ist1 = (long)&dblfault_stack[sizeof(dblfault_stack)]; 1676 1677 /* 1678 * NMI stack, runs on ist2. The pcpu pointer is stored just 1679 * above the start of the ist2 stack. 1680 */ 1681 np = ((struct nmi_pcpu *) &nmi0_stack[sizeof(nmi0_stack)]) - 1; 1682 np->np_pcpu = (register_t) pc; 1683 common_tss[0].tss_ist2 = (long) np; 1684 1685 /* Set the IO permission bitmap (empty due to tss seg limit) */ 1686 common_tss[0].tss_iobase = sizeof(struct amd64tss) + 1687 IOPAGES * PAGE_SIZE; 1688 1689 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 1690 ltr(gsel_tss); 1691 1692 /* Set up the fast syscall stuff */ 1693 msr = rdmsr(MSR_EFER) | EFER_SCE; 1694 wrmsr(MSR_EFER, msr); 1695 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 1696 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 1697 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 1698 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 1699 wrmsr(MSR_STAR, msr); 1700 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D); 1701 1702 getmemsize(kmdp, physfree); 1703 init_param2(physmem); 1704 1705 /* now running on new page tables, configured,and u/iom is accessible */ 1706 1707 msgbufinit(msgbufp, MSGBUF_SIZE); 1708 fpuinit(); 1709 1710 /* transfer to user mode */ 1711 1712 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 1713 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 1714 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL); 1715 _ufssel = GSEL(GUFS32_SEL, SEL_UPL); 1716 _ugssel = GSEL(GUGS32_SEL, SEL_UPL); 1717 1718 load_ds(_udatasel); 1719 load_es(_udatasel); 1720 load_fs(_ufssel); 1721 1722 /* setup proc 0's pcb */ 1723 thread0.td_pcb->pcb_flags = 0; 1724 thread0.td_pcb->pcb_cr3 = KPML4phys; 1725 thread0.td_frame = &proc0_tf; 1726 1727 env = getenv("kernelname"); 1728 if (env != NULL) 1729 strlcpy(kernelname, env, sizeof(kernelname)); 1730 1731#ifdef XENHVM 1732 if (inw(0x10) == 0x49d2) { 1733 if (bootverbose) 1734 printf("Xen detected: disabling emulated block and network devices\n"); 1735 outw(0x10, 3); 1736 } 1737#endif 1738 1739 if (cpu_probe_amdc1e()) 1740 cpu_idle_fn = cpu_idle_amdc1e; 1741 1742 /* Location of kernel stack for locore */ 1743 return ((u_int64_t)thread0.td_pcb); 1744} 1745 1746void 1747cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size) 1748{ 1749 1750 pcpu->pc_acpi_id = 0xffffffff; 1751} 1752 1753void 1754spinlock_enter(void) 1755{ 1756 struct thread *td; 1757 1758 td = curthread; 1759 if (td->td_md.md_spinlock_count == 0) 1760 td->td_md.md_saved_flags = intr_disable(); 1761 td->td_md.md_spinlock_count++; 1762 critical_enter(); 1763} 1764 1765void 1766spinlock_exit(void) 1767{ 1768 struct thread *td; 1769 1770 td = curthread; 1771 critical_exit(); 1772 td->td_md.md_spinlock_count--; 1773 if (td->td_md.md_spinlock_count == 0) 1774 intr_restore(td->td_md.md_saved_flags); 1775} 1776 1777/* 1778 * Construct a PCB from a trapframe. This is called from kdb_trap() where 1779 * we want to start a backtrace from the function that caused us to enter 1780 * the debugger. We have the context in the trapframe, but base the trace 1781 * on the PCB. The PCB doesn't have to be perfect, as long as it contains 1782 * enough for a backtrace. 1783 */ 1784void 1785makectx(struct trapframe *tf, struct pcb *pcb) 1786{ 1787 1788 pcb->pcb_r12 = tf->tf_r12; 1789 pcb->pcb_r13 = tf->tf_r13; 1790 pcb->pcb_r14 = tf->tf_r14; 1791 pcb->pcb_r15 = tf->tf_r15; 1792 pcb->pcb_rbp = tf->tf_rbp; 1793 pcb->pcb_rbx = tf->tf_rbx; 1794 pcb->pcb_rip = tf->tf_rip; 1795 pcb->pcb_rsp = (ISPL(tf->tf_cs)) ? tf->tf_rsp : (long)(tf + 1) - 8; 1796} 1797 1798int 1799ptrace_set_pc(struct thread *td, unsigned long addr) 1800{ 1801 td->td_frame->tf_rip = addr; 1802 return (0); 1803} 1804 1805int 1806ptrace_single_step(struct thread *td) 1807{ 1808 td->td_frame->tf_rflags |= PSL_T; 1809 return (0); 1810} 1811 1812int 1813ptrace_clear_single_step(struct thread *td) 1814{ 1815 td->td_frame->tf_rflags &= ~PSL_T; 1816 return (0); 1817} 1818 1819int 1820fill_regs(struct thread *td, struct reg *regs) 1821{ 1822 struct trapframe *tp; 1823 1824 tp = td->td_frame; 1825 regs->r_r15 = tp->tf_r15; 1826 regs->r_r14 = tp->tf_r14; 1827 regs->r_r13 = tp->tf_r13; 1828 regs->r_r12 = tp->tf_r12; 1829 regs->r_r11 = tp->tf_r11; 1830 regs->r_r10 = tp->tf_r10; 1831 regs->r_r9 = tp->tf_r9; 1832 regs->r_r8 = tp->tf_r8; 1833 regs->r_rdi = tp->tf_rdi; 1834 regs->r_rsi = tp->tf_rsi; 1835 regs->r_rbp = tp->tf_rbp; 1836 regs->r_rbx = tp->tf_rbx; 1837 regs->r_rdx = tp->tf_rdx; 1838 regs->r_rcx = tp->tf_rcx; 1839 regs->r_rax = tp->tf_rax; 1840 regs->r_rip = tp->tf_rip; 1841 regs->r_cs = tp->tf_cs; 1842 regs->r_rflags = tp->tf_rflags; 1843 regs->r_rsp = tp->tf_rsp; 1844 regs->r_ss = tp->tf_ss; 1845 if (tp->tf_flags & TF_HASSEGS) { 1846 regs->r_ds = tp->tf_ds; 1847 regs->r_es = tp->tf_es; 1848 regs->r_fs = tp->tf_fs; 1849 regs->r_gs = tp->tf_gs; 1850 } else { 1851 regs->r_ds = 0; 1852 regs->r_es = 0; 1853 regs->r_fs = 0; 1854 regs->r_gs = 0; 1855 } 1856 return (0); 1857} 1858 1859int 1860set_regs(struct thread *td, struct reg *regs) 1861{ 1862 struct trapframe *tp; 1863 register_t rflags; 1864 1865 tp = td->td_frame; 1866 rflags = regs->r_rflags & 0xffffffff; 1867 if (!EFL_SECURE(rflags, tp->tf_rflags) || !CS_SECURE(regs->r_cs)) 1868 return (EINVAL); 1869 tp->tf_r15 = regs->r_r15; 1870 tp->tf_r14 = regs->r_r14; 1871 tp->tf_r13 = regs->r_r13; 1872 tp->tf_r12 = regs->r_r12; 1873 tp->tf_r11 = regs->r_r11; 1874 tp->tf_r10 = regs->r_r10; 1875 tp->tf_r9 = regs->r_r9; 1876 tp->tf_r8 = regs->r_r8; 1877 tp->tf_rdi = regs->r_rdi; 1878 tp->tf_rsi = regs->r_rsi; 1879 tp->tf_rbp = regs->r_rbp; 1880 tp->tf_rbx = regs->r_rbx; 1881 tp->tf_rdx = regs->r_rdx; 1882 tp->tf_rcx = regs->r_rcx; 1883 tp->tf_rax = regs->r_rax; 1884 tp->tf_rip = regs->r_rip; 1885 tp->tf_cs = regs->r_cs; 1886 tp->tf_rflags = rflags; 1887 tp->tf_rsp = regs->r_rsp; 1888 tp->tf_ss = regs->r_ss; 1889 if (0) { /* XXXKIB */ 1890 tp->tf_ds = regs->r_ds; 1891 tp->tf_es = regs->r_es; 1892 tp->tf_fs = regs->r_fs; 1893 tp->tf_gs = regs->r_gs; 1894 tp->tf_flags = TF_HASSEGS; 1895 } 1896 td->td_pcb->pcb_flags |= PCB_FULLCTX; 1897 return (0); 1898} 1899 1900/* XXX check all this stuff! */ 1901/* externalize from sv_xmm */ 1902static void 1903fill_fpregs_xmm(struct savefpu *sv_xmm, struct fpreg *fpregs) 1904{ 1905 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 1906 struct envxmm *penv_xmm = &sv_xmm->sv_env; 1907 int i; 1908 1909 /* pcb -> fpregs */ 1910 bzero(fpregs, sizeof(*fpregs)); 1911 1912 /* FPU control/status */ 1913 penv_fpreg->en_cw = penv_xmm->en_cw; 1914 penv_fpreg->en_sw = penv_xmm->en_sw; 1915 penv_fpreg->en_tw = penv_xmm->en_tw; 1916 penv_fpreg->en_opcode = penv_xmm->en_opcode; 1917 penv_fpreg->en_rip = penv_xmm->en_rip; 1918 penv_fpreg->en_rdp = penv_xmm->en_rdp; 1919 penv_fpreg->en_mxcsr = penv_xmm->en_mxcsr; 1920 penv_fpreg->en_mxcsr_mask = penv_xmm->en_mxcsr_mask; 1921 1922 /* FPU registers */ 1923 for (i = 0; i < 8; ++i) 1924 bcopy(sv_xmm->sv_fp[i].fp_acc.fp_bytes, fpregs->fpr_acc[i], 10); 1925 1926 /* SSE registers */ 1927 for (i = 0; i < 16; ++i) 1928 bcopy(sv_xmm->sv_xmm[i].xmm_bytes, fpregs->fpr_xacc[i], 16); 1929} 1930 1931/* internalize from fpregs into sv_xmm */ 1932static void 1933set_fpregs_xmm(struct fpreg *fpregs, struct savefpu *sv_xmm) 1934{ 1935 struct envxmm *penv_xmm = &sv_xmm->sv_env; 1936 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 1937 int i; 1938 1939 /* fpregs -> pcb */ 1940 /* FPU control/status */ 1941 penv_xmm->en_cw = penv_fpreg->en_cw; 1942 penv_xmm->en_sw = penv_fpreg->en_sw; 1943 penv_xmm->en_tw = penv_fpreg->en_tw; 1944 penv_xmm->en_opcode = penv_fpreg->en_opcode; 1945 penv_xmm->en_rip = penv_fpreg->en_rip; 1946 penv_xmm->en_rdp = penv_fpreg->en_rdp; 1947 penv_xmm->en_mxcsr = penv_fpreg->en_mxcsr; 1948 penv_xmm->en_mxcsr_mask = penv_fpreg->en_mxcsr_mask & cpu_mxcsr_mask; 1949 1950 /* FPU registers */ 1951 for (i = 0; i < 8; ++i) 1952 bcopy(fpregs->fpr_acc[i], sv_xmm->sv_fp[i].fp_acc.fp_bytes, 10); 1953 1954 /* SSE registers */ 1955 for (i = 0; i < 16; ++i) 1956 bcopy(fpregs->fpr_xacc[i], sv_xmm->sv_xmm[i].xmm_bytes, 16); 1957} 1958 1959/* externalize from td->pcb */ 1960int 1961fill_fpregs(struct thread *td, struct fpreg *fpregs) 1962{ 1963 1964 fill_fpregs_xmm(&td->td_pcb->pcb_save, fpregs); 1965 return (0); 1966} 1967 1968/* internalize to td->pcb */ 1969int 1970set_fpregs(struct thread *td, struct fpreg *fpregs) 1971{ 1972 1973 set_fpregs_xmm(fpregs, &td->td_pcb->pcb_save); 1974 return (0); 1975} 1976 1977/* 1978 * Get machine context. 1979 */ 1980int 1981get_mcontext(struct thread *td, mcontext_t *mcp, int flags) 1982{ 1983 struct trapframe *tp; 1984 1985 tp = td->td_frame; 1986 PROC_LOCK(curthread->td_proc); 1987 mcp->mc_onstack = sigonstack(tp->tf_rsp); 1988 PROC_UNLOCK(curthread->td_proc); 1989 mcp->mc_r15 = tp->tf_r15; 1990 mcp->mc_r14 = tp->tf_r14; 1991 mcp->mc_r13 = tp->tf_r13; 1992 mcp->mc_r12 = tp->tf_r12; 1993 mcp->mc_r11 = tp->tf_r11; 1994 mcp->mc_r10 = tp->tf_r10; 1995 mcp->mc_r9 = tp->tf_r9; 1996 mcp->mc_r8 = tp->tf_r8; 1997 mcp->mc_rdi = tp->tf_rdi; 1998 mcp->mc_rsi = tp->tf_rsi; 1999 mcp->mc_rbp = tp->tf_rbp; 2000 mcp->mc_rbx = tp->tf_rbx; 2001 mcp->mc_rcx = tp->tf_rcx; 2002 mcp->mc_rflags = tp->tf_rflags; 2003 if (flags & GET_MC_CLEAR_RET) { 2004 mcp->mc_rax = 0; 2005 mcp->mc_rdx = 0; 2006 mcp->mc_rflags &= ~PSL_C; 2007 } else { 2008 mcp->mc_rax = tp->tf_rax; 2009 mcp->mc_rdx = tp->tf_rdx; 2010 } 2011 mcp->mc_rip = tp->tf_rip; 2012 mcp->mc_cs = tp->tf_cs; 2013 mcp->mc_rsp = tp->tf_rsp; 2014 mcp->mc_ss = tp->tf_ss; 2015 mcp->mc_ds = tp->tf_ds; 2016 mcp->mc_es = tp->tf_es; 2017 mcp->mc_fs = tp->tf_fs; 2018 mcp->mc_gs = tp->tf_gs; 2019 mcp->mc_flags = tp->tf_flags; 2020 mcp->mc_len = sizeof(*mcp); 2021 get_fpcontext(td, mcp); 2022 mcp->mc_fsbase = td->td_pcb->pcb_fsbase; 2023 mcp->mc_gsbase = td->td_pcb->pcb_gsbase; 2024 return (0); 2025} 2026 2027/* 2028 * Set machine context. 2029 * 2030 * However, we don't set any but the user modifiable flags, and we won't 2031 * touch the cs selector. 2032 */ 2033int 2034set_mcontext(struct thread *td, const mcontext_t *mcp) 2035{ 2036 struct trapframe *tp; 2037 long rflags; 2038 int ret; 2039 2040 tp = td->td_frame; 2041 if (mcp->mc_len != sizeof(*mcp) || 2042 (mcp->mc_flags & ~_MC_FLAG_MASK) != 0) 2043 return (EINVAL); 2044 rflags = (mcp->mc_rflags & PSL_USERCHANGE) | 2045 (tp->tf_rflags & ~PSL_USERCHANGE); 2046 ret = set_fpcontext(td, mcp); 2047 if (ret != 0) 2048 return (ret); 2049 tp->tf_r15 = mcp->mc_r15; 2050 tp->tf_r14 = mcp->mc_r14; 2051 tp->tf_r13 = mcp->mc_r13; 2052 tp->tf_r12 = mcp->mc_r12; 2053 tp->tf_r11 = mcp->mc_r11; 2054 tp->tf_r10 = mcp->mc_r10; 2055 tp->tf_r9 = mcp->mc_r9; 2056 tp->tf_r8 = mcp->mc_r8; 2057 tp->tf_rdi = mcp->mc_rdi; 2058 tp->tf_rsi = mcp->mc_rsi; 2059 tp->tf_rbp = mcp->mc_rbp; 2060 tp->tf_rbx = mcp->mc_rbx; 2061 tp->tf_rdx = mcp->mc_rdx; 2062 tp->tf_rcx = mcp->mc_rcx; 2063 tp->tf_rax = mcp->mc_rax; 2064 tp->tf_rip = mcp->mc_rip; 2065 tp->tf_rflags = rflags; 2066 tp->tf_rsp = mcp->mc_rsp; 2067 tp->tf_ss = mcp->mc_ss; 2068 tp->tf_flags = mcp->mc_flags; 2069 if (tp->tf_flags & TF_HASSEGS) { 2070 tp->tf_ds = mcp->mc_ds; 2071 tp->tf_es = mcp->mc_es; 2072 tp->tf_fs = mcp->mc_fs; 2073 tp->tf_gs = mcp->mc_gs; 2074 } 2075 if (mcp->mc_flags & _MC_HASBASES) { 2076 td->td_pcb->pcb_fsbase = mcp->mc_fsbase; 2077 td->td_pcb->pcb_gsbase = mcp->mc_gsbase; 2078 } 2079 td->td_pcb->pcb_flags |= PCB_FULLCTX; 2080 td->td_pcb->pcb_full_iret = 1; 2081 return (0); 2082} 2083 2084static void 2085get_fpcontext(struct thread *td, mcontext_t *mcp) 2086{ 2087 2088 mcp->mc_ownedfp = fpugetregs(td, (struct savefpu *)&mcp->mc_fpstate); 2089 mcp->mc_fpformat = fpuformat(); 2090} 2091 2092static int 2093set_fpcontext(struct thread *td, const mcontext_t *mcp) 2094{ 2095 struct savefpu *fpstate; 2096 2097 if (mcp->mc_fpformat == _MC_FPFMT_NODEV) 2098 return (0); 2099 else if (mcp->mc_fpformat != _MC_FPFMT_XMM) 2100 return (EINVAL); 2101 else if (mcp->mc_ownedfp == _MC_FPOWNED_NONE) 2102 /* We don't care what state is left in the FPU or PCB. */ 2103 fpstate_drop(td); 2104 else if (mcp->mc_ownedfp == _MC_FPOWNED_FPU || 2105 mcp->mc_ownedfp == _MC_FPOWNED_PCB) { 2106 /* 2107 * XXX we violate the dubious requirement that fpusetregs() 2108 * be called with interrupts disabled. 2109 * XXX obsolete on trap-16 systems? 2110 */ 2111 fpstate = (struct savefpu *)&mcp->mc_fpstate; 2112 fpstate->sv_env.en_mxcsr &= cpu_mxcsr_mask; 2113 fpusetregs(td, fpstate); 2114 } else 2115 return (EINVAL); 2116 return (0); 2117} 2118 2119void 2120fpstate_drop(struct thread *td) 2121{ 2122 register_t s; 2123 2124 s = intr_disable(); 2125 if (PCPU_GET(fpcurthread) == td) 2126 fpudrop(); 2127 /* 2128 * XXX force a full drop of the fpu. The above only drops it if we 2129 * owned it. 2130 * 2131 * XXX I don't much like fpugetregs()'s semantics of doing a full 2132 * drop. Dropping only to the pcb matches fnsave's behaviour. 2133 * We only need to drop to !PCB_INITDONE in sendsig(). But 2134 * sendsig() is the only caller of fpugetregs()... perhaps we just 2135 * have too many layers. 2136 */ 2137 curthread->td_pcb->pcb_flags &= ~PCB_FPUINITDONE; 2138 intr_restore(s); 2139} 2140 2141int 2142fill_dbregs(struct thread *td, struct dbreg *dbregs) 2143{ 2144 struct pcb *pcb; 2145 2146 if (td == NULL) { 2147 dbregs->dr[0] = rdr0(); 2148 dbregs->dr[1] = rdr1(); 2149 dbregs->dr[2] = rdr2(); 2150 dbregs->dr[3] = rdr3(); 2151 dbregs->dr[6] = rdr6(); 2152 dbregs->dr[7] = rdr7(); 2153 } else { 2154 pcb = td->td_pcb; 2155 dbregs->dr[0] = pcb->pcb_dr0; 2156 dbregs->dr[1] = pcb->pcb_dr1; 2157 dbregs->dr[2] = pcb->pcb_dr2; 2158 dbregs->dr[3] = pcb->pcb_dr3; 2159 dbregs->dr[6] = pcb->pcb_dr6; 2160 dbregs->dr[7] = pcb->pcb_dr7; 2161 } 2162 dbregs->dr[4] = 0; 2163 dbregs->dr[5] = 0; 2164 dbregs->dr[8] = 0; 2165 dbregs->dr[9] = 0; 2166 dbregs->dr[10] = 0; 2167 dbregs->dr[11] = 0; 2168 dbregs->dr[12] = 0; 2169 dbregs->dr[13] = 0; 2170 dbregs->dr[14] = 0; 2171 dbregs->dr[15] = 0; 2172 return (0); 2173} 2174 2175int 2176set_dbregs(struct thread *td, struct dbreg *dbregs) 2177{ 2178 struct pcb *pcb; 2179 int i; 2180 2181 if (td == NULL) { 2182 load_dr0(dbregs->dr[0]); 2183 load_dr1(dbregs->dr[1]); 2184 load_dr2(dbregs->dr[2]); 2185 load_dr3(dbregs->dr[3]); 2186 load_dr6(dbregs->dr[6]); 2187 load_dr7(dbregs->dr[7]); 2188 } else { 2189 /* 2190 * Don't let an illegal value for dr7 get set. Specifically, 2191 * check for undefined settings. Setting these bit patterns 2192 * result in undefined behaviour and can lead to an unexpected 2193 * TRCTRAP or a general protection fault right here. 2194 * Upper bits of dr6 and dr7 must not be set 2195 */ 2196 for (i = 0; i < 4; i++) { 2197 if (DBREG_DR7_ACCESS(dbregs->dr[7], i) == 0x02) 2198 return (EINVAL); 2199 if (td->td_frame->tf_cs == _ucode32sel && 2200 DBREG_DR7_LEN(dbregs->dr[7], i) == DBREG_DR7_LEN_8) 2201 return (EINVAL); 2202 } 2203 if ((dbregs->dr[6] & 0xffffffff00000000ul) != 0 || 2204 (dbregs->dr[7] & 0xffffffff00000000ul) != 0) 2205 return (EINVAL); 2206 2207 pcb = td->td_pcb; 2208 2209 /* 2210 * Don't let a process set a breakpoint that is not within the 2211 * process's address space. If a process could do this, it 2212 * could halt the system by setting a breakpoint in the kernel 2213 * (if ddb was enabled). Thus, we need to check to make sure 2214 * that no breakpoints are being enabled for addresses outside 2215 * process's address space. 2216 * 2217 * XXX - what about when the watched area of the user's 2218 * address space is written into from within the kernel 2219 * ... wouldn't that still cause a breakpoint to be generated 2220 * from within kernel mode? 2221 */ 2222 2223 if (DBREG_DR7_ENABLED(dbregs->dr[7], 0)) { 2224 /* dr0 is enabled */ 2225 if (dbregs->dr[0] >= VM_MAXUSER_ADDRESS) 2226 return (EINVAL); 2227 } 2228 if (DBREG_DR7_ENABLED(dbregs->dr[7], 1)) { 2229 /* dr1 is enabled */ 2230 if (dbregs->dr[1] >= VM_MAXUSER_ADDRESS) 2231 return (EINVAL); 2232 } 2233 if (DBREG_DR7_ENABLED(dbregs->dr[7], 2)) { 2234 /* dr2 is enabled */ 2235 if (dbregs->dr[2] >= VM_MAXUSER_ADDRESS) 2236 return (EINVAL); 2237 } 2238 if (DBREG_DR7_ENABLED(dbregs->dr[7], 3)) { 2239 /* dr3 is enabled */ 2240 if (dbregs->dr[3] >= VM_MAXUSER_ADDRESS) 2241 return (EINVAL); 2242 } 2243 2244 pcb->pcb_dr0 = dbregs->dr[0]; 2245 pcb->pcb_dr1 = dbregs->dr[1]; 2246 pcb->pcb_dr2 = dbregs->dr[2]; 2247 pcb->pcb_dr3 = dbregs->dr[3]; 2248 pcb->pcb_dr6 = dbregs->dr[6]; 2249 pcb->pcb_dr7 = dbregs->dr[7]; 2250 2251 pcb->pcb_flags |= PCB_DBREGS; 2252 } 2253 2254 return (0); 2255} 2256 2257void 2258reset_dbregs(void) 2259{ 2260 2261 load_dr7(0); /* Turn off the control bits first */ 2262 load_dr0(0); 2263 load_dr1(0); 2264 load_dr2(0); 2265 load_dr3(0); 2266 load_dr6(0); 2267} 2268 2269/* 2270 * Return > 0 if a hardware breakpoint has been hit, and the 2271 * breakpoint was in user space. Return 0, otherwise. 2272 */ 2273int 2274user_dbreg_trap(void) 2275{ 2276 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */ 2277 u_int64_t bp; /* breakpoint bits extracted from dr6 */ 2278 int nbp; /* number of breakpoints that triggered */ 2279 caddr_t addr[4]; /* breakpoint addresses */ 2280 int i; 2281 2282 dr7 = rdr7(); 2283 if ((dr7 & 0x000000ff) == 0) { 2284 /* 2285 * all GE and LE bits in the dr7 register are zero, 2286 * thus the trap couldn't have been caused by the 2287 * hardware debug registers 2288 */ 2289 return 0; 2290 } 2291 2292 nbp = 0; 2293 dr6 = rdr6(); 2294 bp = dr6 & 0x0000000f; 2295 2296 if (!bp) { 2297 /* 2298 * None of the breakpoint bits are set meaning this 2299 * trap was not caused by any of the debug registers 2300 */ 2301 return 0; 2302 } 2303 2304 /* 2305 * at least one of the breakpoints were hit, check to see 2306 * which ones and if any of them are user space addresses 2307 */ 2308 2309 if (bp & 0x01) { 2310 addr[nbp++] = (caddr_t)rdr0(); 2311 } 2312 if (bp & 0x02) { 2313 addr[nbp++] = (caddr_t)rdr1(); 2314 } 2315 if (bp & 0x04) { 2316 addr[nbp++] = (caddr_t)rdr2(); 2317 } 2318 if (bp & 0x08) { 2319 addr[nbp++] = (caddr_t)rdr3(); 2320 } 2321 2322 for (i = 0; i < nbp; i++) { 2323 if (addr[i] < (caddr_t)VM_MAXUSER_ADDRESS) { 2324 /* 2325 * addr[i] is in user space 2326 */ 2327 return nbp; 2328 } 2329 } 2330 2331 /* 2332 * None of the breakpoints are in user space. 2333 */ 2334 return 0; 2335} 2336 2337#ifdef KDB 2338 2339/* 2340 * Provide inb() and outb() as functions. They are normally only available as 2341 * inline functions, thus cannot be called from the debugger. 2342 */ 2343 2344/* silence compiler warnings */ 2345u_char inb_(u_short); 2346void outb_(u_short, u_char); 2347 2348u_char 2349inb_(u_short port) 2350{ 2351 return inb(port); 2352} 2353 2354void 2355outb_(u_short port, u_char data) 2356{ 2357 outb(port, data); 2358} 2359 2360#endif /* KDB */ 2361