t4_chip_type.h revision 273806
1/* 2 * This file is part of the Chelsio T4 Ethernet driver. 3 * 4 * Copyright (C) 2003-2014 Chelsio Communications. All rights reserved. 5 * 6 * This program is distributed in the hope that it will be useful, but WITHOUT 7 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 8 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 9 * release for licensing terms and conditions. 10 */ 11#ifndef __T4_CHIP_TYPE_H__ 12#define __T4_CHIP_TYPE_H__ 13 14/* 15 * All T4 and later chips have their PCI-E Device IDs encoded as 0xVFPP where: 16 * 17 * V = "4" for T4; "5" for T5, etc. or 18 * = "a" for T4 FPGA; "b" for T4 FPGA, etc. 19 * F = "0" for PF 0..3; "4".."7" for PF4..7; and "8" for VFs 20 * PP = adapter product designation 21 * 22 * We use the "version" (V) of the adpater to code the Chip Version above 23 * but separate out the FPGA as a separate boolean as per above. 24 */ 25#define CHELSIO_PCI_ID_VER(__DeviceID) ((__DeviceID) >> 12) 26#define CHELSIO_PCI_ID_FUNC(__DeviceID) (((__DeviceID) >> 8) & 0xf) 27#define CHELSIO_PCI_ID_PROD(__DeviceID) ((__DeviceID) & 0xff) 28 29#define CHELSIO_T4 0x4 30#define CHELSIO_T4_FPGA 0xa 31#define CHELSIO_T5 0x5 32#define CHELSIO_T5_FPGA 0xb 33 34/* 35 * Translate a PCI Device ID to a base Chelsio Chip Version -- CHELSIO_T4, 36 * CHELSIO_T5, etc. If it weren't for the screwed up numbering of the FPGAs 37 * we could do this simply as DeviceID >> 12 (because we know the real 38 * encoding oc CHELSIO_Tx identifiers). However, the FPGAs _do_ have weird 39 * Device IDs so we need to do this translation here. Note that only constant 40 * arithmetic and comparisons can be done here since this is being used to 41 * initialize static tables, etc. 42 * 43 * Finally: This will of course need to be expanded as future chips are 44 * developed. 45 */ 46#define CHELSIO_PCI_ID_CHIP_VERSION(__DeviceID) \ 47 (CHELSIO_PCI_ID_VER(__DeviceID) == CHELSIO_T4 || \ 48 CHELSIO_PCI_ID_VER(__DeviceID) == CHELSIO_T4_FPGA \ 49 ? CHELSIO_T4 \ 50 : CHELSIO_T5) 51 52/* 53 * Internally we code the Chelsio T4 Family "Chip Code" as a tuple: 54 * 55 * (Is FPGA, Chip Version, Chip Revision) 56 * 57 * where: 58 * 59 * Is FPGA: is 0/1 indicating whether we're working with an FPGA 60 * Chip Version: is T4, T5, etc. 61 * Chip Revision: is the FAB "spin" of the Chip Version. 62 */ 63#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision)) 64#define CHELSIO_CHIP_FPGA 0x100 65#define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf) 66#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf) 67 68enum chip_type { 69 T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1), 70 T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2), 71 T4_FIRST_REV = T4_A1, 72 T4_LAST_REV = T4_A2, 73 74 T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0), 75 T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0), 76 T5_FIRST_REV = T5_A0, 77 T5_LAST_REV = T5_A1, 78}; 79 80static inline int is_t4(enum chip_type chip) 81{ 82 return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4); 83} 84 85static inline int is_t5(enum chip_type chip) 86{ 87 88 return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5); 89} 90 91static inline int is_fpga(enum chip_type chip) 92{ 93 return chip & CHELSIO_CHIP_FPGA; 94} 95 96#endif /* __T4_CHIP_TYPE_H__ */ 97