InstrInfoEmitter.cpp revision 302408
1236769Sobrien//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. --*- C++ -*-===// 2236769Sobrien// 3236769Sobrien// The LLVM Compiler Infrastructure 4236769Sobrien// 5236769Sobrien// This file is distributed under the University of Illinois Open Source 6236769Sobrien// License. See LICENSE.TXT for details. 7236769Sobrien// 8236769Sobrien//===----------------------------------------------------------------------===// 9236769Sobrien// 10236769Sobrien// This tablegen backend is responsible for emitting a description of the target 11236769Sobrien// instruction set for the code generator. 12236769Sobrien// 13236769Sobrien//===----------------------------------------------------------------------===// 14236769Sobrien 15236769Sobrien#include "CodeGenDAGPatterns.h" 16236769Sobrien#include "CodeGenSchedule.h" 17236769Sobrien#include "CodeGenTarget.h" 18236769Sobrien#include "SequenceToOffsetTable.h" 19236769Sobrien#include "TableGenBackends.h" 20236769Sobrien#include "llvm/ADT/StringExtras.h" 21236769Sobrien#include "llvm/TableGen/Error.h" 22236769Sobrien#include "llvm/TableGen/Record.h" 23236769Sobrien#include "llvm/TableGen/TableGenBackend.h" 24236769Sobrien#include <algorithm> 25236769Sobrien#include <cstdio> 26236769Sobrien#include <map> 27236769Sobrien#include <vector> 28236769Sobrien 29236769Sobrienusing namespace llvm; 30236769Sobrien 31236769Sobriennamespace { 32236769Sobrienclass InstrInfoEmitter { 33236769Sobrien RecordKeeper &Records; 34236769Sobrien CodeGenDAGPatterns CDP; 35236769Sobrien const CodeGenSchedModels &SchedModels; 36236769Sobrien 37236769Sobrienpublic: 38236769Sobrien InstrInfoEmitter(RecordKeeper &R): 39236769Sobrien Records(R), CDP(R), SchedModels(CDP.getTargetInfo().getSchedModels()) {} 40236769Sobrien 41236769Sobrien // run - Output the instruction set description. 42236769Sobrien void run(raw_ostream &OS); 43236769Sobrien 44236769Sobrienprivate: 45236769Sobrien void emitEnums(raw_ostream &OS); 46236769Sobrien 47236769Sobrien typedef std::map<std::vector<std::string>, unsigned> OperandInfoMapTy; 48236769Sobrien 49236769Sobrien /// The keys of this map are maps which have OpName enum values as their keys 50236769Sobrien /// and instruction operand indices as their values. The values of this map 51236769Sobrien /// are lists of instruction names. 52236769Sobrien typedef std::map<std::map<unsigned, unsigned>, 53236769Sobrien std::vector<std::string> > OpNameMapTy; 54236769Sobrien typedef std::map<std::string, unsigned>::iterator StrUintMapIter; 55236769Sobrien void emitRecord(const CodeGenInstruction &Inst, unsigned Num, 56236769Sobrien Record *InstrInfo, 57236769Sobrien std::map<std::vector<Record*>, unsigned> &EL, 58236769Sobrien const OperandInfoMapTy &OpInfo, 59236769Sobrien raw_ostream &OS); 60236769Sobrien void emitOperandTypesEnum(raw_ostream &OS, const CodeGenTarget &Target); 61236769Sobrien void initOperandMapData( 62292068Ssjg const std::vector<const CodeGenInstruction *> &NumberedInstructions, 63292068Ssjg const std::string &Namespace, 64292068Ssjg std::map<std::string, unsigned> &Operands, 65292068Ssjg OpNameMapTy &OperandMap); 66292068Ssjg void emitOperandNameMappings(raw_ostream &OS, const CodeGenTarget &Target, 67292068Ssjg const std::vector<const CodeGenInstruction*> &NumberedInstructions); 68236769Sobrien 69236769Sobrien // Operand information. 70236769Sobrien void EmitOperandInfo(raw_ostream &OS, OperandInfoMapTy &OperandInfoIDs); 71236769Sobrien std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst); 72236769Sobrien}; 73236769Sobrien} // end anonymous namespace 74236769Sobrien 75236769Sobrienstatic void PrintDefList(const std::vector<Record*> &Uses, 76236769Sobrien unsigned Num, raw_ostream &OS) { 77236769Sobrien OS << "static const MCPhysReg ImplicitList" << Num << "[] = { "; 78236769Sobrien for (unsigned i = 0, e = Uses.size(); i != e; ++i) 79236769Sobrien OS << getQualifiedName(Uses[i]) << ", "; 80236769Sobrien OS << "0 };\n"; 81236769Sobrien} 82236769Sobrien 83236769Sobrien//===----------------------------------------------------------------------===// 84236769Sobrien// Operand Info Emission. 85236769Sobrien//===----------------------------------------------------------------------===// 86236769Sobrien 87236769Sobrienstd::vector<std::string> 88236769SobrienInstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { 89236769Sobrien std::vector<std::string> Result; 90236769Sobrien 91236769Sobrien for (auto &Op : Inst.Operands) { 92236769Sobrien // Handle aggregate operands and normal operands the same way by expanding 93236769Sobrien // either case into a list of operands for this op. 94236769Sobrien std::vector<CGIOperandList::OperandInfo> OperandList; 95236769Sobrien 96236769Sobrien // This might be a multiple operand thing. Targets like X86 have 97236769Sobrien // registers in their multi-operand operands. It may also be an anonymous 98236769Sobrien // operand, which has a single operand, but no declared class for the 99236769Sobrien // operand. 100236769Sobrien DagInit *MIOI = Op.MIOperandInfo; 101236769Sobrien 102236769Sobrien if (!MIOI || MIOI->getNumArgs() == 0) { 103236769Sobrien // Single, anonymous, operand. 104236769Sobrien OperandList.push_back(Op); 105236769Sobrien } else { 106236769Sobrien for (unsigned j = 0, e = Op.MINumOperands; j != e; ++j) { 107236769Sobrien OperandList.push_back(Op); 108236769Sobrien 109236769Sobrien Record *OpR = cast<DefInit>(MIOI->getArg(j))->getDef(); 110236769Sobrien OperandList.back().Rec = OpR; 111236769Sobrien } 112236769Sobrien } 113236769Sobrien 114236769Sobrien for (unsigned j = 0, e = OperandList.size(); j != e; ++j) { 115236769Sobrien Record *OpR = OperandList[j].Rec; 116236769Sobrien std::string Res; 117236769Sobrien 118236769Sobrien if (OpR->isSubClassOf("RegisterOperand")) 119236769Sobrien OpR = OpR->getValueAsDef("RegClass"); 120236769Sobrien if (OpR->isSubClassOf("RegisterClass")) 121236769Sobrien Res += getQualifiedName(OpR) + "RegClassID, "; 122236769Sobrien else if (OpR->isSubClassOf("PointerLikeRegClass")) 123236769Sobrien Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", "; 124236769Sobrien else 125236769Sobrien // -1 means the operand does not have a fixed register class. 126236769Sobrien Res += "-1, "; 127236769Sobrien 128236769Sobrien // Fill in applicable flags. 129236769Sobrien Res += "0"; 130236769Sobrien 131236769Sobrien // Ptr value whose register class is resolved via callback. 132236769Sobrien if (OpR->isSubClassOf("PointerLikeRegClass")) 133236769Sobrien Res += "|(1<<MCOI::LookupPtrRegClass)"; 134236769Sobrien 135236769Sobrien // Predicate operands. Check to see if the original unexpanded operand 136236769Sobrien // was of type PredicateOp. 137236769Sobrien if (Op.Rec->isSubClassOf("PredicateOp")) 138236769Sobrien Res += "|(1<<MCOI::Predicate)"; 139236769Sobrien 140236769Sobrien // Optional def operands. Check to see if the original unexpanded operand 141236769Sobrien // was of type OptionalDefOperand. 142236769Sobrien if (Op.Rec->isSubClassOf("OptionalDefOperand")) 143236769Sobrien Res += "|(1<<MCOI::OptionalDef)"; 144236769Sobrien 145236769Sobrien // Fill in operand type. 146236769Sobrien Res += ", "; 147236769Sobrien assert(!Op.OperandType.empty() && "Invalid operand type."); 148236769Sobrien Res += Op.OperandType; 149236769Sobrien 150236769Sobrien // Fill in constraint info. 151236769Sobrien Res += ", "; 152236769Sobrien 153276305Sngie const CGIOperandList::ConstraintInfo &Constraint = 154276305Sngie Op.Constraints[j]; 155276305Sngie if (Constraint.isNone()) 156236769Sobrien Res += "0"; 157236769Sobrien else if (Constraint.isEarlyClobber()) 158236769Sobrien Res += "(1 << MCOI::EARLY_CLOBBER)"; 159236769Sobrien else { 160236769Sobrien assert(Constraint.isTied()); 161236769Sobrien Res += "((" + utostr(Constraint.getTiedOperand()) + 162236769Sobrien " << 16) | (1 << MCOI::TIED_TO))"; 163236769Sobrien } 164236769Sobrien 165236769Sobrien Result.push_back(Res); 166236769Sobrien } 167292068Ssjg } 168292068Ssjg 169292068Ssjg return Result; 170236769Sobrien} 171236769Sobrien 172236769Sobrienvoid InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS, 173236769Sobrien OperandInfoMapTy &OperandInfoIDs) { 174236769Sobrien // ID #0 is for no operand info. 175236769Sobrien unsigned OperandListNum = 0; 176236769Sobrien OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum; 177236769Sobrien 178236769Sobrien OS << "\n"; 179276305Sngie const CodeGenTarget &Target = CDP.getTargetInfo(); 180276305Sngie for (const CodeGenInstruction *Inst : Target.instructions()) { 181276305Sngie std::vector<std::string> OperandInfo = GetOperandInfo(*Inst); 182236769Sobrien unsigned &N = OperandInfoIDs[OperandInfo]; 183236769Sobrien if (N != 0) continue; 184236769Sobrien 185236769Sobrien N = ++OperandListNum; 186236769Sobrien OS << "static const MCOperandInfo OperandInfo" << N << "[] = { "; 187236769Sobrien for (const std::string &Info : OperandInfo) 188236769Sobrien OS << "{ " << Info << " }, "; 189236769Sobrien OS << "};\n"; 190236769Sobrien } 191236769Sobrien} 192236769Sobrien 193236769Sobrien/// Initialize data structures for generating operand name mappings. 194236769Sobrien/// 195236769Sobrien/// \param Operands [out] A map used to generate the OpName enum with operand 196236769Sobrien/// names as its keys and operand enum values as its values. 197236769Sobrien/// \param OperandMap [out] A map for representing the operand name mappings for 198236769Sobrien/// each instructions. This is used to generate the OperandMap table as 199236769Sobrien/// well as the getNamedOperandIdx() function. 200236769Sobrienvoid InstrInfoEmitter::initOperandMapData( 201236769Sobrien const std::vector<const CodeGenInstruction *> &NumberedInstructions, 202236769Sobrien const std::string &Namespace, 203236769Sobrien std::map<std::string, unsigned> &Operands, 204236769Sobrien OpNameMapTy &OperandMap) { 205236769Sobrien 206236769Sobrien unsigned NumOperands = 0; 207236769Sobrien for (const CodeGenInstruction *Inst : NumberedInstructions) { 208236769Sobrien if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable")) 209236769Sobrien continue; 210236769Sobrien std::map<unsigned, unsigned> OpList; 211236769Sobrien for (const auto &Info : Inst->Operands) { 212236769Sobrien StrUintMapIter I = Operands.find(Info.Name); 213236769Sobrien 214236769Sobrien if (I == Operands.end()) { 215236769Sobrien I = Operands.insert(Operands.begin(), 216236769Sobrien std::pair<std::string, unsigned>(Info.Name, NumOperands++)); 217236769Sobrien } 218236769Sobrien OpList[I->second] = Info.MIOperandNo; 219236769Sobrien } 220236769Sobrien OperandMap[OpList].push_back(Namespace + "::" + Inst->TheDef->getName()); 221236769Sobrien } 222236769Sobrien} 223236769Sobrien 224236769Sobrien/// Generate a table and function for looking up the indices of operands by 225236769Sobrien/// name. 226236769Sobrien/// 227236769Sobrien/// This code generates: 228236769Sobrien/// - An enum in the llvm::TargetNamespace::OpName namespace, with one entry 229236769Sobrien/// for each operand name. 230236769Sobrien/// - A 2-dimensional table called OperandMap for mapping OpName enum values to 231236769Sobrien/// operand indices. 232236769Sobrien/// - A function called getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) 233236769Sobrien/// for looking up the operand index for an instruction, given a value from 234236769Sobrien/// OpName enum 235236769Sobrienvoid InstrInfoEmitter::emitOperandNameMappings(raw_ostream &OS, 236236769Sobrien const CodeGenTarget &Target, 237236769Sobrien const std::vector<const CodeGenInstruction*> &NumberedInstructions) { 238236769Sobrien 239236769Sobrien const std::string &Namespace = Target.getInstNamespace(); 240236769Sobrien std::string OpNameNS = "OpName"; 241236769Sobrien // Map of operand names to their enumeration value. This will be used to 242236769Sobrien // generate the OpName enum. 243236769Sobrien std::map<std::string, unsigned> Operands; 244236769Sobrien OpNameMapTy OperandMap; 245236769Sobrien 246236769Sobrien initOperandMapData(NumberedInstructions, Namespace, Operands, OperandMap); 247236769Sobrien 248236769Sobrien OS << "#ifdef GET_INSTRINFO_OPERAND_ENUM\n"; 249236769Sobrien OS << "#undef GET_INSTRINFO_OPERAND_ENUM\n"; 250236769Sobrien OS << "namespace llvm {\n"; 251236769Sobrien OS << "namespace " << Namespace << " {\n"; 252236769Sobrien OS << "namespace " << OpNameNS << " { \n"; 253236769Sobrien OS << "enum {\n"; 254236769Sobrien for (const auto &Op : Operands) 255236769Sobrien OS << " " << Op.first << " = " << Op.second << ",\n"; 256236769Sobrien 257236769Sobrien OS << "OPERAND_LAST"; 258236769Sobrien OS << "\n};\n"; 259236769Sobrien OS << "} // end namespace OpName\n"; 260236769Sobrien OS << "} // end namespace " << Namespace << "\n"; 261236769Sobrien OS << "} // end namespace llvm\n"; 262236769Sobrien OS << "#endif //GET_INSTRINFO_OPERAND_ENUM\n"; 263236769Sobrien 264236769Sobrien OS << "#ifdef GET_INSTRINFO_NAMED_OPS\n"; 265236769Sobrien OS << "#undef GET_INSTRINFO_NAMED_OPS\n"; 266236769Sobrien OS << "namespace llvm {\n"; 267236769Sobrien OS << "namespace " << Namespace << " {\n"; 268236769Sobrien OS << "LLVM_READONLY\n"; 269236769Sobrien OS << "int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {\n"; 270236769Sobrien if (!Operands.empty()) { 271236769Sobrien OS << " static const int16_t OperandMap [][" << Operands.size() 272236769Sobrien << "] = {\n"; 273236769Sobrien for (const auto &Entry : OperandMap) { 274236769Sobrien const std::map<unsigned, unsigned> &OpList = Entry.first; 275236769Sobrien OS << "{"; 276236769Sobrien 277236769Sobrien // Emit a row of the OperandMap table 278236769Sobrien for (unsigned i = 0, e = Operands.size(); i != e; ++i) 279236769Sobrien OS << (OpList.count(i) == 0 ? -1 : (int)OpList.find(i)->second) << ", "; 280236769Sobrien 281236769Sobrien OS << "},\n"; 282236769Sobrien } 283236769Sobrien OS << "};\n"; 284236769Sobrien 285236769Sobrien OS << " switch(Opcode) {\n"; 286236769Sobrien unsigned TableIndex = 0; 287236769Sobrien for (const auto &Entry : OperandMap) { 288236769Sobrien for (const std::string &Name : Entry.second) 289236769Sobrien OS << " case " << Name << ":\n"; 290236769Sobrien 291236769Sobrien OS << " return OperandMap[" << TableIndex++ << "][NamedIdx];\n"; 292236769Sobrien } 293236769Sobrien OS << " default: return -1;\n"; 294236769Sobrien OS << " }\n"; 295236769Sobrien } else { 296236769Sobrien // There are no operands, so no need to emit anything 297236769Sobrien OS << " return -1;\n"; 298236769Sobrien } 299236769Sobrien OS << "}\n"; 300236769Sobrien OS << "} // end namespace " << Namespace << "\n"; 301236769Sobrien OS << "} // end namespace llvm\n"; 302236769Sobrien OS << "#endif //GET_INSTRINFO_NAMED_OPS\n"; 303236769Sobrien 304236769Sobrien} 305236769Sobrien 306236769Sobrien/// Generate an enum for all the operand types for this target, under the 307236769Sobrien/// llvm::TargetNamespace::OpTypes namespace. 308236769Sobrien/// Operand types are all definitions derived of the Operand Target.td class. 309236769Sobrienvoid InstrInfoEmitter::emitOperandTypesEnum(raw_ostream &OS, 310236769Sobrien const CodeGenTarget &Target) { 311236769Sobrien 312236769Sobrien const std::string &Namespace = Target.getInstNamespace(); 313236769Sobrien std::vector<Record *> Operands = Records.getAllDerivedDefinitions("Operand"); 314236769Sobrien 315236769Sobrien OS << "\n#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM\n"; 316292068Ssjg OS << "#undef GET_INSTRINFO_OPERAND_TYPES_ENUM\n"; 317292068Ssjg OS << "namespace llvm {\n"; 318292068Ssjg OS << "namespace " << Namespace << " {\n"; 319292068Ssjg OS << "namespace OpTypes { \n"; 320292068Ssjg OS << "enum OperandType {\n"; 321276305Sngie 322276305Sngie unsigned EnumVal = 0; 323276305Sngie for (const Record *Op : Operands) { 324236769Sobrien if (!Op->isAnonymous()) 325236769Sobrien OS << " " << Op->getName() << " = " << EnumVal << ",\n"; 326236769Sobrien ++EnumVal; 327236769Sobrien } 328236769Sobrien 329236769Sobrien OS << " OPERAND_TYPE_LIST_END" << "\n};\n"; 330236769Sobrien OS << "} // end namespace OpTypes\n"; 331236769Sobrien OS << "} // end namespace " << Namespace << "\n"; 332236769Sobrien OS << "} // end namespace llvm\n"; 333236769Sobrien OS << "#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM\n"; 334236769Sobrien} 335236769Sobrien 336292068Ssjg//===----------------------------------------------------------------------===// 337292068Ssjg// Main Output. 338292068Ssjg//===----------------------------------------------------------------------===// 339292068Ssjg 340236769Sobrien// run - Emit the main instruction description records for the target... 341236769Sobrienvoid InstrInfoEmitter::run(raw_ostream &OS) { 342 emitSourceFileHeader("Target Instruction Enum Values", OS); 343 emitEnums(OS); 344 345 emitSourceFileHeader("Target Instruction Descriptors", OS); 346 347 OS << "\n#ifdef GET_INSTRINFO_MC_DESC\n"; 348 OS << "#undef GET_INSTRINFO_MC_DESC\n"; 349 350 OS << "namespace llvm {\n\n"; 351 352 CodeGenTarget &Target = CDP.getTargetInfo(); 353 const std::string &TargetName = Target.getName(); 354 Record *InstrInfo = Target.getInstructionSet(); 355 356 // Keep track of all of the def lists we have emitted already. 357 std::map<std::vector<Record*>, unsigned> EmittedLists; 358 unsigned ListNumber = 0; 359 360 // Emit all of the instruction's implicit uses and defs. 361 for (const CodeGenInstruction *II : Target.instructions()) { 362 Record *Inst = II->TheDef; 363 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses"); 364 if (!Uses.empty()) { 365 unsigned &IL = EmittedLists[Uses]; 366 if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS); 367 } 368 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs"); 369 if (!Defs.empty()) { 370 unsigned &IL = EmittedLists[Defs]; 371 if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS); 372 } 373 } 374 375 OperandInfoMapTy OperandInfoIDs; 376 377 // Emit all of the operand info records. 378 EmitOperandInfo(OS, OperandInfoIDs); 379 380 // Emit all of the MCInstrDesc records in their ENUM ordering. 381 // 382 OS << "\nextern const MCInstrDesc " << TargetName << "Insts[] = {\n"; 383 const std::vector<const CodeGenInstruction*> &NumberedInstructions = 384 Target.getInstructionsByEnumValue(); 385 386 SequenceToOffsetTable<std::string> InstrNames; 387 unsigned Num = 0; 388 for (const CodeGenInstruction *Inst : NumberedInstructions) { 389 // Keep a list of the instruction names. 390 InstrNames.add(Inst->TheDef->getName()); 391 // Emit the record into the table. 392 emitRecord(*Inst, Num++, InstrInfo, EmittedLists, OperandInfoIDs, OS); 393 } 394 OS << "};\n\n"; 395 396 // Emit the array of instruction names. 397 InstrNames.layout(); 398 OS << "extern const char " << TargetName << "InstrNameData[] = {\n"; 399 InstrNames.emit(OS, printChar); 400 OS << "};\n\n"; 401 402 OS << "extern const unsigned " << TargetName <<"InstrNameIndices[] = {"; 403 Num = 0; 404 for (const CodeGenInstruction *Inst : NumberedInstructions) { 405 // Newline every eight entries. 406 if (Num % 8 == 0) 407 OS << "\n "; 408 OS << InstrNames.get(Inst->TheDef->getName()) << "U, "; 409 ++Num; 410 } 411 412 OS << "\n};\n\n"; 413 414 // MCInstrInfo initialization routine. 415 OS << "static inline void Init" << TargetName 416 << "MCInstrInfo(MCInstrInfo *II) {\n"; 417 OS << " II->InitMCInstrInfo(" << TargetName << "Insts, " 418 << TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, " 419 << NumberedInstructions.size() << ");\n}\n\n"; 420 421 OS << "} // end llvm namespace \n"; 422 423 OS << "#endif // GET_INSTRINFO_MC_DESC\n\n"; 424 425 // Create a TargetInstrInfo subclass to hide the MC layer initialization. 426 OS << "\n#ifdef GET_INSTRINFO_HEADER\n"; 427 OS << "#undef GET_INSTRINFO_HEADER\n"; 428 429 std::string ClassName = TargetName + "GenInstrInfo"; 430 OS << "namespace llvm {\n"; 431 OS << "struct " << ClassName << " : public TargetInstrInfo {\n" 432 << " explicit " << ClassName 433 << "(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1);\n" 434 << " ~" << ClassName << "() override {}\n" 435 << "};\n"; 436 OS << "} // end llvm namespace \n"; 437 438 OS << "#endif // GET_INSTRINFO_HEADER\n\n"; 439 440 OS << "\n#ifdef GET_INSTRINFO_CTOR_DTOR\n"; 441 OS << "#undef GET_INSTRINFO_CTOR_DTOR\n"; 442 443 OS << "namespace llvm {\n"; 444 OS << "extern const MCInstrDesc " << TargetName << "Insts[];\n"; 445 OS << "extern const unsigned " << TargetName << "InstrNameIndices[];\n"; 446 OS << "extern const char " << TargetName << "InstrNameData[];\n"; 447 OS << ClassName << "::" << ClassName 448 << "(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode)\n" 449 << " : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode) {\n" 450 << " InitMCInstrInfo(" << TargetName << "Insts, " << TargetName 451 << "InstrNameIndices, " << TargetName << "InstrNameData, " 452 << NumberedInstructions.size() << ");\n}\n"; 453 OS << "} // end llvm namespace \n"; 454 455 OS << "#endif // GET_INSTRINFO_CTOR_DTOR\n\n"; 456 457 emitOperandNameMappings(OS, Target, NumberedInstructions); 458 459 emitOperandTypesEnum(OS, Target); 460} 461 462void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, 463 Record *InstrInfo, 464 std::map<std::vector<Record*>, unsigned> &EmittedLists, 465 const OperandInfoMapTy &OpInfo, 466 raw_ostream &OS) { 467 int MinOperands = 0; 468 if (!Inst.Operands.empty()) 469 // Each logical operand can be multiple MI operands. 470 MinOperands = Inst.Operands.back().MIOperandNo + 471 Inst.Operands.back().MINumOperands; 472 473 OS << " { "; 474 OS << Num << ",\t" << MinOperands << ",\t" 475 << Inst.Operands.NumDefs << ",\t" 476 << Inst.TheDef->getValueAsInt("Size") << ",\t" 477 << SchedModels.getSchedClassIdx(Inst) << ",\t0"; 478 479 // Emit all of the target independent flags... 480 if (Inst.isPseudo) OS << "|(1ULL<<MCID::Pseudo)"; 481 if (Inst.isReturn) OS << "|(1ULL<<MCID::Return)"; 482 if (Inst.isBranch) OS << "|(1ULL<<MCID::Branch)"; 483 if (Inst.isIndirectBranch) OS << "|(1ULL<<MCID::IndirectBranch)"; 484 if (Inst.isCompare) OS << "|(1ULL<<MCID::Compare)"; 485 if (Inst.isMoveImm) OS << "|(1ULL<<MCID::MoveImm)"; 486 if (Inst.isBitcast) OS << "|(1ULL<<MCID::Bitcast)"; 487 if (Inst.isSelect) OS << "|(1ULL<<MCID::Select)"; 488 if (Inst.isBarrier) OS << "|(1ULL<<MCID::Barrier)"; 489 if (Inst.hasDelaySlot) OS << "|(1ULL<<MCID::DelaySlot)"; 490 if (Inst.isCall) OS << "|(1ULL<<MCID::Call)"; 491 if (Inst.canFoldAsLoad) OS << "|(1ULL<<MCID::FoldableAsLoad)"; 492 if (Inst.mayLoad) OS << "|(1ULL<<MCID::MayLoad)"; 493 if (Inst.mayStore) OS << "|(1ULL<<MCID::MayStore)"; 494 if (Inst.isPredicable) OS << "|(1ULL<<MCID::Predicable)"; 495 if (Inst.isConvertibleToThreeAddress) OS << "|(1ULL<<MCID::ConvertibleTo3Addr)"; 496 if (Inst.isCommutable) OS << "|(1ULL<<MCID::Commutable)"; 497 if (Inst.isTerminator) OS << "|(1ULL<<MCID::Terminator)"; 498 if (Inst.isReMaterializable) OS << "|(1ULL<<MCID::Rematerializable)"; 499 if (Inst.isNotDuplicable) OS << "|(1ULL<<MCID::NotDuplicable)"; 500 if (Inst.Operands.hasOptionalDef) OS << "|(1ULL<<MCID::HasOptionalDef)"; 501 if (Inst.usesCustomInserter) OS << "|(1ULL<<MCID::UsesCustomInserter)"; 502 if (Inst.hasPostISelHook) OS << "|(1ULL<<MCID::HasPostISelHook)"; 503 if (Inst.Operands.isVariadic)OS << "|(1ULL<<MCID::Variadic)"; 504 if (Inst.hasSideEffects) OS << "|(1ULL<<MCID::UnmodeledSideEffects)"; 505 if (Inst.isAsCheapAsAMove) OS << "|(1ULL<<MCID::CheapAsAMove)"; 506 if (Inst.hasExtraSrcRegAllocReq) OS << "|(1ULL<<MCID::ExtraSrcRegAllocReq)"; 507 if (Inst.hasExtraDefRegAllocReq) OS << "|(1ULL<<MCID::ExtraDefRegAllocReq)"; 508 if (Inst.isRegSequence) OS << "|(1ULL<<MCID::RegSequence)"; 509 if (Inst.isExtractSubreg) OS << "|(1ULL<<MCID::ExtractSubreg)"; 510 if (Inst.isInsertSubreg) OS << "|(1ULL<<MCID::InsertSubreg)"; 511 if (Inst.isConvergent) OS << "|(1ULL<<MCID::Convergent)"; 512 513 // Emit all of the target-specific flags... 514 BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags"); 515 if (!TSF) 516 PrintFatalError("no TSFlags?"); 517 uint64_t Value = 0; 518 for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) { 519 if (BitInit *Bit = dyn_cast<BitInit>(TSF->getBit(i))) 520 Value |= uint64_t(Bit->getValue()) << i; 521 else 522 PrintFatalError("Invalid TSFlags bit in " + Inst.TheDef->getName()); 523 } 524 OS << ", 0x"; 525 OS.write_hex(Value); 526 OS << "ULL, "; 527 528 // Emit the implicit uses and defs lists... 529 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses"); 530 if (UseList.empty()) 531 OS << "nullptr, "; 532 else 533 OS << "ImplicitList" << EmittedLists[UseList] << ", "; 534 535 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs"); 536 if (DefList.empty()) 537 OS << "nullptr, "; 538 else 539 OS << "ImplicitList" << EmittedLists[DefList] << ", "; 540 541 // Emit the operand info. 542 std::vector<std::string> OperandInfo = GetOperandInfo(Inst); 543 if (OperandInfo.empty()) 544 OS << "nullptr"; 545 else 546 OS << "OperandInfo" << OpInfo.find(OperandInfo)->second; 547 548 CodeGenTarget &Target = CDP.getTargetInfo(); 549 if (Inst.HasComplexDeprecationPredicate) 550 // Emit a function pointer to the complex predicate method. 551 OS << ", -1 " 552 << ",&get" << Inst.DeprecatedReason << "DeprecationInfo"; 553 else if (!Inst.DeprecatedReason.empty()) 554 // Emit the Subtarget feature. 555 OS << ", " << Target.getInstNamespace() << "::" << Inst.DeprecatedReason 556 << " ,nullptr"; 557 else 558 // Instruction isn't deprecated. 559 OS << ", -1 ,nullptr"; 560 561 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n"; 562} 563 564// emitEnums - Print out enum values for all of the instructions. 565void InstrInfoEmitter::emitEnums(raw_ostream &OS) { 566 567 OS << "\n#ifdef GET_INSTRINFO_ENUM\n"; 568 OS << "#undef GET_INSTRINFO_ENUM\n"; 569 570 OS << "namespace llvm {\n\n"; 571 572 CodeGenTarget Target(Records); 573 574 // We must emit the PHI opcode first... 575 std::string Namespace = Target.getInstNamespace(); 576 577 if (Namespace.empty()) 578 PrintFatalError("No instructions defined!"); 579 580 const std::vector<const CodeGenInstruction*> &NumberedInstructions = 581 Target.getInstructionsByEnumValue(); 582 583 OS << "namespace " << Namespace << " {\n"; 584 OS << " enum {\n"; 585 unsigned Num = 0; 586 for (const CodeGenInstruction *Inst : NumberedInstructions) 587 OS << " " << Inst->TheDef->getName() << "\t= " << Num++ << ",\n"; 588 OS << " INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n"; 589 OS << " };\n\n"; 590 OS << "namespace Sched {\n"; 591 OS << " enum {\n"; 592 Num = 0; 593 for (const auto &Class : SchedModels.explicit_classes()) 594 OS << " " << Class.Name << "\t= " << Num++ << ",\n"; 595 OS << " SCHED_LIST_END = " << SchedModels.numInstrSchedClasses() << "\n"; 596 OS << " };\n"; 597 OS << "} // end Sched namespace\n"; 598 OS << "} // end " << Namespace << " namespace\n"; 599 OS << "} // end llvm namespace \n"; 600 601 OS << "#endif // GET_INSTRINFO_ENUM\n\n"; 602} 603 604namespace llvm { 605 606void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS) { 607 InstrInfoEmitter(RK).run(OS); 608 EmitMapTable(RK, OS); 609} 610 611} // end llvm namespace 612