InstrInfoEmitter.cpp revision 243830
1//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This tablegen backend is responsible for emitting a description of the target 11// instruction set for the code generator. 12// 13//===----------------------------------------------------------------------===// 14 15 16#include "CodeGenDAGPatterns.h" 17#include "CodeGenSchedule.h" 18#include "CodeGenTarget.h" 19#include "TableGenBackends.h" 20#include "SequenceToOffsetTable.h" 21#include "llvm/ADT/StringExtras.h" 22#include "llvm/TableGen/Error.h" 23#include "llvm/TableGen/Record.h" 24#include "llvm/TableGen/TableGenBackend.h" 25#include <algorithm> 26#include <cstdio> 27#include <map> 28#include <vector> 29using namespace llvm; 30 31namespace { 32class InstrInfoEmitter { 33 RecordKeeper &Records; 34 CodeGenDAGPatterns CDP; 35 const CodeGenSchedModels &SchedModels; 36 37public: 38 InstrInfoEmitter(RecordKeeper &R): 39 Records(R), CDP(R), SchedModels(CDP.getTargetInfo().getSchedModels()) {} 40 41 // run - Output the instruction set description. 42 void run(raw_ostream &OS); 43 44private: 45 void emitEnums(raw_ostream &OS); 46 47 typedef std::map<std::vector<std::string>, unsigned> OperandInfoMapTy; 48 void emitRecord(const CodeGenInstruction &Inst, unsigned Num, 49 Record *InstrInfo, 50 std::map<std::vector<Record*>, unsigned> &EL, 51 const OperandInfoMapTy &OpInfo, 52 raw_ostream &OS); 53 54 // Operand information. 55 void EmitOperandInfo(raw_ostream &OS, OperandInfoMapTy &OperandInfoIDs); 56 std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst); 57}; 58} // End anonymous namespace 59 60static void PrintDefList(const std::vector<Record*> &Uses, 61 unsigned Num, raw_ostream &OS) { 62 OS << "static const uint16_t ImplicitList" << Num << "[] = { "; 63 for (unsigned i = 0, e = Uses.size(); i != e; ++i) 64 OS << getQualifiedName(Uses[i]) << ", "; 65 OS << "0 };\n"; 66} 67 68//===----------------------------------------------------------------------===// 69// Operand Info Emission. 70//===----------------------------------------------------------------------===// 71 72std::vector<std::string> 73InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { 74 std::vector<std::string> Result; 75 76 for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) { 77 // Handle aggregate operands and normal operands the same way by expanding 78 // either case into a list of operands for this op. 79 std::vector<CGIOperandList::OperandInfo> OperandList; 80 81 // This might be a multiple operand thing. Targets like X86 have 82 // registers in their multi-operand operands. It may also be an anonymous 83 // operand, which has a single operand, but no declared class for the 84 // operand. 85 DagInit *MIOI = Inst.Operands[i].MIOperandInfo; 86 87 if (!MIOI || MIOI->getNumArgs() == 0) { 88 // Single, anonymous, operand. 89 OperandList.push_back(Inst.Operands[i]); 90 } else { 91 for (unsigned j = 0, e = Inst.Operands[i].MINumOperands; j != e; ++j) { 92 OperandList.push_back(Inst.Operands[i]); 93 94 Record *OpR = cast<DefInit>(MIOI->getArg(j))->getDef(); 95 OperandList.back().Rec = OpR; 96 } 97 } 98 99 for (unsigned j = 0, e = OperandList.size(); j != e; ++j) { 100 Record *OpR = OperandList[j].Rec; 101 std::string Res; 102 103 if (OpR->isSubClassOf("RegisterOperand")) 104 OpR = OpR->getValueAsDef("RegClass"); 105 if (OpR->isSubClassOf("RegisterClass")) 106 Res += getQualifiedName(OpR) + "RegClassID, "; 107 else if (OpR->isSubClassOf("PointerLikeRegClass")) 108 Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", "; 109 else 110 // -1 means the operand does not have a fixed register class. 111 Res += "-1, "; 112 113 // Fill in applicable flags. 114 Res += "0"; 115 116 // Ptr value whose register class is resolved via callback. 117 if (OpR->isSubClassOf("PointerLikeRegClass")) 118 Res += "|(1<<MCOI::LookupPtrRegClass)"; 119 120 // Predicate operands. Check to see if the original unexpanded operand 121 // was of type PredicateOperand. 122 if (Inst.Operands[i].Rec->isSubClassOf("PredicateOperand")) 123 Res += "|(1<<MCOI::Predicate)"; 124 125 // Optional def operands. Check to see if the original unexpanded operand 126 // was of type OptionalDefOperand. 127 if (Inst.Operands[i].Rec->isSubClassOf("OptionalDefOperand")) 128 Res += "|(1<<MCOI::OptionalDef)"; 129 130 // Fill in operand type. 131 Res += ", MCOI::"; 132 assert(!Inst.Operands[i].OperandType.empty() && "Invalid operand type."); 133 Res += Inst.Operands[i].OperandType; 134 135 // Fill in constraint info. 136 Res += ", "; 137 138 const CGIOperandList::ConstraintInfo &Constraint = 139 Inst.Operands[i].Constraints[j]; 140 if (Constraint.isNone()) 141 Res += "0"; 142 else if (Constraint.isEarlyClobber()) 143 Res += "(1 << MCOI::EARLY_CLOBBER)"; 144 else { 145 assert(Constraint.isTied()); 146 Res += "((" + utostr(Constraint.getTiedOperand()) + 147 " << 16) | (1 << MCOI::TIED_TO))"; 148 } 149 150 Result.push_back(Res); 151 } 152 } 153 154 return Result; 155} 156 157void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS, 158 OperandInfoMapTy &OperandInfoIDs) { 159 // ID #0 is for no operand info. 160 unsigned OperandListNum = 0; 161 OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum; 162 163 OS << "\n"; 164 const CodeGenTarget &Target = CDP.getTargetInfo(); 165 for (CodeGenTarget::inst_iterator II = Target.inst_begin(), 166 E = Target.inst_end(); II != E; ++II) { 167 std::vector<std::string> OperandInfo = GetOperandInfo(**II); 168 unsigned &N = OperandInfoIDs[OperandInfo]; 169 if (N != 0) continue; 170 171 N = ++OperandListNum; 172 OS << "static const MCOperandInfo OperandInfo" << N << "[] = { "; 173 for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) 174 OS << "{ " << OperandInfo[i] << " }, "; 175 OS << "};\n"; 176 } 177} 178 179//===----------------------------------------------------------------------===// 180// Main Output. 181//===----------------------------------------------------------------------===// 182 183// run - Emit the main instruction description records for the target... 184void InstrInfoEmitter::run(raw_ostream &OS) { 185 emitSourceFileHeader("Target Instruction Enum Values", OS); 186 emitEnums(OS); 187 188 emitSourceFileHeader("Target Instruction Descriptors", OS); 189 190 OS << "\n#ifdef GET_INSTRINFO_MC_DESC\n"; 191 OS << "#undef GET_INSTRINFO_MC_DESC\n"; 192 193 OS << "namespace llvm {\n\n"; 194 195 CodeGenTarget &Target = CDP.getTargetInfo(); 196 const std::string &TargetName = Target.getName(); 197 Record *InstrInfo = Target.getInstructionSet(); 198 199 // Keep track of all of the def lists we have emitted already. 200 std::map<std::vector<Record*>, unsigned> EmittedLists; 201 unsigned ListNumber = 0; 202 203 // Emit all of the instruction's implicit uses and defs. 204 for (CodeGenTarget::inst_iterator II = Target.inst_begin(), 205 E = Target.inst_end(); II != E; ++II) { 206 Record *Inst = (*II)->TheDef; 207 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses"); 208 if (!Uses.empty()) { 209 unsigned &IL = EmittedLists[Uses]; 210 if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS); 211 } 212 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs"); 213 if (!Defs.empty()) { 214 unsigned &IL = EmittedLists[Defs]; 215 if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS); 216 } 217 } 218 219 OperandInfoMapTy OperandInfoIDs; 220 221 // Emit all of the operand info records. 222 EmitOperandInfo(OS, OperandInfoIDs); 223 224 // Emit all of the MCInstrDesc records in their ENUM ordering. 225 // 226 OS << "\nextern const MCInstrDesc " << TargetName << "Insts[] = {\n"; 227 const std::vector<const CodeGenInstruction*> &NumberedInstructions = 228 Target.getInstructionsByEnumValue(); 229 230 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) 231 emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists, 232 OperandInfoIDs, OS); 233 OS << "};\n\n"; 234 235 // Build an array of instruction names 236 SequenceToOffsetTable<std::string> InstrNames; 237 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { 238 const CodeGenInstruction *Instr = NumberedInstructions[i]; 239 InstrNames.add(Instr->TheDef->getName()); 240 } 241 242 InstrNames.layout(); 243 OS << "extern const char " << TargetName << "InstrNameData[] = {\n"; 244 InstrNames.emit(OS, printChar); 245 OS << "};\n\n"; 246 247 OS << "extern const unsigned " << TargetName <<"InstrNameIndices[] = {"; 248 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { 249 if (i % 8 == 0) 250 OS << "\n "; 251 const CodeGenInstruction *Instr = NumberedInstructions[i]; 252 OS << InstrNames.get(Instr->TheDef->getName()) << "U, "; 253 } 254 255 OS << "\n};\n\n"; 256 257 // MCInstrInfo initialization routine. 258 OS << "static inline void Init" << TargetName 259 << "MCInstrInfo(MCInstrInfo *II) {\n"; 260 OS << " II->InitMCInstrInfo(" << TargetName << "Insts, " 261 << TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, " 262 << NumberedInstructions.size() << ");\n}\n\n"; 263 264 OS << "} // End llvm namespace \n"; 265 266 OS << "#endif // GET_INSTRINFO_MC_DESC\n\n"; 267 268 // Create a TargetInstrInfo subclass to hide the MC layer initialization. 269 OS << "\n#ifdef GET_INSTRINFO_HEADER\n"; 270 OS << "#undef GET_INSTRINFO_HEADER\n"; 271 272 std::string ClassName = TargetName + "GenInstrInfo"; 273 OS << "namespace llvm {\n"; 274 OS << "struct " << ClassName << " : public TargetInstrInfoImpl {\n" 275 << " explicit " << ClassName << "(int SO = -1, int DO = -1);\n" 276 << "};\n"; 277 OS << "} // End llvm namespace \n"; 278 279 OS << "#endif // GET_INSTRINFO_HEADER\n\n"; 280 281 OS << "\n#ifdef GET_INSTRINFO_CTOR\n"; 282 OS << "#undef GET_INSTRINFO_CTOR\n"; 283 284 OS << "namespace llvm {\n"; 285 OS << "extern const MCInstrDesc " << TargetName << "Insts[];\n"; 286 OS << "extern const unsigned " << TargetName << "InstrNameIndices[];\n"; 287 OS << "extern const char " << TargetName << "InstrNameData[];\n"; 288 OS << ClassName << "::" << ClassName << "(int SO, int DO)\n" 289 << " : TargetInstrInfoImpl(SO, DO) {\n" 290 << " InitMCInstrInfo(" << TargetName << "Insts, " 291 << TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, " 292 << NumberedInstructions.size() << ");\n}\n"; 293 OS << "} // End llvm namespace \n"; 294 295 OS << "#endif // GET_INSTRINFO_CTOR\n\n"; 296} 297 298void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, 299 Record *InstrInfo, 300 std::map<std::vector<Record*>, unsigned> &EmittedLists, 301 const OperandInfoMapTy &OpInfo, 302 raw_ostream &OS) { 303 int MinOperands = 0; 304 if (!Inst.Operands.empty()) 305 // Each logical operand can be multiple MI operands. 306 MinOperands = Inst.Operands.back().MIOperandNo + 307 Inst.Operands.back().MINumOperands; 308 309 OS << " { "; 310 OS << Num << ",\t" << MinOperands << ",\t" 311 << Inst.Operands.NumDefs << ",\t" 312 << SchedModels.getSchedClassIdx(Inst) << ",\t" 313 << Inst.TheDef->getValueAsInt("Size") << ",\t0"; 314 315 // Emit all of the target indepedent flags... 316 if (Inst.isPseudo) OS << "|(1<<MCID::Pseudo)"; 317 if (Inst.isReturn) OS << "|(1<<MCID::Return)"; 318 if (Inst.isBranch) OS << "|(1<<MCID::Branch)"; 319 if (Inst.isIndirectBranch) OS << "|(1<<MCID::IndirectBranch)"; 320 if (Inst.isCompare) OS << "|(1<<MCID::Compare)"; 321 if (Inst.isMoveImm) OS << "|(1<<MCID::MoveImm)"; 322 if (Inst.isBitcast) OS << "|(1<<MCID::Bitcast)"; 323 if (Inst.isSelect) OS << "|(1<<MCID::Select)"; 324 if (Inst.isBarrier) OS << "|(1<<MCID::Barrier)"; 325 if (Inst.hasDelaySlot) OS << "|(1<<MCID::DelaySlot)"; 326 if (Inst.isCall) OS << "|(1<<MCID::Call)"; 327 if (Inst.canFoldAsLoad) OS << "|(1<<MCID::FoldableAsLoad)"; 328 if (Inst.mayLoad) OS << "|(1<<MCID::MayLoad)"; 329 if (Inst.mayStore) OS << "|(1<<MCID::MayStore)"; 330 if (Inst.isPredicable) OS << "|(1<<MCID::Predicable)"; 331 if (Inst.isConvertibleToThreeAddress) OS << "|(1<<MCID::ConvertibleTo3Addr)"; 332 if (Inst.isCommutable) OS << "|(1<<MCID::Commutable)"; 333 if (Inst.isTerminator) OS << "|(1<<MCID::Terminator)"; 334 if (Inst.isReMaterializable) OS << "|(1<<MCID::Rematerializable)"; 335 if (Inst.isNotDuplicable) OS << "|(1<<MCID::NotDuplicable)"; 336 if (Inst.Operands.hasOptionalDef) OS << "|(1<<MCID::HasOptionalDef)"; 337 if (Inst.usesCustomInserter) OS << "|(1<<MCID::UsesCustomInserter)"; 338 if (Inst.hasPostISelHook) OS << "|(1<<MCID::HasPostISelHook)"; 339 if (Inst.Operands.isVariadic)OS << "|(1<<MCID::Variadic)"; 340 if (Inst.hasSideEffects) OS << "|(1<<MCID::UnmodeledSideEffects)"; 341 if (Inst.isAsCheapAsAMove) OS << "|(1<<MCID::CheapAsAMove)"; 342 if (Inst.hasExtraSrcRegAllocReq) OS << "|(1<<MCID::ExtraSrcRegAllocReq)"; 343 if (Inst.hasExtraDefRegAllocReq) OS << "|(1<<MCID::ExtraDefRegAllocReq)"; 344 345 // Emit all of the target-specific flags... 346 BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags"); 347 if (!TSF) 348 PrintFatalError("no TSFlags?"); 349 uint64_t Value = 0; 350 for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) { 351 if (BitInit *Bit = dyn_cast<BitInit>(TSF->getBit(i))) 352 Value |= uint64_t(Bit->getValue()) << i; 353 else 354 PrintFatalError("Invalid TSFlags bit in " + Inst.TheDef->getName()); 355 } 356 OS << ", 0x"; 357 OS.write_hex(Value); 358 OS << "ULL, "; 359 360 // Emit the implicit uses and defs lists... 361 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses"); 362 if (UseList.empty()) 363 OS << "NULL, "; 364 else 365 OS << "ImplicitList" << EmittedLists[UseList] << ", "; 366 367 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs"); 368 if (DefList.empty()) 369 OS << "NULL, "; 370 else 371 OS << "ImplicitList" << EmittedLists[DefList] << ", "; 372 373 // Emit the operand info. 374 std::vector<std::string> OperandInfo = GetOperandInfo(Inst); 375 if (OperandInfo.empty()) 376 OS << "0"; 377 else 378 OS << "OperandInfo" << OpInfo.find(OperandInfo)->second; 379 380 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n"; 381} 382 383// emitEnums - Print out enum values for all of the instructions. 384void InstrInfoEmitter::emitEnums(raw_ostream &OS) { 385 386 OS << "\n#ifdef GET_INSTRINFO_ENUM\n"; 387 OS << "#undef GET_INSTRINFO_ENUM\n"; 388 389 OS << "namespace llvm {\n\n"; 390 391 CodeGenTarget Target(Records); 392 393 // We must emit the PHI opcode first... 394 std::string Namespace = Target.getInstNamespace(); 395 396 if (Namespace.empty()) { 397 fprintf(stderr, "No instructions defined!\n"); 398 exit(1); 399 } 400 401 const std::vector<const CodeGenInstruction*> &NumberedInstructions = 402 Target.getInstructionsByEnumValue(); 403 404 OS << "namespace " << Namespace << " {\n"; 405 OS << " enum {\n"; 406 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { 407 OS << " " << NumberedInstructions[i]->TheDef->getName() 408 << "\t= " << i << ",\n"; 409 } 410 OS << " INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n"; 411 OS << " };\n}\n"; 412 OS << "} // End llvm namespace \n"; 413 414 OS << "#endif // GET_INSTRINFO_ENUM\n\n"; 415} 416 417namespace llvm { 418 419void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS) { 420 InstrInfoEmitter(RK).run(OS); 421 EmitMapTable(RK, OS); 422} 423 424} // End llvm namespace 425