CodeEmitterGen.cpp revision 207618 
1//===- CodeEmitterGen.cpp - Code Emitter Generator ------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// CodeEmitterGen uses the descriptions of instructions and their fields to
11// construct an automated code emitter: a function that, given a MachineInstr,
12// returns the (currently, 32-bit unsigned) value of the instruction.
13//
14//===----------------------------------------------------------------------===//
15
16#include "CodeEmitterGen.h"
17#include "CodeGenTarget.h"
18#include "Record.h"
19#include "llvm/ADT/StringExtras.h"
20#include "llvm/Support/Debug.h"
21using namespace llvm;
22
23void CodeEmitterGen::reverseBits(std::vector<Record*> &Insts) {
24  for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end();
25       I != E; ++I) {
26    Record *R = *I;
27    if (R->getName() == "PHI" ||
28        R->getName() == "INLINEASM" ||
29        R->getName() == "DBG_LABEL" ||
30        R->getName() == "EH_LABEL" ||
31        R->getName() == "GC_LABEL" ||
32        R->getName() == "KILL" ||
33        R->getName() == "EXTRACT_SUBREG" ||
34        R->getName() == "INSERT_SUBREG" ||
35        R->getName() == "IMPLICIT_DEF" ||
36        R->getName() == "SUBREG_TO_REG" ||
37        R->getName() == "COPY_TO_REGCLASS" ||
38        R->getName() == "DBG_VALUE" ||
39        R->getName() == "REG_SEQUENCE") continue;
40
41    BitsInit *BI = R->getValueAsBitsInit("Inst");
42
43    unsigned numBits = BI->getNumBits();
44    BitsInit *NewBI = new BitsInit(numBits);
45    for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) {
46      unsigned bitSwapIdx = numBits - bit - 1;
47      Init *OrigBit = BI->getBit(bit);
48      Init *BitSwap = BI->getBit(bitSwapIdx);
49      NewBI->setBit(bit, BitSwap);
50      NewBI->setBit(bitSwapIdx, OrigBit);
51    }
52    if (numBits % 2) {
53      unsigned middle = (numBits + 1) / 2;
54      NewBI->setBit(middle, BI->getBit(middle));
55    }
56
57    // Update the bits in reversed order so that emitInstrOpBits will get the
58    // correct endianness.
59    R->getValue("Inst")->setValue(NewBI);
60  }
61}
62
63
64// If the VarBitInit at position 'bit' matches the specified variable then
65// return the variable bit position.  Otherwise return -1.
66int CodeEmitterGen::getVariableBit(const std::string &VarName,
67            BitsInit *BI, int bit) {
68  if (VarBitInit *VBI = dynamic_cast<VarBitInit*>(BI->getBit(bit))) {
69    TypedInit *TI = VBI->getVariable();
70
71    if (VarInit *VI = dynamic_cast<VarInit*>(TI)) {
72      if (VI->getName() == VarName) return VBI->getBitNum();
73    }
74  }
75
76  return -1;
77}
78
79
80void CodeEmitterGen::run(raw_ostream &o) {
81  CodeGenTarget Target;
82  std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
83
84  // For little-endian instruction bit encodings, reverse the bit order
85  if (Target.isLittleEndianEncoding()) reverseBits(Insts);
86
87  EmitSourceFileHeader("Machine Code Emitter", o);
88  std::string Namespace = Insts[0]->getValueAsString("Namespace") + "::";
89
90  const std::vector<const CodeGenInstruction*> &NumberedInstructions =
91    Target.getInstructionsByEnumValue();
92
93  // Emit function declaration
94  o << "unsigned " << Target.getName() << "CodeEmitter::"
95    << "getBinaryCodeForInstr(const MachineInstr &MI) {\n";
96
97  // Emit instruction base values
98  o << "  static const unsigned InstBits[] = {\n";
99  for (std::vector<const CodeGenInstruction*>::const_iterator
100          IN = NumberedInstructions.begin(),
101          EN = NumberedInstructions.end();
102       IN != EN; ++IN) {
103    const CodeGenInstruction *CGI = *IN;
104    Record *R = CGI->TheDef;
105
106    if (R->getName() == "PHI" ||
107        R->getName() == "INLINEASM" ||
108        R->getName() == "DBG_LABEL" ||
109        R->getName() == "EH_LABEL" ||
110        R->getName() == "GC_LABEL" ||
111        R->getName() == "KILL" ||
112        R->getName() == "EXTRACT_SUBREG" ||
113        R->getName() == "INSERT_SUBREG" ||
114        R->getName() == "IMPLICIT_DEF" ||
115        R->getName() == "SUBREG_TO_REG" ||
116        R->getName() == "COPY_TO_REGCLASS" ||
117        R->getName() == "DBG_VALUE" ||
118        R->getName() == "REG_SEQUENCE") {
119      o << "    0U,\n";
120      continue;
121    }
122
123    BitsInit *BI = R->getValueAsBitsInit("Inst");
124
125    // Start by filling in fixed values...
126    unsigned Value = 0;
127    for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) {
128      if (BitInit *B = dynamic_cast<BitInit*>(BI->getBit(e-i-1))) {
129        Value |= B->getValue() << (e-i-1);
130      }
131    }
132    o << "    " << Value << "U," << '\t' << "// " << R->getName() << "\n";
133  }
134  o << "    0U\n  };\n";
135
136  // Map to accumulate all the cases.
137  std::map<std::string, std::vector<std::string> > CaseMap;
138
139  // Construct all cases statement for each opcode
140  for (std::vector<Record*>::iterator IC = Insts.begin(), EC = Insts.end();
141        IC != EC; ++IC) {
142    Record *R = *IC;
143    const std::string &InstName = R->getName();
144    std::string Case("");
145
146    if (InstName == "PHI" ||
147        InstName == "INLINEASM" ||
148        InstName == "DBG_LABEL"||
149        InstName == "EH_LABEL"||
150        InstName == "GC_LABEL"||
151        InstName == "KILL"||
152        InstName == "EXTRACT_SUBREG" ||
153        InstName == "INSERT_SUBREG" ||
154        InstName == "IMPLICIT_DEF" ||
155        InstName == "SUBREG_TO_REG" ||
156        InstName == "COPY_TO_REGCLASS" ||
157        InstName == "DBG_VALUE" ||
158        InstName == "REG_SEQUENCE") continue;
159
160    BitsInit *BI = R->getValueAsBitsInit("Inst");
161    const std::vector<RecordVal> &Vals = R->getValues();
162    CodeGenInstruction &CGI = Target.getInstruction(R);
163
164    // Loop over all of the fields in the instruction, determining which are the
165    // operands to the instruction.
166    unsigned op = 0;
167    for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
168      if (!Vals[i].getPrefix() && !Vals[i].getValue()->isComplete()) {
169        // Is the operand continuous? If so, we can just mask and OR it in
170        // instead of doing it bit-by-bit, saving a lot in runtime cost.
171        const std::string &VarName = Vals[i].getName();
172        bool gotOp = false;
173
174        for (int bit = BI->getNumBits()-1; bit >= 0; ) {
175          int varBit = getVariableBit(VarName, BI, bit);
176
177          if (varBit == -1) {
178            --bit;
179          } else {
180            int beginInstBit = bit;
181            int beginVarBit = varBit;
182            int N = 1;
183
184            for (--bit; bit >= 0;) {
185              varBit = getVariableBit(VarName, BI, bit);
186              if (varBit == -1 || varBit != (beginVarBit - N)) break;
187              ++N;
188              --bit;
189            }
190
191            if (!gotOp) {
192              /// If this operand is not supposed to be emitted by the generated
193              /// emitter, skip it.
194              while (CGI.isFlatOperandNotEmitted(op))
195                ++op;
196
197              Case += "      // op: " + VarName + "\n"
198                   +  "      op = getMachineOpValue(MI, MI.getOperand("
199                   +  utostr(op++) + "));\n";
200              gotOp = true;
201            }
202
203            unsigned opMask = ~0U >> (32-N);
204            int opShift = beginVarBit - N + 1;
205            opMask <<= opShift;
206            opShift = beginInstBit - beginVarBit;
207
208            if (opShift > 0) {
209              Case += "      Value |= (op & " + utostr(opMask) + "U) << "
210                   +  itostr(opShift) + ";\n";
211            } else if (opShift < 0) {
212              Case += "      Value |= (op & " + utostr(opMask) + "U) >> "
213                   +  itostr(-opShift) + ";\n";
214            } else {
215              Case += "      Value |= op & " + utostr(opMask) + "U;\n";
216            }
217          }
218        }
219      }
220    }
221
222    std::vector<std::string> &InstList = CaseMap[Case];
223    InstList.push_back(InstName);
224  }
225
226
227  // Emit initial function code
228  o << "  const unsigned opcode = MI.getOpcode();\n"
229    << "  unsigned Value = InstBits[opcode];\n"
230    << "  unsigned op = 0;\n"
231    << "  op = op;  // suppress warning\n"
232    << "  switch (opcode) {\n";
233
234  // Emit each case statement
235  std::map<std::string, std::vector<std::string> >::iterator IE, EE;
236  for (IE = CaseMap.begin(), EE = CaseMap.end(); IE != EE; ++IE) {
237    const std::string &Case = IE->first;
238    std::vector<std::string> &InstList = IE->second;
239
240    for (int i = 0, N = InstList.size(); i < N; i++) {
241      if (i) o << "\n";
242      o << "    case " << Namespace << InstList[i]  << ":";
243    }
244    o << " {\n";
245    o << Case;
246    o << "      break;\n"
247      << "    }\n";
248  }
249
250  // Default case: unhandled opcode
251  o << "  default:\n"
252    << "    std::string msg;\n"
253    << "    raw_string_ostream Msg(msg);\n"
254    << "    Msg << \"Not supported instr: \" << MI;\n"
255    << "    report_fatal_error(Msg.str());\n"
256    << "  }\n"
257    << "  return Value;\n"
258    << "}\n\n";
259}
260