1287514Sdim//===-- RegisterContext_mips.h --------------------------------*- C++ -*-===// 2287514Sdim// 3287514Sdim// The LLVM Compiler Infrastructure 4287514Sdim// 5287514Sdim// This file is distributed under the University of Illinois Open Source 6287514Sdim// License. See LICENSE.TXT for details. 7287514Sdim// 8287514Sdim//===----------------------------------------------------------------------===// 9287514Sdim 10287514Sdim#ifndef liblldb_RegisterContext_mips64_H_ 11287514Sdim#define liblldb_RegisterContext_mips64_H_ 12287514Sdim 13287514Sdim// eh_frame and DWARF Register numbers (eRegisterKindEHFrame & eRegisterKindDWARF) 14287514Sdim 15287514Sdimenum 16287514Sdim{ 17287514Sdim // GP Registers 18296417Sdim dwarf_zero_mips = 0, 19296417Sdim dwarf_r1_mips, 20296417Sdim dwarf_r2_mips, 21296417Sdim dwarf_r3_mips, 22296417Sdim dwarf_r4_mips, 23296417Sdim dwarf_r5_mips, 24296417Sdim dwarf_r6_mips, 25296417Sdim dwarf_r7_mips, 26296417Sdim dwarf_r8_mips, 27296417Sdim dwarf_r9_mips, 28296417Sdim dwarf_r10_mips, 29296417Sdim dwarf_r11_mips, 30296417Sdim dwarf_r12_mips, 31296417Sdim dwarf_r13_mips, 32296417Sdim dwarf_r14_mips, 33296417Sdim dwarf_r15_mips, 34296417Sdim dwarf_r16_mips, 35296417Sdim dwarf_r17_mips, 36296417Sdim dwarf_r18_mips, 37296417Sdim dwarf_r19_mips, 38296417Sdim dwarf_r20_mips, 39296417Sdim dwarf_r21_mips, 40296417Sdim dwarf_r22_mips, 41296417Sdim dwarf_r23_mips, 42296417Sdim dwarf_r24_mips, 43296417Sdim dwarf_r25_mips, 44296417Sdim dwarf_r26_mips, 45296417Sdim dwarf_r27_mips, 46296417Sdim dwarf_gp_mips, 47296417Sdim dwarf_sp_mips, 48296417Sdim dwarf_r30_mips, 49296417Sdim dwarf_ra_mips, 50296417Sdim dwarf_sr_mips, 51296417Sdim dwarf_lo_mips, 52296417Sdim dwarf_hi_mips, 53296417Sdim dwarf_bad_mips, 54296417Sdim dwarf_cause_mips, 55296417Sdim dwarf_pc_mips, 56296417Sdim dwarf_f0_mips, 57296417Sdim dwarf_f1_mips, 58296417Sdim dwarf_f2_mips, 59296417Sdim dwarf_f3_mips, 60296417Sdim dwarf_f4_mips, 61296417Sdim dwarf_f5_mips, 62296417Sdim dwarf_f6_mips, 63296417Sdim dwarf_f7_mips, 64296417Sdim dwarf_f8_mips, 65296417Sdim dwarf_f9_mips, 66296417Sdim dwarf_f10_mips, 67296417Sdim dwarf_f11_mips, 68296417Sdim dwarf_f12_mips, 69296417Sdim dwarf_f13_mips, 70296417Sdim dwarf_f14_mips, 71296417Sdim dwarf_f15_mips, 72296417Sdim dwarf_f16_mips, 73296417Sdim dwarf_f17_mips, 74296417Sdim dwarf_f18_mips, 75296417Sdim dwarf_f19_mips, 76296417Sdim dwarf_f20_mips, 77296417Sdim dwarf_f21_mips, 78296417Sdim dwarf_f22_mips, 79296417Sdim dwarf_f23_mips, 80296417Sdim dwarf_f24_mips, 81296417Sdim dwarf_f25_mips, 82296417Sdim dwarf_f26_mips, 83296417Sdim dwarf_f27_mips, 84296417Sdim dwarf_f28_mips, 85296417Sdim dwarf_f29_mips, 86296417Sdim dwarf_f30_mips, 87296417Sdim dwarf_f31_mips, 88296417Sdim dwarf_fcsr_mips, 89296417Sdim dwarf_fir_mips, 90296417Sdim dwarf_w0_mips, 91296417Sdim dwarf_w1_mips, 92296417Sdim dwarf_w2_mips, 93296417Sdim dwarf_w3_mips, 94296417Sdim dwarf_w4_mips, 95296417Sdim dwarf_w5_mips, 96296417Sdim dwarf_w6_mips, 97296417Sdim dwarf_w7_mips, 98296417Sdim dwarf_w8_mips, 99296417Sdim dwarf_w9_mips, 100296417Sdim dwarf_w10_mips, 101296417Sdim dwarf_w11_mips, 102296417Sdim dwarf_w12_mips, 103296417Sdim dwarf_w13_mips, 104296417Sdim dwarf_w14_mips, 105296417Sdim dwarf_w15_mips, 106296417Sdim dwarf_w16_mips, 107296417Sdim dwarf_w17_mips, 108296417Sdim dwarf_w18_mips, 109296417Sdim dwarf_w19_mips, 110296417Sdim dwarf_w20_mips, 111296417Sdim dwarf_w21_mips, 112296417Sdim dwarf_w22_mips, 113296417Sdim dwarf_w23_mips, 114296417Sdim dwarf_w24_mips, 115296417Sdim dwarf_w25_mips, 116296417Sdim dwarf_w26_mips, 117296417Sdim dwarf_w27_mips, 118296417Sdim dwarf_w28_mips, 119296417Sdim dwarf_w29_mips, 120296417Sdim dwarf_w30_mips, 121296417Sdim dwarf_w31_mips, 122296417Sdim dwarf_mcsr_mips, 123296417Sdim dwarf_mir_mips, 124296417Sdim dwarf_config5_mips, 125296417Sdim dwarf_ic_mips, 126296417Sdim dwarf_dummy_mips 127287514Sdim}; 128287514Sdim 129287514Sdimenum 130287514Sdim{ 131296417Sdim dwarf_zero_mips64 = 0, 132296417Sdim dwarf_r1_mips64, 133296417Sdim dwarf_r2_mips64, 134296417Sdim dwarf_r3_mips64, 135296417Sdim dwarf_r4_mips64, 136296417Sdim dwarf_r5_mips64, 137296417Sdim dwarf_r6_mips64, 138296417Sdim dwarf_r7_mips64, 139296417Sdim dwarf_r8_mips64, 140296417Sdim dwarf_r9_mips64, 141296417Sdim dwarf_r10_mips64, 142296417Sdim dwarf_r11_mips64, 143296417Sdim dwarf_r12_mips64, 144296417Sdim dwarf_r13_mips64, 145296417Sdim dwarf_r14_mips64, 146296417Sdim dwarf_r15_mips64, 147296417Sdim dwarf_r16_mips64, 148296417Sdim dwarf_r17_mips64, 149296417Sdim dwarf_r18_mips64, 150296417Sdim dwarf_r19_mips64, 151296417Sdim dwarf_r20_mips64, 152296417Sdim dwarf_r21_mips64, 153296417Sdim dwarf_r22_mips64, 154296417Sdim dwarf_r23_mips64, 155296417Sdim dwarf_r24_mips64, 156296417Sdim dwarf_r25_mips64, 157296417Sdim dwarf_r26_mips64, 158296417Sdim dwarf_r27_mips64, 159296417Sdim dwarf_gp_mips64, 160296417Sdim dwarf_sp_mips64, 161296417Sdim dwarf_r30_mips64, 162296417Sdim dwarf_ra_mips64, 163296417Sdim dwarf_sr_mips64, 164296417Sdim dwarf_lo_mips64, 165296417Sdim dwarf_hi_mips64, 166296417Sdim dwarf_bad_mips64, 167296417Sdim dwarf_cause_mips64, 168296417Sdim dwarf_pc_mips64, 169296417Sdim dwarf_f0_mips64, 170296417Sdim dwarf_f1_mips64, 171296417Sdim dwarf_f2_mips64, 172296417Sdim dwarf_f3_mips64, 173296417Sdim dwarf_f4_mips64, 174296417Sdim dwarf_f5_mips64, 175296417Sdim dwarf_f6_mips64, 176296417Sdim dwarf_f7_mips64, 177296417Sdim dwarf_f8_mips64, 178296417Sdim dwarf_f9_mips64, 179296417Sdim dwarf_f10_mips64, 180296417Sdim dwarf_f11_mips64, 181296417Sdim dwarf_f12_mips64, 182296417Sdim dwarf_f13_mips64, 183296417Sdim dwarf_f14_mips64, 184296417Sdim dwarf_f15_mips64, 185296417Sdim dwarf_f16_mips64, 186296417Sdim dwarf_f17_mips64, 187296417Sdim dwarf_f18_mips64, 188296417Sdim dwarf_f19_mips64, 189296417Sdim dwarf_f20_mips64, 190296417Sdim dwarf_f21_mips64, 191296417Sdim dwarf_f22_mips64, 192296417Sdim dwarf_f23_mips64, 193296417Sdim dwarf_f24_mips64, 194296417Sdim dwarf_f25_mips64, 195296417Sdim dwarf_f26_mips64, 196296417Sdim dwarf_f27_mips64, 197296417Sdim dwarf_f28_mips64, 198296417Sdim dwarf_f29_mips64, 199296417Sdim dwarf_f30_mips64, 200296417Sdim dwarf_f31_mips64, 201296417Sdim dwarf_fcsr_mips64, 202296417Sdim dwarf_fir_mips64, 203296417Sdim dwarf_ic_mips64, 204296417Sdim dwarf_dummy_mips64, 205296417Sdim dwarf_w0_mips64, 206296417Sdim dwarf_w1_mips64, 207296417Sdim dwarf_w2_mips64, 208296417Sdim dwarf_w3_mips64, 209296417Sdim dwarf_w4_mips64, 210296417Sdim dwarf_w5_mips64, 211296417Sdim dwarf_w6_mips64, 212296417Sdim dwarf_w7_mips64, 213296417Sdim dwarf_w8_mips64, 214296417Sdim dwarf_w9_mips64, 215296417Sdim dwarf_w10_mips64, 216296417Sdim dwarf_w11_mips64, 217296417Sdim dwarf_w12_mips64, 218296417Sdim dwarf_w13_mips64, 219296417Sdim dwarf_w14_mips64, 220296417Sdim dwarf_w15_mips64, 221296417Sdim dwarf_w16_mips64, 222296417Sdim dwarf_w17_mips64, 223296417Sdim dwarf_w18_mips64, 224296417Sdim dwarf_w19_mips64, 225296417Sdim dwarf_w20_mips64, 226296417Sdim dwarf_w21_mips64, 227296417Sdim dwarf_w22_mips64, 228296417Sdim dwarf_w23_mips64, 229296417Sdim dwarf_w24_mips64, 230296417Sdim dwarf_w25_mips64, 231296417Sdim dwarf_w26_mips64, 232296417Sdim dwarf_w27_mips64, 233296417Sdim dwarf_w28_mips64, 234296417Sdim dwarf_w29_mips64, 235296417Sdim dwarf_w30_mips64, 236296417Sdim dwarf_w31_mips64, 237296417Sdim dwarf_mcsr_mips64, 238296417Sdim dwarf_mir_mips64, 239296417Sdim dwarf_config5_mips64, 240287514Sdim}; 241287514Sdim 242287514Sdimstruct IOVEC_mips 243287514Sdim{ 244287514Sdim void *iov_base; 245287514Sdim size_t iov_len; 246287514Sdim}; 247287514Sdim 248287514Sdim// GP registers 249287514Sdimstruct GPR_linux_mips 250287514Sdim{ 251287514Sdim uint64_t zero; 252287514Sdim uint64_t r1; 253287514Sdim uint64_t r2; 254287514Sdim uint64_t r3; 255287514Sdim uint64_t r4; 256287514Sdim uint64_t r5; 257287514Sdim uint64_t r6; 258287514Sdim uint64_t r7; 259287514Sdim uint64_t r8; 260287514Sdim uint64_t r9; 261287514Sdim uint64_t r10; 262287514Sdim uint64_t r11; 263287514Sdim uint64_t r12; 264287514Sdim uint64_t r13; 265287514Sdim uint64_t r14; 266287514Sdim uint64_t r15; 267287514Sdim uint64_t r16; 268287514Sdim uint64_t r17; 269287514Sdim uint64_t r18; 270287514Sdim uint64_t r19; 271287514Sdim uint64_t r20; 272287514Sdim uint64_t r21; 273287514Sdim uint64_t r22; 274287514Sdim uint64_t r23; 275287514Sdim uint64_t r24; 276287514Sdim uint64_t r25; 277287514Sdim uint64_t r26; 278287514Sdim uint64_t r27; 279287514Sdim uint64_t gp; 280287514Sdim uint64_t sp; 281287514Sdim uint64_t r30; 282287514Sdim uint64_t ra; 283287514Sdim uint64_t mullo; 284287514Sdim uint64_t mulhi; 285287514Sdim uint64_t pc; 286287514Sdim uint64_t badvaddr; 287287514Sdim uint64_t sr; 288287514Sdim uint64_t cause; 289287514Sdim uint64_t config5; 290287514Sdim}; 291287514Sdim 292287514Sdimstruct FPR_linux_mips 293287514Sdim{ 294287514Sdim uint64_t f0; 295287514Sdim uint64_t f1; 296287514Sdim uint64_t f2; 297287514Sdim uint64_t f3; 298287514Sdim uint64_t f4; 299287514Sdim uint64_t f5; 300287514Sdim uint64_t f6; 301287514Sdim uint64_t f7; 302287514Sdim uint64_t f8; 303287514Sdim uint64_t f9; 304287514Sdim uint64_t f10; 305287514Sdim uint64_t f11; 306287514Sdim uint64_t f12; 307287514Sdim uint64_t f13; 308287514Sdim uint64_t f14; 309287514Sdim uint64_t f15; 310287514Sdim uint64_t f16; 311287514Sdim uint64_t f17; 312287514Sdim uint64_t f18; 313287514Sdim uint64_t f19; 314287514Sdim uint64_t f20; 315287514Sdim uint64_t f21; 316287514Sdim uint64_t f22; 317287514Sdim uint64_t f23; 318287514Sdim uint64_t f24; 319287514Sdim uint64_t f25; 320287514Sdim uint64_t f26; 321287514Sdim uint64_t f27; 322287514Sdim uint64_t f28; 323287514Sdim uint64_t f29; 324287514Sdim uint64_t f30; 325287514Sdim uint64_t f31; 326287514Sdim uint32_t fcsr; 327287514Sdim uint32_t fir; 328287514Sdim uint32_t config5; 329287514Sdim}; 330287514Sdim 331287514Sdimstruct MSAReg 332287514Sdim{ 333287514Sdim uint8_t byte[16]; 334287514Sdim}; 335287514Sdim 336287514Sdimstruct MSA_linux_mips 337287514Sdim{ 338287514Sdim MSAReg w0; 339287514Sdim MSAReg w1; 340287514Sdim MSAReg w2; 341287514Sdim MSAReg w3; 342287514Sdim MSAReg w4; 343287514Sdim MSAReg w5; 344287514Sdim MSAReg w6; 345287514Sdim MSAReg w7; 346287514Sdim MSAReg w8; 347287514Sdim MSAReg w9; 348287514Sdim MSAReg w10; 349287514Sdim MSAReg w11; 350287514Sdim MSAReg w12; 351287514Sdim MSAReg w13; 352287514Sdim MSAReg w14; 353287514Sdim MSAReg w15; 354287514Sdim MSAReg w16; 355287514Sdim MSAReg w17; 356287514Sdim MSAReg w18; 357287514Sdim MSAReg w19; 358287514Sdim MSAReg w20; 359287514Sdim MSAReg w21; 360287514Sdim MSAReg w22; 361287514Sdim MSAReg w23; 362287514Sdim MSAReg w24; 363287514Sdim MSAReg w25; 364287514Sdim MSAReg w26; 365287514Sdim MSAReg w27; 366287514Sdim MSAReg w28; 367287514Sdim MSAReg w29; 368287514Sdim MSAReg w30; 369287514Sdim MSAReg w31; 370287514Sdim uint32_t fcsr; /* FPU control status register */ 371287514Sdim uint32_t fir; /* FPU implementaion revision */ 372287514Sdim uint32_t mcsr; /* MSA control status register */ 373287514Sdim uint32_t mir; /* MSA implementation revision */ 374287514Sdim uint32_t config5; /* Config5 register */ 375287514Sdim}; 376287514Sdim 377287514Sdimstruct UserArea 378287514Sdim{ 379287514Sdim GPR_linux_mips gpr; // General purpose registers. 380287514Sdim FPR_linux_mips fpr; // Floating point registers. 381287514Sdim MSA_linux_mips msa; // MSA registers. 382287514Sdim}; 383287514Sdim 384287514Sdim#endif // liblldb_RegisterContext_mips64_H_ 385