1234287Sdim/*===---- cpuid.h - X86 cpu model detection --------------------------------=== 2234287Sdim * 3234287Sdim * Permission is hereby granted, free of charge, to any person obtaining a copy 4234287Sdim * of this software and associated documentation files (the "Software"), to deal 5234287Sdim * in the Software without restriction, including without limitation the rights 6234287Sdim * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7234287Sdim * copies of the Software, and to permit persons to whom the Software is 8234287Sdim * furnished to do so, subject to the following conditions: 9234287Sdim * 10234287Sdim * The above copyright notice and this permission notice shall be included in 11234287Sdim * all copies or substantial portions of the Software. 12234287Sdim * 13234287Sdim * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14234287Sdim * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15234287Sdim * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16234287Sdim * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17234287Sdim * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18234287Sdim * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19234287Sdim * THE SOFTWARE. 20234287Sdim * 21234287Sdim *===-----------------------------------------------------------------------=== 22234287Sdim */ 23234287Sdim 24234287Sdim#if !(__x86_64__ || __i386__) 25234287Sdim#error this header is for x86 only 26234287Sdim#endif 27234287Sdim 28280031Sdim/* Responses identification request with %eax 0 */ 29280031Sdim/* AMD: "AuthenticAMD" */ 30280031Sdim#define signature_AMD_ebx 0x68747541 31280031Sdim#define signature_AMD_edx 0x69746e65 32280031Sdim#define signature_AMD_ecx 0x444d4163 33280031Sdim/* CENTAUR: "CentaurHauls" */ 34280031Sdim#define signature_CENTAUR_ebx 0x746e6543 35280031Sdim#define signature_CENTAUR_edx 0x48727561 36280031Sdim#define signature_CENTAUR_ecx 0x736c7561 37280031Sdim/* CYRIX: "CyrixInstead" */ 38280031Sdim#define signature_CYRIX_ebx 0x69727943 39280031Sdim#define signature_CYRIX_edx 0x736e4978 40280031Sdim#define signature_CYRIX_ecx 0x64616574 41280031Sdim/* INTEL: "GenuineIntel" */ 42280031Sdim#define signature_INTEL_ebx 0x756e6547 43280031Sdim#define signature_INTEL_edx 0x49656e69 44280031Sdim#define signature_INTEL_ecx 0x6c65746e 45280031Sdim/* TM1: "TransmetaCPU" */ 46280031Sdim#define signature_TM1_ebx 0x6e617254 47280031Sdim#define signature_TM1_edx 0x74656d73 48280031Sdim#define signature_TM1_ecx 0x55504361 49280031Sdim/* TM2: "GenuineTMx86" */ 50280031Sdim#define signature_TM2_ebx 0x756e6547 51280031Sdim#define signature_TM2_edx 0x54656e69 52280031Sdim#define signature_TM2_ecx 0x3638784d 53280031Sdim/* NSC: "Geode by NSC" */ 54280031Sdim#define signature_NSC_ebx 0x646f6547 55280031Sdim#define signature_NSC_edx 0x43534e20 56280031Sdim#define signature_NSC_ecx 0x79622065 57280031Sdim/* NEXGEN: "NexGenDriven" */ 58280031Sdim#define signature_NEXGEN_ebx 0x4778654e 59280031Sdim#define signature_NEXGEN_edx 0x72446e65 60280031Sdim#define signature_NEXGEN_ecx 0x6e657669 61280031Sdim/* RISE: "RiseRiseRise" */ 62280031Sdim#define signature_RISE_ebx 0x65736952 63280031Sdim#define signature_RISE_edx 0x65736952 64280031Sdim#define signature_RISE_ecx 0x65736952 65280031Sdim/* SIS: "SiS SiS SiS " */ 66280031Sdim#define signature_SIS_ebx 0x20536953 67280031Sdim#define signature_SIS_edx 0x20536953 68280031Sdim#define signature_SIS_ecx 0x20536953 69280031Sdim/* UMC: "UMC UMC UMC " */ 70280031Sdim#define signature_UMC_ebx 0x20434d55 71280031Sdim#define signature_UMC_edx 0x20434d55 72280031Sdim#define signature_UMC_ecx 0x20434d55 73280031Sdim/* VIA: "VIA VIA VIA " */ 74280031Sdim#define signature_VIA_ebx 0x20414956 75280031Sdim#define signature_VIA_edx 0x20414956 76280031Sdim#define signature_VIA_ecx 0x20414956 77280031Sdim/* VORTEX: "Vortex86 SoC" */ 78280031Sdim#define signature_VORTEX_ebx 0x74726f56 79280031Sdim#define signature_VORTEX_edx 0x36387865 80280031Sdim#define signature_VORTEX_ecx 0x436f5320 81280031Sdim 82253802Sdim/* Features in %ecx for level 1 */ 83253802Sdim#define bit_SSE3 0x00000001 84253802Sdim#define bit_PCLMULQDQ 0x00000002 85253802Sdim#define bit_DTES64 0x00000004 86253802Sdim#define bit_MONITOR 0x00000008 87253802Sdim#define bit_DSCPL 0x00000010 88253802Sdim#define bit_VMX 0x00000020 89253802Sdim#define bit_SMX 0x00000040 90253802Sdim#define bit_EIST 0x00000080 91253802Sdim#define bit_TM2 0x00000100 92253802Sdim#define bit_SSSE3 0x00000200 93253802Sdim#define bit_CNXTID 0x00000400 94253802Sdim#define bit_FMA 0x00001000 95253802Sdim#define bit_CMPXCHG16B 0x00002000 96253802Sdim#define bit_xTPR 0x00004000 97253802Sdim#define bit_PDCM 0x00008000 98253802Sdim#define bit_PCID 0x00020000 99253802Sdim#define bit_DCA 0x00040000 100253802Sdim#define bit_SSE41 0x00080000 101253802Sdim#define bit_SSE42 0x00100000 102253802Sdim#define bit_x2APIC 0x00200000 103253802Sdim#define bit_MOVBE 0x00400000 104253802Sdim#define bit_POPCNT 0x00800000 105253802Sdim#define bit_TSCDeadline 0x01000000 106253802Sdim#define bit_AESNI 0x02000000 107253802Sdim#define bit_XSAVE 0x04000000 108253802Sdim#define bit_OSXSAVE 0x08000000 109253802Sdim#define bit_AVX 0x10000000 110280031Sdim#define bit_RDRND 0x40000000 111253802Sdim 112253802Sdim/* Features in %edx for level 1 */ 113253802Sdim#define bit_FPU 0x00000001 114253802Sdim#define bit_VME 0x00000002 115253802Sdim#define bit_DE 0x00000004 116253802Sdim#define bit_PSE 0x00000008 117253802Sdim#define bit_TSC 0x00000010 118253802Sdim#define bit_MSR 0x00000020 119253802Sdim#define bit_PAE 0x00000040 120253802Sdim#define bit_MCE 0x00000080 121253802Sdim#define bit_CX8 0x00000100 122253802Sdim#define bit_APIC 0x00000200 123253802Sdim#define bit_SEP 0x00000800 124253802Sdim#define bit_MTRR 0x00001000 125253802Sdim#define bit_PGE 0x00002000 126253802Sdim#define bit_MCA 0x00004000 127253802Sdim#define bit_CMOV 0x00008000 128253802Sdim#define bit_PAT 0x00010000 129253802Sdim#define bit_PSE36 0x00020000 130253802Sdim#define bit_PSN 0x00040000 131253802Sdim#define bit_CLFSH 0x00080000 132253802Sdim#define bit_DS 0x00200000 133253802Sdim#define bit_ACPI 0x00400000 134253802Sdim#define bit_MMX 0x00800000 135253802Sdim#define bit_FXSR 0x01000000 136259498Sdim#define bit_FXSAVE bit_FXSR /* for gcc compat */ 137253802Sdim#define bit_SSE 0x02000000 138253802Sdim#define bit_SSE2 0x04000000 139253802Sdim#define bit_SS 0x08000000 140253802Sdim#define bit_HTT 0x10000000 141253802Sdim#define bit_TM 0x20000000 142253802Sdim#define bit_PBE 0x80000000 143253802Sdim 144253802Sdim/* Features in %ebx for level 7 sub-leaf 0 */ 145253802Sdim#define bit_FSGSBASE 0x00000001 146253802Sdim#define bit_SMEP 0x00000080 147253802Sdim#define bit_ENH_MOVSB 0x00000200 148253802Sdim 149253802Sdim#if __i386__ 150253802Sdim#define __cpuid(__level, __eax, __ebx, __ecx, __edx) \ 151280031Sdim __asm("cpuid" : "=a"(__eax), "=b" (__ebx), "=c"(__ecx), "=d"(__edx) \ 152280031Sdim : "0"(__level)) 153280031Sdim 154280031Sdim#define __cpuid_count(__level, __count, __eax, __ebx, __ecx, __edx) \ 155280031Sdim __asm("cpuid" : "=a"(__eax), "=b" (__ebx), "=c"(__ecx), "=d"(__edx) \ 156280031Sdim : "0"(__level), "2"(__count)) 157280031Sdim#else 158280031Sdim/* x86-64 uses %rbx as the base register, so preserve it. */ 159280031Sdim#define __cpuid(__level, __eax, __ebx, __ecx, __edx) \ 160280031Sdim __asm(" xchgq %%rbx,%q1\n" \ 161253802Sdim " cpuid\n" \ 162280031Sdim " xchgq %%rbx,%q1" \ 163253802Sdim : "=a"(__eax), "=r" (__ebx), "=c"(__ecx), "=d"(__edx) \ 164253802Sdim : "0"(__level)) 165253802Sdim 166253802Sdim#define __cpuid_count(__level, __count, __eax, __ebx, __ecx, __edx) \ 167280031Sdim __asm(" xchgq %%rbx,%q1\n" \ 168253802Sdim " cpuid\n" \ 169280031Sdim " xchgq %%rbx,%q1" \ 170253802Sdim : "=a"(__eax), "=r" (__ebx), "=c"(__ecx), "=d"(__edx) \ 171253802Sdim : "0"(__level), "2"(__count)) 172253802Sdim#endif 173253802Sdim 174249423Sdimstatic __inline int __get_cpuid (unsigned int __level, unsigned int *__eax, 175249423Sdim unsigned int *__ebx, unsigned int *__ecx, 176249423Sdim unsigned int *__edx) { 177253802Sdim __cpuid(__level, *__eax, *__ebx, *__ecx, *__edx); 178234287Sdim return 1; 179234287Sdim} 180253802Sdim 181253802Sdimstatic __inline int __get_cpuid_max (unsigned int __level, unsigned int *__sig) 182253802Sdim{ 183253802Sdim unsigned int __eax, __ebx, __ecx, __edx; 184253802Sdim#if __i386__ 185253802Sdim int __cpuid_supported; 186253802Sdim 187253802Sdim __asm(" pushfl\n" 188253802Sdim " popl %%eax\n" 189253802Sdim " movl %%eax,%%ecx\n" 190253802Sdim " xorl $0x00200000,%%eax\n" 191253802Sdim " pushl %%eax\n" 192253802Sdim " popfl\n" 193253802Sdim " pushfl\n" 194253802Sdim " popl %%eax\n" 195253802Sdim " movl $0,%0\n" 196253802Sdim " cmpl %%eax,%%ecx\n" 197253802Sdim " je 1f\n" 198253802Sdim " movl $1,%0\n" 199253802Sdim "1:" 200253802Sdim : "=r" (__cpuid_supported) : : "eax", "ecx"); 201253802Sdim if (!__cpuid_supported) 202253802Sdim return 0; 203253802Sdim#endif 204253802Sdim 205253802Sdim __cpuid(__level, __eax, __ebx, __ecx, __edx); 206253802Sdim if (__sig) 207253802Sdim *__sig = __ebx; 208253802Sdim return __eax; 209253802Sdim} 210