InstCombineSimplifyDemanded.cpp revision 218893
133965Sjdp//===- InstCombineSimplifyDemanded.cpp ------------------------------------===// 2130561Sobrien// 333965Sjdp// The LLVM Compiler Infrastructure 433965Sjdp// 533965Sjdp// This file is distributed under the University of Illinois Open Source 633965Sjdp// License. See LICENSE.TXT for details. 733965Sjdp// 833965Sjdp//===----------------------------------------------------------------------===// 933965Sjdp// 1033965Sjdp// This file contains logic for simplifying instructions based on information 1133965Sjdp// about how they are used. 1233965Sjdp// 1333965Sjdp//===----------------------------------------------------------------------===// 1433965Sjdp 1533965Sjdp 1633965Sjdp#include "InstCombine.h" 1733965Sjdp#include "llvm/Target/TargetData.h" 1833965Sjdp#include "llvm/IntrinsicInst.h" 1933965Sjdp 2033965Sjdpusing namespace llvm; 2133965Sjdp 2233965Sjdp 2333965Sjdp/// ShrinkDemandedConstant - Check to see if the specified operand of the 2433965Sjdp/// specified instruction is a constant integer. If so, check to see if there 25130561Sobrien/// are any bits set in the constant that are not demanded. If so, shrink the 26130561Sobrien/// constant and return true. 27130561Sobrienstatic bool ShrinkDemandedConstant(Instruction *I, unsigned OpNo, 28130561Sobrien APInt Demanded) { 29130561Sobrien assert(I && "No instruction?"); 30130561Sobrien assert(OpNo < I->getNumOperands() && "Operand index too large"); 31130561Sobrien 32130561Sobrien // If the operand is not a constant integer, nothing to do. 33130561Sobrien ConstantInt *OpC = dyn_cast<ConstantInt>(I->getOperand(OpNo)); 34130561Sobrien if (!OpC) return false; 35130561Sobrien 36130561Sobrien // If there are no bits set that aren't demanded, nothing to do. 37130561Sobrien Demanded = Demanded.zextOrTrunc(OpC->getValue().getBitWidth()); 3833965Sjdp if ((~Demanded & OpC->getValue()) == 0) 3933965Sjdp return false; 40 41 // This instruction is producing bits that are not demanded. Shrink the RHS. 42 Demanded &= OpC->getValue(); 43 I->setOperand(OpNo, ConstantInt::get(OpC->getType(), Demanded)); 44 return true; 45} 46 47 48 49/// SimplifyDemandedInstructionBits - Inst is an integer instruction that 50/// SimplifyDemandedBits knows about. See if the instruction has any 51/// properties that allow us to simplify its operands. 52bool InstCombiner::SimplifyDemandedInstructionBits(Instruction &Inst) { 53 unsigned BitWidth = Inst.getType()->getScalarSizeInBits(); 54 APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0); 55 APInt DemandedMask(APInt::getAllOnesValue(BitWidth)); 56 57 Value *V = SimplifyDemandedUseBits(&Inst, DemandedMask, 58 KnownZero, KnownOne, 0); 59 if (V == 0) return false; 60 if (V == &Inst) return true; 61 ReplaceInstUsesWith(Inst, V); 62 return true; 63} 64 65/// SimplifyDemandedBits - This form of SimplifyDemandedBits simplifies the 66/// specified instruction operand if possible, updating it in place. It returns 67/// true if it made any change and false otherwise. 68bool InstCombiner::SimplifyDemandedBits(Use &U, APInt DemandedMask, 69 APInt &KnownZero, APInt &KnownOne, 70 unsigned Depth) { 71 Value *NewVal = SimplifyDemandedUseBits(U.get(), DemandedMask, 72 KnownZero, KnownOne, Depth); 73 if (NewVal == 0) return false; 74 U = NewVal; 75 return true; 76} 77 78 79/// SimplifyDemandedUseBits - This function attempts to replace V with a simpler 80/// value based on the demanded bits. When this function is called, it is known 81/// that only the bits set in DemandedMask of the result of V are ever used 82/// downstream. Consequently, depending on the mask and V, it may be possible 83/// to replace V with a constant or one of its operands. In such cases, this 84/// function does the replacement and returns true. In all other cases, it 85/// returns false after analyzing the expression and setting KnownOne and known 86/// to be one in the expression. KnownZero contains all the bits that are known 87/// to be zero in the expression. These are provided to potentially allow the 88/// caller (which might recursively be SimplifyDemandedBits itself) to simplify 89/// the expression. KnownOne and KnownZero always follow the invariant that 90/// KnownOne & KnownZero == 0. That is, a bit can't be both 1 and 0. Note that 91/// the bits in KnownOne and KnownZero may only be accurate for those bits set 92/// in DemandedMask. Note also that the bitwidth of V, DemandedMask, KnownZero 93/// and KnownOne must all be the same. 94/// 95/// This returns null if it did not change anything and it permits no 96/// simplification. This returns V itself if it did some simplification of V's 97/// operands based on the information about what bits are demanded. This returns 98/// some other non-null value if it found out that V is equal to another value 99/// in the context where the specified bits are demanded, but not for all users. 100Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask, 101 APInt &KnownZero, APInt &KnownOne, 102 unsigned Depth) { 103 assert(V != 0 && "Null pointer of Value???"); 104 assert(Depth <= 6 && "Limit Search Depth"); 105 uint32_t BitWidth = DemandedMask.getBitWidth(); 106 const Type *VTy = V->getType(); 107 assert((TD || !VTy->isPointerTy()) && 108 "SimplifyDemandedBits needs to know bit widths!"); 109 assert((!TD || TD->getTypeSizeInBits(VTy->getScalarType()) == BitWidth) && 110 (!VTy->isIntOrIntVectorTy() || 111 VTy->getScalarSizeInBits() == BitWidth) && 112 KnownZero.getBitWidth() == BitWidth && 113 KnownOne.getBitWidth() == BitWidth && 114 "Value *V, DemandedMask, KnownZero and KnownOne " 115 "must have same BitWidth"); 116 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 117 // We know all of the bits for a constant! 118 KnownOne = CI->getValue() & DemandedMask; 119 KnownZero = ~KnownOne & DemandedMask; 120 return 0; 121 } 122 if (isa<ConstantPointerNull>(V)) { 123 // We know all of the bits for a constant! 124 KnownOne.clearAllBits(); 125 KnownZero = DemandedMask; 126 return 0; 127 } 128 129 KnownZero.clearAllBits(); 130 KnownOne.clearAllBits(); 131 if (DemandedMask == 0) { // Not demanding any bits from V. 132 if (isa<UndefValue>(V)) 133 return 0; 134 return UndefValue::get(VTy); 135 } 136 137 if (Depth == 6) // Limit search depth. 138 return 0; 139 140 APInt LHSKnownZero(BitWidth, 0), LHSKnownOne(BitWidth, 0); 141 APInt RHSKnownZero(BitWidth, 0), RHSKnownOne(BitWidth, 0); 142 143 Instruction *I = dyn_cast<Instruction>(V); 144 if (!I) { 145 ComputeMaskedBits(V, DemandedMask, KnownZero, KnownOne, Depth); 146 return 0; // Only analyze instructions. 147 } 148 149 // If there are multiple uses of this value and we aren't at the root, then 150 // we can't do any simplifications of the operands, because DemandedMask 151 // only reflects the bits demanded by *one* of the users. 152 if (Depth != 0 && !I->hasOneUse()) { 153 // Despite the fact that we can't simplify this instruction in all User's 154 // context, we can at least compute the knownzero/knownone bits, and we can 155 // do simplifications that apply to *just* the one user if we know that 156 // this instruction has a simpler value in that context. 157 if (I->getOpcode() == Instruction::And) { 158 // If either the LHS or the RHS are Zero, the result is zero. 159 ComputeMaskedBits(I->getOperand(1), DemandedMask, 160 RHSKnownZero, RHSKnownOne, Depth+1); 161 ComputeMaskedBits(I->getOperand(0), DemandedMask & ~RHSKnownZero, 162 LHSKnownZero, LHSKnownOne, Depth+1); 163 164 // If all of the demanded bits are known 1 on one side, return the other. 165 // These bits cannot contribute to the result of the 'and' in this 166 // context. 167 if ((DemandedMask & ~LHSKnownZero & RHSKnownOne) == 168 (DemandedMask & ~LHSKnownZero)) 169 return I->getOperand(0); 170 if ((DemandedMask & ~RHSKnownZero & LHSKnownOne) == 171 (DemandedMask & ~RHSKnownZero)) 172 return I->getOperand(1); 173 174 // If all of the demanded bits in the inputs are known zeros, return zero. 175 if ((DemandedMask & (RHSKnownZero|LHSKnownZero)) == DemandedMask) 176 return Constant::getNullValue(VTy); 177 178 } else if (I->getOpcode() == Instruction::Or) { 179 // We can simplify (X|Y) -> X or Y in the user's context if we know that 180 // only bits from X or Y are demanded. 181 182 // If either the LHS or the RHS are One, the result is One. 183 ComputeMaskedBits(I->getOperand(1), DemandedMask, 184 RHSKnownZero, RHSKnownOne, Depth+1); 185 ComputeMaskedBits(I->getOperand(0), DemandedMask & ~RHSKnownOne, 186 LHSKnownZero, LHSKnownOne, Depth+1); 187 188 // If all of the demanded bits are known zero on one side, return the 189 // other. These bits cannot contribute to the result of the 'or' in this 190 // context. 191 if ((DemandedMask & ~LHSKnownOne & RHSKnownZero) == 192 (DemandedMask & ~LHSKnownOne)) 193 return I->getOperand(0); 194 if ((DemandedMask & ~RHSKnownOne & LHSKnownZero) == 195 (DemandedMask & ~RHSKnownOne)) 196 return I->getOperand(1); 197 198 // If all of the potentially set bits on one side are known to be set on 199 // the other side, just use the 'other' side. 200 if ((DemandedMask & (~RHSKnownZero) & LHSKnownOne) == 201 (DemandedMask & (~RHSKnownZero))) 202 return I->getOperand(0); 203 if ((DemandedMask & (~LHSKnownZero) & RHSKnownOne) == 204 (DemandedMask & (~LHSKnownZero))) 205 return I->getOperand(1); 206 } 207 208 // Compute the KnownZero/KnownOne bits to simplify things downstream. 209 ComputeMaskedBits(I, DemandedMask, KnownZero, KnownOne, Depth); 210 return 0; 211 } 212 213 // If this is the root being simplified, allow it to have multiple uses, 214 // just set the DemandedMask to all bits so that we can try to simplify the 215 // operands. This allows visitTruncInst (for example) to simplify the 216 // operand of a trunc without duplicating all the logic below. 217 if (Depth == 0 && !V->hasOneUse()) 218 DemandedMask = APInt::getAllOnesValue(BitWidth); 219 220 switch (I->getOpcode()) { 221 default: 222 ComputeMaskedBits(I, DemandedMask, KnownZero, KnownOne, Depth); 223 break; 224 case Instruction::And: 225 // If either the LHS or the RHS are Zero, the result is zero. 226 if (SimplifyDemandedBits(I->getOperandUse(1), DemandedMask, 227 RHSKnownZero, RHSKnownOne, Depth+1) || 228 SimplifyDemandedBits(I->getOperandUse(0), DemandedMask & ~RHSKnownZero, 229 LHSKnownZero, LHSKnownOne, Depth+1)) 230 return I; 231 assert(!(RHSKnownZero & RHSKnownOne) && "Bits known to be one AND zero?"); 232 assert(!(LHSKnownZero & LHSKnownOne) && "Bits known to be one AND zero?"); 233 234 // If all of the demanded bits are known 1 on one side, return the other. 235 // These bits cannot contribute to the result of the 'and'. 236 if ((DemandedMask & ~LHSKnownZero & RHSKnownOne) == 237 (DemandedMask & ~LHSKnownZero)) 238 return I->getOperand(0); 239 if ((DemandedMask & ~RHSKnownZero & LHSKnownOne) == 240 (DemandedMask & ~RHSKnownZero)) 241 return I->getOperand(1); 242 243 // If all of the demanded bits in the inputs are known zeros, return zero. 244 if ((DemandedMask & (RHSKnownZero|LHSKnownZero)) == DemandedMask) 245 return Constant::getNullValue(VTy); 246 247 // If the RHS is a constant, see if we can simplify it. 248 if (ShrinkDemandedConstant(I, 1, DemandedMask & ~LHSKnownZero)) 249 return I; 250 251 // Output known-1 bits are only known if set in both the LHS & RHS. 252 KnownOne = RHSKnownOne & LHSKnownOne; 253 // Output known-0 are known to be clear if zero in either the LHS | RHS. 254 KnownZero = RHSKnownZero | LHSKnownZero; 255 break; 256 case Instruction::Or: 257 // If either the LHS or the RHS are One, the result is One. 258 if (SimplifyDemandedBits(I->getOperandUse(1), DemandedMask, 259 RHSKnownZero, RHSKnownOne, Depth+1) || 260 SimplifyDemandedBits(I->getOperandUse(0), DemandedMask & ~RHSKnownOne, 261 LHSKnownZero, LHSKnownOne, Depth+1)) 262 return I; 263 assert(!(RHSKnownZero & RHSKnownOne) && "Bits known to be one AND zero?"); 264 assert(!(LHSKnownZero & LHSKnownOne) && "Bits known to be one AND zero?"); 265 266 // If all of the demanded bits are known zero on one side, return the other. 267 // These bits cannot contribute to the result of the 'or'. 268 if ((DemandedMask & ~LHSKnownOne & RHSKnownZero) == 269 (DemandedMask & ~LHSKnownOne)) 270 return I->getOperand(0); 271 if ((DemandedMask & ~RHSKnownOne & LHSKnownZero) == 272 (DemandedMask & ~RHSKnownOne)) 273 return I->getOperand(1); 274 275 // If all of the potentially set bits on one side are known to be set on 276 // the other side, just use the 'other' side. 277 if ((DemandedMask & (~RHSKnownZero) & LHSKnownOne) == 278 (DemandedMask & (~RHSKnownZero))) 279 return I->getOperand(0); 280 if ((DemandedMask & (~LHSKnownZero) & RHSKnownOne) == 281 (DemandedMask & (~LHSKnownZero))) 282 return I->getOperand(1); 283 284 // If the RHS is a constant, see if we can simplify it. 285 if (ShrinkDemandedConstant(I, 1, DemandedMask)) 286 return I; 287 288 // Output known-0 bits are only known if clear in both the LHS & RHS. 289 KnownZero = RHSKnownZero & LHSKnownZero; 290 // Output known-1 are known to be set if set in either the LHS | RHS. 291 KnownOne = RHSKnownOne | LHSKnownOne; 292 break; 293 case Instruction::Xor: { 294 if (SimplifyDemandedBits(I->getOperandUse(1), DemandedMask, 295 RHSKnownZero, RHSKnownOne, Depth+1) || 296 SimplifyDemandedBits(I->getOperandUse(0), DemandedMask, 297 LHSKnownZero, LHSKnownOne, Depth+1)) 298 return I; 299 assert(!(RHSKnownZero & RHSKnownOne) && "Bits known to be one AND zero?"); 300 assert(!(LHSKnownZero & LHSKnownOne) && "Bits known to be one AND zero?"); 301 302 // If all of the demanded bits are known zero on one side, return the other. 303 // These bits cannot contribute to the result of the 'xor'. 304 if ((DemandedMask & RHSKnownZero) == DemandedMask) 305 return I->getOperand(0); 306 if ((DemandedMask & LHSKnownZero) == DemandedMask) 307 return I->getOperand(1); 308 309 // If all of the demanded bits are known to be zero on one side or the 310 // other, turn this into an *inclusive* or. 311 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 312 if ((DemandedMask & ~RHSKnownZero & ~LHSKnownZero) == 0) { 313 Instruction *Or = 314 BinaryOperator::CreateOr(I->getOperand(0), I->getOperand(1), 315 I->getName()); 316 return InsertNewInstBefore(Or, *I); 317 } 318 319 // If all of the demanded bits on one side are known, and all of the set 320 // bits on that side are also known to be set on the other side, turn this 321 // into an AND, as we know the bits will be cleared. 322 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 323 if ((DemandedMask & (RHSKnownZero|RHSKnownOne)) == DemandedMask) { 324 // all known 325 if ((RHSKnownOne & LHSKnownOne) == RHSKnownOne) { 326 Constant *AndC = Constant::getIntegerValue(VTy, 327 ~RHSKnownOne & DemandedMask); 328 Instruction *And = 329 BinaryOperator::CreateAnd(I->getOperand(0), AndC, "tmp"); 330 return InsertNewInstBefore(And, *I); 331 } 332 } 333 334 // If the RHS is a constant, see if we can simplify it. 335 // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1. 336 if (ShrinkDemandedConstant(I, 1, DemandedMask)) 337 return I; 338 339 // If our LHS is an 'and' and if it has one use, and if any of the bits we 340 // are flipping are known to be set, then the xor is just resetting those 341 // bits to zero. We can just knock out bits from the 'and' and the 'xor', 342 // simplifying both of them. 343 if (Instruction *LHSInst = dyn_cast<Instruction>(I->getOperand(0))) 344 if (LHSInst->getOpcode() == Instruction::And && LHSInst->hasOneUse() && 345 isa<ConstantInt>(I->getOperand(1)) && 346 isa<ConstantInt>(LHSInst->getOperand(1)) && 347 (LHSKnownOne & RHSKnownOne & DemandedMask) != 0) { 348 ConstantInt *AndRHS = cast<ConstantInt>(LHSInst->getOperand(1)); 349 ConstantInt *XorRHS = cast<ConstantInt>(I->getOperand(1)); 350 APInt NewMask = ~(LHSKnownOne & RHSKnownOne & DemandedMask); 351 352 Constant *AndC = 353 ConstantInt::get(I->getType(), NewMask & AndRHS->getValue()); 354 Instruction *NewAnd = 355 BinaryOperator::CreateAnd(I->getOperand(0), AndC, "tmp"); 356 InsertNewInstBefore(NewAnd, *I); 357 358 Constant *XorC = 359 ConstantInt::get(I->getType(), NewMask & XorRHS->getValue()); 360 Instruction *NewXor = 361 BinaryOperator::CreateXor(NewAnd, XorC, "tmp"); 362 return InsertNewInstBefore(NewXor, *I); 363 } 364 365 // Output known-0 bits are known if clear or set in both the LHS & RHS. 366 KnownZero= (RHSKnownZero & LHSKnownZero) | (RHSKnownOne & LHSKnownOne); 367 // Output known-1 are known to be set if set in only one of the LHS, RHS. 368 KnownOne = (RHSKnownZero & LHSKnownOne) | (RHSKnownOne & LHSKnownZero); 369 break; 370 } 371 case Instruction::Select: 372 if (SimplifyDemandedBits(I->getOperandUse(2), DemandedMask, 373 RHSKnownZero, RHSKnownOne, Depth+1) || 374 SimplifyDemandedBits(I->getOperandUse(1), DemandedMask, 375 LHSKnownZero, LHSKnownOne, Depth+1)) 376 return I; 377 assert(!(RHSKnownZero & RHSKnownOne) && "Bits known to be one AND zero?"); 378 assert(!(LHSKnownZero & LHSKnownOne) && "Bits known to be one AND zero?"); 379 380 // If the operands are constants, see if we can simplify them. 381 if (ShrinkDemandedConstant(I, 1, DemandedMask) || 382 ShrinkDemandedConstant(I, 2, DemandedMask)) 383 return I; 384 385 // Only known if known in both the LHS and RHS. 386 KnownOne = RHSKnownOne & LHSKnownOne; 387 KnownZero = RHSKnownZero & LHSKnownZero; 388 break; 389 case Instruction::Trunc: { 390 unsigned truncBf = I->getOperand(0)->getType()->getScalarSizeInBits(); 391 DemandedMask = DemandedMask.zext(truncBf); 392 KnownZero = KnownZero.zext(truncBf); 393 KnownOne = KnownOne.zext(truncBf); 394 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMask, 395 KnownZero, KnownOne, Depth+1)) 396 return I; 397 DemandedMask = DemandedMask.trunc(BitWidth); 398 KnownZero = KnownZero.trunc(BitWidth); 399 KnownOne = KnownOne.trunc(BitWidth); 400 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?"); 401 break; 402 } 403 case Instruction::BitCast: 404 if (!I->getOperand(0)->getType()->isIntOrIntVectorTy()) 405 return 0; // vector->int or fp->int? 406 407 if (const VectorType *DstVTy = dyn_cast<VectorType>(I->getType())) { 408 if (const VectorType *SrcVTy = 409 dyn_cast<VectorType>(I->getOperand(0)->getType())) { 410 if (DstVTy->getNumElements() != SrcVTy->getNumElements()) 411 // Don't touch a bitcast between vectors of different element counts. 412 return 0; 413 } else 414 // Don't touch a scalar-to-vector bitcast. 415 return 0; 416 } else if (I->getOperand(0)->getType()->isVectorTy()) 417 // Don't touch a vector-to-scalar bitcast. 418 return 0; 419 420 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMask, 421 KnownZero, KnownOne, Depth+1)) 422 return I; 423 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?"); 424 break; 425 case Instruction::ZExt: { 426 // Compute the bits in the result that are not present in the input. 427 unsigned SrcBitWidth =I->getOperand(0)->getType()->getScalarSizeInBits(); 428 429 DemandedMask = DemandedMask.trunc(SrcBitWidth); 430 KnownZero = KnownZero.trunc(SrcBitWidth); 431 KnownOne = KnownOne.trunc(SrcBitWidth); 432 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMask, 433 KnownZero, KnownOne, Depth+1)) 434 return I; 435 DemandedMask = DemandedMask.zext(BitWidth); 436 KnownZero = KnownZero.zext(BitWidth); 437 KnownOne = KnownOne.zext(BitWidth); 438 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?"); 439 // The top bits are known to be zero. 440 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - SrcBitWidth); 441 break; 442 } 443 case Instruction::SExt: { 444 // Compute the bits in the result that are not present in the input. 445 unsigned SrcBitWidth =I->getOperand(0)->getType()->getScalarSizeInBits(); 446 447 APInt InputDemandedBits = DemandedMask & 448 APInt::getLowBitsSet(BitWidth, SrcBitWidth); 449 450 APInt NewBits(APInt::getHighBitsSet(BitWidth, BitWidth - SrcBitWidth)); 451 // If any of the sign extended bits are demanded, we know that the sign 452 // bit is demanded. 453 if ((NewBits & DemandedMask) != 0) 454 InputDemandedBits.setBit(SrcBitWidth-1); 455 456 InputDemandedBits = InputDemandedBits.trunc(SrcBitWidth); 457 KnownZero = KnownZero.trunc(SrcBitWidth); 458 KnownOne = KnownOne.trunc(SrcBitWidth); 459 if (SimplifyDemandedBits(I->getOperandUse(0), InputDemandedBits, 460 KnownZero, KnownOne, Depth+1)) 461 return I; 462 InputDemandedBits = InputDemandedBits.zext(BitWidth); 463 KnownZero = KnownZero.zext(BitWidth); 464 KnownOne = KnownOne.zext(BitWidth); 465 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?"); 466 467 // If the sign bit of the input is known set or clear, then we know the 468 // top bits of the result. 469 470 // If the input sign bit is known zero, or if the NewBits are not demanded 471 // convert this into a zero extension. 472 if (KnownZero[SrcBitWidth-1] || (NewBits & ~DemandedMask) == NewBits) { 473 // Convert to ZExt cast 474 CastInst *NewCast = new ZExtInst(I->getOperand(0), VTy, I->getName()); 475 return InsertNewInstBefore(NewCast, *I); 476 } else if (KnownOne[SrcBitWidth-1]) { // Input sign bit known set 477 KnownOne |= NewBits; 478 } 479 break; 480 } 481 case Instruction::Add: { 482 // Figure out what the input bits are. If the top bits of the and result 483 // are not demanded, then the add doesn't demand them from its input 484 // either. 485 unsigned NLZ = DemandedMask.countLeadingZeros(); 486 487 // If there is a constant on the RHS, there are a variety of xformations 488 // we can do. 489 if (ConstantInt *RHS = dyn_cast<ConstantInt>(I->getOperand(1))) { 490 // If null, this should be simplified elsewhere. Some of the xforms here 491 // won't work if the RHS is zero. 492 if (RHS->isZero()) 493 break; 494 495 // If the top bit of the output is demanded, demand everything from the 496 // input. Otherwise, we demand all the input bits except NLZ top bits. 497 APInt InDemandedBits(APInt::getLowBitsSet(BitWidth, BitWidth - NLZ)); 498 499 // Find information about known zero/one bits in the input. 500 if (SimplifyDemandedBits(I->getOperandUse(0), InDemandedBits, 501 LHSKnownZero, LHSKnownOne, Depth+1)) 502 return I; 503 504 // If the RHS of the add has bits set that can't affect the input, reduce 505 // the constant. 506 if (ShrinkDemandedConstant(I, 1, InDemandedBits)) 507 return I; 508 509 // Avoid excess work. 510 if (LHSKnownZero == 0 && LHSKnownOne == 0) 511 break; 512 513 // Turn it into OR if input bits are zero. 514 if ((LHSKnownZero & RHS->getValue()) == RHS->getValue()) { 515 Instruction *Or = 516 BinaryOperator::CreateOr(I->getOperand(0), I->getOperand(1), 517 I->getName()); 518 return InsertNewInstBefore(Or, *I); 519 } 520 521 // We can say something about the output known-zero and known-one bits, 522 // depending on potential carries from the input constant and the 523 // unknowns. For example if the LHS is known to have at most the 0x0F0F0 524 // bits set and the RHS constant is 0x01001, then we know we have a known 525 // one mask of 0x00001 and a known zero mask of 0xE0F0E. 526 527 // To compute this, we first compute the potential carry bits. These are 528 // the bits which may be modified. I'm not aware of a better way to do 529 // this scan. 530 const APInt &RHSVal = RHS->getValue(); 531 APInt CarryBits((~LHSKnownZero + RHSVal) ^ (~LHSKnownZero ^ RHSVal)); 532 533 // Now that we know which bits have carries, compute the known-1/0 sets. 534 535 // Bits are known one if they are known zero in one operand and one in the 536 // other, and there is no input carry. 537 KnownOne = ((LHSKnownZero & RHSVal) | 538 (LHSKnownOne & ~RHSVal)) & ~CarryBits; 539 540 // Bits are known zero if they are known zero in both operands and there 541 // is no input carry. 542 KnownZero = LHSKnownZero & ~RHSVal & ~CarryBits; 543 } else { 544 // If the high-bits of this ADD are not demanded, then it does not demand 545 // the high bits of its LHS or RHS. 546 if (DemandedMask[BitWidth-1] == 0) { 547 // Right fill the mask of bits for this ADD to demand the most 548 // significant bit and all those below it. 549 APInt DemandedFromOps(APInt::getLowBitsSet(BitWidth, BitWidth-NLZ)); 550 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedFromOps, 551 LHSKnownZero, LHSKnownOne, Depth+1) || 552 SimplifyDemandedBits(I->getOperandUse(1), DemandedFromOps, 553 LHSKnownZero, LHSKnownOne, Depth+1)) 554 return I; 555 } 556 } 557 break; 558 } 559 case Instruction::Sub: 560 // If the high-bits of this SUB are not demanded, then it does not demand 561 // the high bits of its LHS or RHS. 562 if (DemandedMask[BitWidth-1] == 0) { 563 // Right fill the mask of bits for this SUB to demand the most 564 // significant bit and all those below it. 565 uint32_t NLZ = DemandedMask.countLeadingZeros(); 566 APInt DemandedFromOps(APInt::getLowBitsSet(BitWidth, BitWidth-NLZ)); 567 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedFromOps, 568 LHSKnownZero, LHSKnownOne, Depth+1) || 569 SimplifyDemandedBits(I->getOperandUse(1), DemandedFromOps, 570 LHSKnownZero, LHSKnownOne, Depth+1)) 571 return I; 572 } 573 // Otherwise just hand the sub off to ComputeMaskedBits to fill in 574 // the known zeros and ones. 575 ComputeMaskedBits(V, DemandedMask, KnownZero, KnownOne, Depth); 576 break; 577 case Instruction::Shl: 578 if (ConstantInt *SA = dyn_cast<ConstantInt>(I->getOperand(1))) { 579 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1); 580 APInt DemandedMaskIn(DemandedMask.lshr(ShiftAmt)); 581 582 // If the shift is NUW/NSW, then it does demand the high bits. 583 ShlOperator *IOp = cast<ShlOperator>(I); 584 if (IOp->hasNoSignedWrap()) 585 DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt+1); 586 else if (IOp->hasNoUnsignedWrap()) 587 DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt); 588 589 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMaskIn, 590 KnownZero, KnownOne, Depth+1)) 591 return I; 592 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?"); 593 KnownZero <<= ShiftAmt; 594 KnownOne <<= ShiftAmt; 595 // low bits known zero. 596 if (ShiftAmt) 597 KnownZero |= APInt::getLowBitsSet(BitWidth, ShiftAmt); 598 } 599 break; 600 case Instruction::LShr: 601 // For a logical shift right 602 if (ConstantInt *SA = dyn_cast<ConstantInt>(I->getOperand(1))) { 603 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1); 604 605 // Unsigned shift right. 606 APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt)); 607 608 // If the shift is exact, then it does demand the low bits (and knows that 609 // they are zero). 610 if (cast<LShrOperator>(I)->isExact()) 611 DemandedMaskIn |= APInt::getLowBitsSet(BitWidth, ShiftAmt); 612 613 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMaskIn, 614 KnownZero, KnownOne, Depth+1)) 615 return I; 616 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?"); 617 KnownZero = APIntOps::lshr(KnownZero, ShiftAmt); 618 KnownOne = APIntOps::lshr(KnownOne, ShiftAmt); 619 if (ShiftAmt) { 620 // Compute the new bits that are at the top now. 621 APInt HighBits(APInt::getHighBitsSet(BitWidth, ShiftAmt)); 622 KnownZero |= HighBits; // high bits known zero. 623 } 624 } 625 break; 626 case Instruction::AShr: 627 // If this is an arithmetic shift right and only the low-bit is set, we can 628 // always convert this into a logical shr, even if the shift amount is 629 // variable. The low bit of the shift cannot be an input sign bit unless 630 // the shift amount is >= the size of the datatype, which is undefined. 631 if (DemandedMask == 1) { 632 // Perform the logical shift right. 633 Instruction *NewVal = BinaryOperator::CreateLShr( 634 I->getOperand(0), I->getOperand(1), I->getName()); 635 return InsertNewInstBefore(NewVal, *I); 636 } 637 638 // If the sign bit is the only bit demanded by this ashr, then there is no 639 // need to do it, the shift doesn't change the high bit. 640 if (DemandedMask.isSignBit()) 641 return I->getOperand(0); 642 643 if (ConstantInt *SA = dyn_cast<ConstantInt>(I->getOperand(1))) { 644 uint32_t ShiftAmt = SA->getLimitedValue(BitWidth-1); 645 646 // Signed shift right. 647 APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt)); 648 // If any of the "high bits" are demanded, we should set the sign bit as 649 // demanded. 650 if (DemandedMask.countLeadingZeros() <= ShiftAmt) 651 DemandedMaskIn.setBit(BitWidth-1); 652 653 // If the shift is exact, then it does demand the low bits (and knows that 654 // they are zero). 655 if (cast<AShrOperator>(I)->isExact()) 656 DemandedMaskIn |= APInt::getLowBitsSet(BitWidth, ShiftAmt); 657 658 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMaskIn, 659 KnownZero, KnownOne, Depth+1)) 660 return I; 661 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?"); 662 // Compute the new bits that are at the top now. 663 APInt HighBits(APInt::getHighBitsSet(BitWidth, ShiftAmt)); 664 KnownZero = APIntOps::lshr(KnownZero, ShiftAmt); 665 KnownOne = APIntOps::lshr(KnownOne, ShiftAmt); 666 667 // Handle the sign bits. 668 APInt SignBit(APInt::getSignBit(BitWidth)); 669 // Adjust to where it is now in the mask. 670 SignBit = APIntOps::lshr(SignBit, ShiftAmt); 671 672 // If the input sign bit is known to be zero, or if none of the top bits 673 // are demanded, turn this into an unsigned shift right. 674 if (BitWidth <= ShiftAmt || KnownZero[BitWidth-ShiftAmt-1] || 675 (HighBits & ~DemandedMask) == HighBits) { 676 // Perform the logical shift right. 677 Instruction *NewVal = BinaryOperator::CreateLShr( 678 I->getOperand(0), SA, I->getName()); 679 return InsertNewInstBefore(NewVal, *I); 680 } else if ((KnownOne & SignBit) != 0) { // New bits are known one. 681 KnownOne |= HighBits; 682 } 683 } 684 break; 685 case Instruction::SRem: 686 if (ConstantInt *Rem = dyn_cast<ConstantInt>(I->getOperand(1))) { 687 APInt RA = Rem->getValue().abs(); 688 if (RA.isPowerOf2()) { 689 if (DemandedMask.ult(RA)) // srem won't affect demanded bits 690 return I->getOperand(0); 691 692 APInt LowBits = RA - 1; 693 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth); 694 if (SimplifyDemandedBits(I->getOperandUse(0), Mask2, 695 LHSKnownZero, LHSKnownOne, Depth+1)) 696 return I; 697 698 // The low bits of LHS are unchanged by the srem. 699 KnownZero = LHSKnownZero & LowBits; 700 KnownOne = LHSKnownOne & LowBits; 701 702 // If LHS is non-negative or has all low bits zero, then the upper bits 703 // are all zero. 704 if (LHSKnownZero[BitWidth-1] || ((LHSKnownZero & LowBits) == LowBits)) 705 KnownZero |= ~LowBits; 706 707 // If LHS is negative and not all low bits are zero, then the upper bits 708 // are all one. 709 if (LHSKnownOne[BitWidth-1] && ((LHSKnownOne & LowBits) != 0)) 710 KnownOne |= ~LowBits; 711 712 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?"); 713 } 714 } 715 break; 716 case Instruction::URem: { 717 APInt KnownZero2(BitWidth, 0), KnownOne2(BitWidth, 0); 718 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 719 if (SimplifyDemandedBits(I->getOperandUse(0), AllOnes, 720 KnownZero2, KnownOne2, Depth+1) || 721 SimplifyDemandedBits(I->getOperandUse(1), AllOnes, 722 KnownZero2, KnownOne2, Depth+1)) 723 return I; 724 725 unsigned Leaders = KnownZero2.countLeadingOnes(); 726 Leaders = std::max(Leaders, 727 KnownZero2.countLeadingOnes()); 728 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & DemandedMask; 729 break; 730 } 731 case Instruction::Call: 732 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) { 733 switch (II->getIntrinsicID()) { 734 default: break; 735 case Intrinsic::bswap: { 736 // If the only bits demanded come from one byte of the bswap result, 737 // just shift the input byte into position to eliminate the bswap. 738 unsigned NLZ = DemandedMask.countLeadingZeros(); 739 unsigned NTZ = DemandedMask.countTrailingZeros(); 740 741 // Round NTZ down to the next byte. If we have 11 trailing zeros, then 742 // we need all the bits down to bit 8. Likewise, round NLZ. If we 743 // have 14 leading zeros, round to 8. 744 NLZ &= ~7; 745 NTZ &= ~7; 746 // If we need exactly one byte, we can do this transformation. 747 if (BitWidth-NLZ-NTZ == 8) { 748 unsigned ResultBit = NTZ; 749 unsigned InputBit = BitWidth-NTZ-8; 750 751 // Replace this with either a left or right shift to get the byte into 752 // the right place. 753 Instruction *NewVal; 754 if (InputBit > ResultBit) 755 NewVal = BinaryOperator::CreateLShr(II->getArgOperand(0), 756 ConstantInt::get(I->getType(), InputBit-ResultBit)); 757 else 758 NewVal = BinaryOperator::CreateShl(II->getArgOperand(0), 759 ConstantInt::get(I->getType(), ResultBit-InputBit)); 760 NewVal->takeName(I); 761 return InsertNewInstBefore(NewVal, *I); 762 } 763 764 // TODO: Could compute known zero/one bits based on the input. 765 break; 766 } 767 } 768 } 769 ComputeMaskedBits(V, DemandedMask, KnownZero, KnownOne, Depth); 770 break; 771 } 772 773 // If the client is only demanding bits that we know, return the known 774 // constant. 775 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) 776 return Constant::getIntegerValue(VTy, KnownOne); 777 return 0; 778} 779 780 781/// SimplifyDemandedVectorElts - The specified value produces a vector with 782/// any number of elements. DemandedElts contains the set of elements that are 783/// actually used by the caller. This method analyzes which elements of the 784/// operand are undef and returns that information in UndefElts. 785/// 786/// If the information about demanded elements can be used to simplify the 787/// operation, the operation is simplified, then the resultant value is 788/// returned. This returns null if no change was made. 789Value *InstCombiner::SimplifyDemandedVectorElts(Value *V, APInt DemandedElts, 790 APInt &UndefElts, 791 unsigned Depth) { 792 unsigned VWidth = cast<VectorType>(V->getType())->getNumElements(); 793 APInt EltMask(APInt::getAllOnesValue(VWidth)); 794 assert((DemandedElts & ~EltMask) == 0 && "Invalid DemandedElts!"); 795 796 if (isa<UndefValue>(V)) { 797 // If the entire vector is undefined, just return this info. 798 UndefElts = EltMask; 799 return 0; 800 } 801 802 if (DemandedElts == 0) { // If nothing is demanded, provide undef. 803 UndefElts = EltMask; 804 return UndefValue::get(V->getType()); 805 } 806 807 UndefElts = 0; 808 if (ConstantVector *CV = dyn_cast<ConstantVector>(V)) { 809 const Type *EltTy = cast<VectorType>(V->getType())->getElementType(); 810 Constant *Undef = UndefValue::get(EltTy); 811 812 std::vector<Constant*> Elts; 813 for (unsigned i = 0; i != VWidth; ++i) 814 if (!DemandedElts[i]) { // If not demanded, set to undef. 815 Elts.push_back(Undef); 816 UndefElts.setBit(i); 817 } else if (isa<UndefValue>(CV->getOperand(i))) { // Already undef. 818 Elts.push_back(Undef); 819 UndefElts.setBit(i); 820 } else { // Otherwise, defined. 821 Elts.push_back(CV->getOperand(i)); 822 } 823 824 // If we changed the constant, return it. 825 Constant *NewCP = ConstantVector::get(Elts); 826 return NewCP != CV ? NewCP : 0; 827 } 828 829 if (isa<ConstantAggregateZero>(V)) { 830 // Simplify the CAZ to a ConstantVector where the non-demanded elements are 831 // set to undef. 832 833 // Check if this is identity. If so, return 0 since we are not simplifying 834 // anything. 835 if (DemandedElts.isAllOnesValue()) 836 return 0; 837 838 const Type *EltTy = cast<VectorType>(V->getType())->getElementType(); 839 Constant *Zero = Constant::getNullValue(EltTy); 840 Constant *Undef = UndefValue::get(EltTy); 841 std::vector<Constant*> Elts; 842 for (unsigned i = 0; i != VWidth; ++i) { 843 Constant *Elt = DemandedElts[i] ? Zero : Undef; 844 Elts.push_back(Elt); 845 } 846 UndefElts = DemandedElts ^ EltMask; 847 return ConstantVector::get(Elts); 848 } 849 850 // Limit search depth. 851 if (Depth == 10) 852 return 0; 853 854 // If multiple users are using the root value, procede with 855 // simplification conservatively assuming that all elements 856 // are needed. 857 if (!V->hasOneUse()) { 858 // Quit if we find multiple users of a non-root value though. 859 // They'll be handled when it's their turn to be visited by 860 // the main instcombine process. 861 if (Depth != 0) 862 // TODO: Just compute the UndefElts information recursively. 863 return 0; 864 865 // Conservatively assume that all elements are needed. 866 DemandedElts = EltMask; 867 } 868 869 Instruction *I = dyn_cast<Instruction>(V); 870 if (!I) return 0; // Only analyze instructions. 871 872 bool MadeChange = false; 873 APInt UndefElts2(VWidth, 0); 874 Value *TmpV; 875 switch (I->getOpcode()) { 876 default: break; 877 878 case Instruction::InsertElement: { 879 // If this is a variable index, we don't know which element it overwrites. 880 // demand exactly the same input as we produce. 881 ConstantInt *Idx = dyn_cast<ConstantInt>(I->getOperand(2)); 882 if (Idx == 0) { 883 // Note that we can't propagate undef elt info, because we don't know 884 // which elt is getting updated. 885 TmpV = SimplifyDemandedVectorElts(I->getOperand(0), DemandedElts, 886 UndefElts2, Depth+1); 887 if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; } 888 break; 889 } 890 891 // If this is inserting an element that isn't demanded, remove this 892 // insertelement. 893 unsigned IdxNo = Idx->getZExtValue(); 894 if (IdxNo >= VWidth || !DemandedElts[IdxNo]) { 895 Worklist.Add(I); 896 return I->getOperand(0); 897 } 898 899 // Otherwise, the element inserted overwrites whatever was there, so the 900 // input demanded set is simpler than the output set. 901 APInt DemandedElts2 = DemandedElts; 902 DemandedElts2.clearBit(IdxNo); 903 TmpV = SimplifyDemandedVectorElts(I->getOperand(0), DemandedElts2, 904 UndefElts, Depth+1); 905 if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; } 906 907 // The inserted element is defined. 908 UndefElts.clearBit(IdxNo); 909 break; 910 } 911 case Instruction::ShuffleVector: { 912 ShuffleVectorInst *Shuffle = cast<ShuffleVectorInst>(I); 913 uint64_t LHSVWidth = 914 cast<VectorType>(Shuffle->getOperand(0)->getType())->getNumElements(); 915 APInt LeftDemanded(LHSVWidth, 0), RightDemanded(LHSVWidth, 0); 916 for (unsigned i = 0; i < VWidth; i++) { 917 if (DemandedElts[i]) { 918 unsigned MaskVal = Shuffle->getMaskValue(i); 919 if (MaskVal != -1u) { 920 assert(MaskVal < LHSVWidth * 2 && 921 "shufflevector mask index out of range!"); 922 if (MaskVal < LHSVWidth) 923 LeftDemanded.setBit(MaskVal); 924 else 925 RightDemanded.setBit(MaskVal - LHSVWidth); 926 } 927 } 928 } 929 930 APInt UndefElts4(LHSVWidth, 0); 931 TmpV = SimplifyDemandedVectorElts(I->getOperand(0), LeftDemanded, 932 UndefElts4, Depth+1); 933 if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; } 934 935 APInt UndefElts3(LHSVWidth, 0); 936 TmpV = SimplifyDemandedVectorElts(I->getOperand(1), RightDemanded, 937 UndefElts3, Depth+1); 938 if (TmpV) { I->setOperand(1, TmpV); MadeChange = true; } 939 940 bool NewUndefElts = false; 941 for (unsigned i = 0; i < VWidth; i++) { 942 unsigned MaskVal = Shuffle->getMaskValue(i); 943 if (MaskVal == -1u) { 944 UndefElts.setBit(i); 945 } else if (MaskVal < LHSVWidth) { 946 if (UndefElts4[MaskVal]) { 947 NewUndefElts = true; 948 UndefElts.setBit(i); 949 } 950 } else { 951 if (UndefElts3[MaskVal - LHSVWidth]) { 952 NewUndefElts = true; 953 UndefElts.setBit(i); 954 } 955 } 956 } 957 958 if (NewUndefElts) { 959 // Add additional discovered undefs. 960 std::vector<Constant*> Elts; 961 for (unsigned i = 0; i < VWidth; ++i) { 962 if (UndefElts[i]) 963 Elts.push_back(UndefValue::get(Type::getInt32Ty(I->getContext()))); 964 else 965 Elts.push_back(ConstantInt::get(Type::getInt32Ty(I->getContext()), 966 Shuffle->getMaskValue(i))); 967 } 968 I->setOperand(2, ConstantVector::get(Elts)); 969 MadeChange = true; 970 } 971 break; 972 } 973 case Instruction::BitCast: { 974 // Vector->vector casts only. 975 const VectorType *VTy = dyn_cast<VectorType>(I->getOperand(0)->getType()); 976 if (!VTy) break; 977 unsigned InVWidth = VTy->getNumElements(); 978 APInt InputDemandedElts(InVWidth, 0); 979 unsigned Ratio; 980 981 if (VWidth == InVWidth) { 982 // If we are converting from <4 x i32> -> <4 x f32>, we demand the same 983 // elements as are demanded of us. 984 Ratio = 1; 985 InputDemandedElts = DemandedElts; 986 } else if (VWidth > InVWidth) { 987 // Untested so far. 988 break; 989 990 // If there are more elements in the result than there are in the source, 991 // then an input element is live if any of the corresponding output 992 // elements are live. 993 Ratio = VWidth/InVWidth; 994 for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx) { 995 if (DemandedElts[OutIdx]) 996 InputDemandedElts.setBit(OutIdx/Ratio); 997 } 998 } else { 999 // Untested so far. 1000 break; 1001 1002 // If there are more elements in the source than there are in the result, 1003 // then an input element is live if the corresponding output element is 1004 // live. 1005 Ratio = InVWidth/VWidth; 1006 for (unsigned InIdx = 0; InIdx != InVWidth; ++InIdx) 1007 if (DemandedElts[InIdx/Ratio]) 1008 InputDemandedElts.setBit(InIdx); 1009 } 1010 1011 // div/rem demand all inputs, because they don't want divide by zero. 1012 TmpV = SimplifyDemandedVectorElts(I->getOperand(0), InputDemandedElts, 1013 UndefElts2, Depth+1); 1014 if (TmpV) { 1015 I->setOperand(0, TmpV); 1016 MadeChange = true; 1017 } 1018 1019 UndefElts = UndefElts2; 1020 if (VWidth > InVWidth) { 1021 llvm_unreachable("Unimp"); 1022 // If there are more elements in the result than there are in the source, 1023 // then an output element is undef if the corresponding input element is 1024 // undef. 1025 for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx) 1026 if (UndefElts2[OutIdx/Ratio]) 1027 UndefElts.setBit(OutIdx); 1028 } else if (VWidth < InVWidth) { 1029 llvm_unreachable("Unimp"); 1030 // If there are more elements in the source than there are in the result, 1031 // then a result element is undef if all of the corresponding input 1032 // elements are undef. 1033 UndefElts = ~0ULL >> (64-VWidth); // Start out all undef. 1034 for (unsigned InIdx = 0; InIdx != InVWidth; ++InIdx) 1035 if (!UndefElts2[InIdx]) // Not undef? 1036 UndefElts.clearBit(InIdx/Ratio); // Clear undef bit. 1037 } 1038 break; 1039 } 1040 case Instruction::And: 1041 case Instruction::Or: 1042 case Instruction::Xor: 1043 case Instruction::Add: 1044 case Instruction::Sub: 1045 case Instruction::Mul: 1046 // div/rem demand all inputs, because they don't want divide by zero. 1047 TmpV = SimplifyDemandedVectorElts(I->getOperand(0), DemandedElts, 1048 UndefElts, Depth+1); 1049 if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; } 1050 TmpV = SimplifyDemandedVectorElts(I->getOperand(1), DemandedElts, 1051 UndefElts2, Depth+1); 1052 if (TmpV) { I->setOperand(1, TmpV); MadeChange = true; } 1053 1054 // Output elements are undefined if both are undefined. Consider things 1055 // like undef&0. The result is known zero, not undef. 1056 UndefElts &= UndefElts2; 1057 break; 1058 1059 case Instruction::Call: { 1060 IntrinsicInst *II = dyn_cast<IntrinsicInst>(I); 1061 if (!II) break; 1062 switch (II->getIntrinsicID()) { 1063 default: break; 1064 1065 // Binary vector operations that work column-wise. A dest element is a 1066 // function of the corresponding input elements from the two inputs. 1067 case Intrinsic::x86_sse_sub_ss: 1068 case Intrinsic::x86_sse_mul_ss: 1069 case Intrinsic::x86_sse_min_ss: 1070 case Intrinsic::x86_sse_max_ss: 1071 case Intrinsic::x86_sse2_sub_sd: 1072 case Intrinsic::x86_sse2_mul_sd: 1073 case Intrinsic::x86_sse2_min_sd: 1074 case Intrinsic::x86_sse2_max_sd: 1075 TmpV = SimplifyDemandedVectorElts(II->getArgOperand(0), DemandedElts, 1076 UndefElts, Depth+1); 1077 if (TmpV) { II->setArgOperand(0, TmpV); MadeChange = true; } 1078 TmpV = SimplifyDemandedVectorElts(II->getArgOperand(1), DemandedElts, 1079 UndefElts2, Depth+1); 1080 if (TmpV) { II->setArgOperand(1, TmpV); MadeChange = true; } 1081 1082 // If only the low elt is demanded and this is a scalarizable intrinsic, 1083 // scalarize it now. 1084 if (DemandedElts == 1) { 1085 switch (II->getIntrinsicID()) { 1086 default: break; 1087 case Intrinsic::x86_sse_sub_ss: 1088 case Intrinsic::x86_sse_mul_ss: 1089 case Intrinsic::x86_sse2_sub_sd: 1090 case Intrinsic::x86_sse2_mul_sd: 1091 // TODO: Lower MIN/MAX/ABS/etc 1092 Value *LHS = II->getArgOperand(0); 1093 Value *RHS = II->getArgOperand(1); 1094 // Extract the element as scalars. 1095 LHS = InsertNewInstBefore(ExtractElementInst::Create(LHS, 1096 ConstantInt::get(Type::getInt32Ty(I->getContext()), 0U)), *II); 1097 RHS = InsertNewInstBefore(ExtractElementInst::Create(RHS, 1098 ConstantInt::get(Type::getInt32Ty(I->getContext()), 0U)), *II); 1099 1100 switch (II->getIntrinsicID()) { 1101 default: llvm_unreachable("Case stmts out of sync!"); 1102 case Intrinsic::x86_sse_sub_ss: 1103 case Intrinsic::x86_sse2_sub_sd: 1104 TmpV = InsertNewInstBefore(BinaryOperator::CreateFSub(LHS, RHS, 1105 II->getName()), *II); 1106 break; 1107 case Intrinsic::x86_sse_mul_ss: 1108 case Intrinsic::x86_sse2_mul_sd: 1109 TmpV = InsertNewInstBefore(BinaryOperator::CreateFMul(LHS, RHS, 1110 II->getName()), *II); 1111 break; 1112 } 1113 1114 Instruction *New = 1115 InsertElementInst::Create( 1116 UndefValue::get(II->getType()), TmpV, 1117 ConstantInt::get(Type::getInt32Ty(I->getContext()), 0U, false), 1118 II->getName()); 1119 InsertNewInstBefore(New, *II); 1120 return New; 1121 } 1122 } 1123 1124 // Output elements are undefined if both are undefined. Consider things 1125 // like undef&0. The result is known zero, not undef. 1126 UndefElts &= UndefElts2; 1127 break; 1128 } 1129 break; 1130 } 1131 } 1132 return MadeChange ? I : 0; 1133} 1134