XCoreRegisterInfo.cpp revision 218893 
1//===- XCoreRegisterInfo.cpp - XCore Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the XCore implementation of the MRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "XCoreRegisterInfo.h"
15#include "XCoreMachineFunctionInfo.h"
16#include "XCore.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "llvm/CodeGen/MachineFunction.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineLocation.h"
21#include "llvm/CodeGen/MachineModuleInfo.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/CodeGen/RegisterScavenging.h"
24#include "llvm/Target/TargetFrameLowering.h"
25#include "llvm/Target/TargetMachine.h"
26#include "llvm/Target/TargetOptions.h"
27#include "llvm/Target/TargetInstrInfo.h"
28#include "llvm/Type.h"
29#include "llvm/Function.h"
30#include "llvm/ADT/BitVector.h"
31#include "llvm/ADT/STLExtras.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35
36using namespace llvm;
37
38XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
39  : XCoreGenRegisterInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
40    TII(tii) {
41}
42
43// helper functions
44static inline bool isImmUs(unsigned val) {
45  return val <= 11;
46}
47
48static inline bool isImmU6(unsigned val) {
49  return val < (1 << 6);
50}
51
52static inline bool isImmU16(unsigned val) {
53  return val < (1 << 16);
54}
55
56static const unsigned XCore_ArgRegs[] = {
57  XCore::R0, XCore::R1, XCore::R2, XCore::R3
58};
59
60const unsigned * XCoreRegisterInfo::getArgRegs(const MachineFunction *MF)
61{
62  return XCore_ArgRegs;
63}
64
65unsigned XCoreRegisterInfo::getNumArgRegs(const MachineFunction *MF)
66{
67  return array_lengthof(XCore_ArgRegs);
68}
69
70bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF) {
71  return MF.getMMI().hasDebugInfo() || !MF.getFunction()->doesNotThrow() ||
72          UnwindTablesMandatory;
73}
74
75const unsigned* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
76                                                                         const {
77  static const unsigned CalleeSavedRegs[] = {
78    XCore::R4, XCore::R5, XCore::R6, XCore::R7,
79    XCore::R8, XCore::R9, XCore::R10, XCore::LR,
80    0
81  };
82  return CalleeSavedRegs;
83}
84
85BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
86  BitVector Reserved(getNumRegs());
87  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
88
89  Reserved.set(XCore::CP);
90  Reserved.set(XCore::DP);
91  Reserved.set(XCore::SP);
92  Reserved.set(XCore::LR);
93  if (TFI->hasFP(MF)) {
94    Reserved.set(XCore::R10);
95  }
96  return Reserved;
97}
98
99bool
100XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
101  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
102
103  // TODO can we estimate stack size?
104  return TFI->hasFP(MF);
105}
106
107// This function eliminates ADJCALLSTACKDOWN,
108// ADJCALLSTACKUP pseudo instructions
109void XCoreRegisterInfo::
110eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
111                              MachineBasicBlock::iterator I) const {
112  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
113
114  if (!TFI->hasReservedCallFrame(MF)) {
115    // Turn the adjcallstackdown instruction into 'extsp <amt>' and the
116    // adjcallstackup instruction into 'ldaw sp, sp[<amt>]'
117    MachineInstr *Old = I;
118    uint64_t Amount = Old->getOperand(0).getImm();
119    if (Amount != 0) {
120      // We need to keep the stack aligned properly.  To do this, we round the
121      // amount of space needed for the outgoing arguments up to the next
122      // alignment boundary.
123      unsigned Align = TFI->getStackAlignment();
124      Amount = (Amount+Align-1)/Align*Align;
125
126      assert(Amount%4 == 0);
127      Amount /= 4;
128
129      bool isU6 = isImmU6(Amount);
130      if (!isU6 && !isImmU16(Amount)) {
131        // FIX could emit multiple instructions in this case.
132#ifndef NDEBUG
133        errs() << "eliminateCallFramePseudoInstr size too big: "
134               << Amount << "\n";
135#endif
136        llvm_unreachable(0);
137      }
138
139      MachineInstr *New;
140      if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) {
141        int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
142        New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
143          .addImm(Amount);
144      } else {
145        assert(Old->getOpcode() == XCore::ADJCALLSTACKUP);
146        int Opcode = isU6 ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
147        New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
148          .addImm(Amount);
149      }
150
151      // Replace the pseudo instruction with a new instruction...
152      MBB.insert(I, New);
153    }
154  }
155
156  MBB.erase(I);
157}
158
159void
160XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
161                                       int SPAdj, RegScavenger *RS) const {
162  assert(SPAdj == 0 && "Unexpected");
163  MachineInstr &MI = *II;
164  DebugLoc dl = MI.getDebugLoc();
165  unsigned i = 0;
166
167  while (!MI.getOperand(i).isFI()) {
168    ++i;
169    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
170  }
171
172  MachineOperand &FrameOp = MI.getOperand(i);
173  int FrameIndex = FrameOp.getIndex();
174
175  MachineFunction &MF = *MI.getParent()->getParent();
176  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
177  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
178  int StackSize = MF.getFrameInfo()->getStackSize();
179
180  #ifndef NDEBUG
181  DEBUG(errs() << "\nFunction         : "
182        << MF.getFunction()->getName() << "\n");
183  DEBUG(errs() << "<--------->\n");
184  DEBUG(MI.print(errs()));
185  DEBUG(errs() << "FrameIndex         : " << FrameIndex << "\n");
186  DEBUG(errs() << "FrameOffset        : " << Offset << "\n");
187  DEBUG(errs() << "StackSize          : " << StackSize << "\n");
188  #endif
189
190  Offset += StackSize;
191
192  // fold constant into offset.
193  Offset += MI.getOperand(i + 1).getImm();
194  MI.getOperand(i + 1).ChangeToImmediate(0);
195
196  assert(Offset%4 == 0 && "Misaligned stack offset");
197
198  DEBUG(errs() << "Offset             : " << Offset << "\n" << "<--------->\n");
199
200  Offset/=4;
201
202  bool FP = TFI->hasFP(MF);
203
204  unsigned Reg = MI.getOperand(0).getReg();
205  bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill();
206
207  assert(XCore::GRRegsRegisterClass->contains(Reg) &&
208         "Unexpected register operand");
209
210  MachineBasicBlock &MBB = *MI.getParent();
211
212  if (FP) {
213    bool isUs = isImmUs(Offset);
214    unsigned FramePtr = XCore::R10;
215
216    if (!isUs) {
217      if (!RS)
218        report_fatal_error("eliminateFrameIndex Frame size too big: " +
219                           Twine(Offset));
220      unsigned ScratchReg = RS->scavengeRegister(XCore::GRRegsRegisterClass, II,
221                                                 SPAdj);
222      loadConstant(MBB, II, ScratchReg, Offset, dl);
223      switch (MI.getOpcode()) {
224      case XCore::LDWFI:
225        BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
226              .addReg(FramePtr)
227              .addReg(ScratchReg, RegState::Kill);
228        break;
229      case XCore::STWFI:
230        BuildMI(MBB, II, dl, TII.get(XCore::STW_3r))
231              .addReg(Reg, getKillRegState(isKill))
232              .addReg(FramePtr)
233              .addReg(ScratchReg, RegState::Kill);
234        break;
235      case XCore::LDAWFI:
236        BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
237              .addReg(FramePtr)
238              .addReg(ScratchReg, RegState::Kill);
239        break;
240      default:
241        llvm_unreachable("Unexpected Opcode");
242      }
243    } else {
244      switch (MI.getOpcode()) {
245      case XCore::LDWFI:
246        BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
247              .addReg(FramePtr)
248              .addImm(Offset);
249        break;
250      case XCore::STWFI:
251        BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
252              .addReg(Reg, getKillRegState(isKill))
253              .addReg(FramePtr)
254              .addImm(Offset);
255        break;
256      case XCore::LDAWFI:
257        BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
258              .addReg(FramePtr)
259              .addImm(Offset);
260        break;
261      default:
262        llvm_unreachable("Unexpected Opcode");
263      }
264    }
265  } else {
266    bool isU6 = isImmU6(Offset);
267    if (!isU6 && !isImmU16(Offset))
268      report_fatal_error("eliminateFrameIndex Frame size too big: " +
269                         Twine(Offset));
270
271    switch (MI.getOpcode()) {
272    int NewOpcode;
273    case XCore::LDWFI:
274      NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
275      BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
276            .addImm(Offset);
277      break;
278    case XCore::STWFI:
279      NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
280      BuildMI(MBB, II, dl, TII.get(NewOpcode))
281            .addReg(Reg, getKillRegState(isKill))
282            .addImm(Offset);
283      break;
284    case XCore::LDAWFI:
285      NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
286      BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
287            .addImm(Offset);
288      break;
289    default:
290      llvm_unreachable("Unexpected Opcode");
291    }
292  }
293  // Erase old instruction.
294  MBB.erase(II);
295}
296
297void XCoreRegisterInfo::
298loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
299            unsigned DstReg, int64_t Value, DebugLoc dl) const {
300  // TODO use mkmsk if possible.
301  if (!isImmU16(Value)) {
302    // TODO use constant pool.
303    report_fatal_error("loadConstant value too big " + Twine(Value));
304  }
305  int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
306  BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
307}
308
309int XCoreRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
310  return XCoreGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
311}
312
313unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
314  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
315
316  return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;
317}
318
319unsigned XCoreRegisterInfo::getRARegister() const {
320  return XCore::LR;
321}
322
323#include "XCoreGenRegisterInfo.inc"
324
325