XCoreInstrInfo.td revision 251662
1//===-- XCoreInstrInfo.td - Target Description for XCore ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the XCore instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14// Uses of CP, DP are not currently reflected in the patterns, since 15// having a physical register as an operand prevents loop hoisting and 16// since the value of these registers never changes during the life of the 17// function. 18 19//===----------------------------------------------------------------------===// 20// Instruction format superclass. 21//===----------------------------------------------------------------------===// 22 23include "XCoreInstrFormats.td" 24 25//===----------------------------------------------------------------------===// 26// XCore specific DAG Nodes. 27// 28 29// Call 30def SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 31def XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink, 32 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 33 SDNPVariadic]>; 34 35def XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTBrind, 36 [SDNPHasChain, SDNPOptInGlue, SDNPMayLoad, SDNPVariadic]>; 37 38def SDT_XCoreBR_JT : SDTypeProfile<0, 2, 39 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 40 41def XCoreBR_JT : SDNode<"XCoreISD::BR_JT", SDT_XCoreBR_JT, 42 [SDNPHasChain]>; 43 44def XCoreBR_JT32 : SDNode<"XCoreISD::BR_JT32", SDT_XCoreBR_JT, 45 [SDNPHasChain]>; 46 47def SDT_XCoreAddress : SDTypeProfile<1, 1, 48 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 49 50def pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress, 51 []>; 52 53def dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress, 54 []>; 55 56def cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress, 57 []>; 58 59def SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>; 60def XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp, 61 [SDNPHasChain, SDNPMayStore]>; 62 63// These are target-independent nodes, but have target-specific formats. 64def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 65def SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 66 SDTCisVT<1, i32> ]>; 67 68def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart, 69 [SDNPHasChain, SDNPOutGlue]>; 70def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XCoreCallSeqEnd, 71 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 72 73//===----------------------------------------------------------------------===// 74// Instruction Pattern Stuff 75//===----------------------------------------------------------------------===// 76 77def div4_xform : SDNodeXForm<imm, [{ 78 // Transformation function: imm/4 79 assert(N->getZExtValue() % 4 == 0); 80 return getI32Imm(N->getZExtValue()/4); 81}]>; 82 83def msksize_xform : SDNodeXForm<imm, [{ 84 // Transformation function: get the size of a mask 85 assert(isMask_32(N->getZExtValue())); 86 // look for the first non-zero bit 87 return getI32Imm(32 - CountLeadingZeros_32(N->getZExtValue())); 88}]>; 89 90def neg_xform : SDNodeXForm<imm, [{ 91 // Transformation function: -imm 92 uint32_t value = N->getZExtValue(); 93 return getI32Imm(-value); 94}]>; 95 96def bpwsub_xform : SDNodeXForm<imm, [{ 97 // Transformation function: 32-imm 98 uint32_t value = N->getZExtValue(); 99 return getI32Imm(32-value); 100}]>; 101 102def div4neg_xform : SDNodeXForm<imm, [{ 103 // Transformation function: -imm/4 104 uint32_t value = N->getZExtValue(); 105 assert(-value % 4 == 0); 106 return getI32Imm(-value/4); 107}]>; 108 109def immUs4Neg : PatLeaf<(imm), [{ 110 uint32_t value = (uint32_t)N->getZExtValue(); 111 return (-value)%4 == 0 && (-value)/4 <= 11; 112}]>; 113 114def immUs4 : PatLeaf<(imm), [{ 115 uint32_t value = (uint32_t)N->getZExtValue(); 116 return value%4 == 0 && value/4 <= 11; 117}]>; 118 119def immUsNeg : PatLeaf<(imm), [{ 120 return -((uint32_t)N->getZExtValue()) <= 11; 121}]>; 122 123def immUs : PatLeaf<(imm), [{ 124 return (uint32_t)N->getZExtValue() <= 11; 125}]>; 126 127def immU6 : PatLeaf<(imm), [{ 128 return (uint32_t)N->getZExtValue() < (1 << 6); 129}]>; 130 131def immU10 : PatLeaf<(imm), [{ 132 return (uint32_t)N->getZExtValue() < (1 << 10); 133}]>; 134 135def immU16 : PatLeaf<(imm), [{ 136 return (uint32_t)N->getZExtValue() < (1 << 16); 137}]>; 138 139def immU20 : PatLeaf<(imm), [{ 140 return (uint32_t)N->getZExtValue() < (1 << 20); 141}]>; 142 143def immMskBitp : PatLeaf<(imm), [{ return immMskBitp(N); }]>; 144 145def immBitp : PatLeaf<(imm), [{ 146 uint32_t value = (uint32_t)N->getZExtValue(); 147 return (value >= 1 && value <= 8) 148 || value == 16 149 || value == 24 150 || value == 32; 151}]>; 152 153def immBpwSubBitp : PatLeaf<(imm), [{ 154 uint32_t value = (uint32_t)N->getZExtValue(); 155 return (value >= 24 && value <= 31) 156 || value == 16 157 || value == 8 158 || value == 0; 159}]>; 160 161def lda16f : PatFrag<(ops node:$addr, node:$offset), 162 (add node:$addr, (shl node:$offset, 1))>; 163def lda16b : PatFrag<(ops node:$addr, node:$offset), 164 (sub node:$addr, (shl node:$offset, 1))>; 165def ldawf : PatFrag<(ops node:$addr, node:$offset), 166 (add node:$addr, (shl node:$offset, 2))>; 167def ldawb : PatFrag<(ops node:$addr, node:$offset), 168 (sub node:$addr, (shl node:$offset, 2))>; 169 170// Instruction operand types 171def pcrel_imm : Operand<i32>; 172def pcrel_imm_neg : Operand<i32> { 173 let DecoderMethod = "DecodeNegImmOperand"; 174} 175def brtarget : Operand<OtherVT>; 176def brtarget_neg : Operand<OtherVT> { 177 let DecoderMethod = "DecodeNegImmOperand"; 178} 179 180// Addressing modes 181def ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>; 182 183// Address operands 184def MEMii : Operand<i32> { 185 let MIOperandInfo = (ops i32imm, i32imm); 186} 187 188// Jump tables. 189def InlineJT : Operand<i32> { 190 let PrintMethod = "printInlineJT"; 191} 192 193def InlineJT32 : Operand<i32> { 194 let PrintMethod = "printInlineJT32"; 195} 196 197//===----------------------------------------------------------------------===// 198// Instruction Class Templates 199//===----------------------------------------------------------------------===// 200 201// Three operand short 202 203multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> { 204 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 205 !strconcat(OpcStr, " $dst, $b, $c"), 206 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 207 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 208 !strconcat(OpcStr, " $dst, $b, $c"), 209 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; 210} 211 212multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> { 213 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 214 !strconcat(OpcStr, " $dst, $b, $c"), []>; 215 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 216 !strconcat(OpcStr, " $dst, $b, $c"), []>; 217} 218 219multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr, 220 SDNode OpNode> { 221 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 222 !strconcat(OpcStr, " $dst, $b, $c"), 223 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 224 def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 225 !strconcat(OpcStr, " $dst, $b, $c"), 226 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; 227} 228 229class F3R<bits<5> opc, string OpcStr, SDNode OpNode> : 230 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 231 !strconcat(OpcStr, " $dst, $b, $c"), 232 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 233 234class F3R_np<bits<5> opc, string OpcStr> : 235 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 236 !strconcat(OpcStr, " $dst, $b, $c"), []>; 237// Three operand long 238 239/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. 240multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr, 241 SDNode OpNode> { 242 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 243 !strconcat(OpcStr, " $dst, $b, $c"), 244 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 245 def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 246 !strconcat(OpcStr, " $dst, $b, $c"), 247 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; 248} 249 250/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. 251multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr, 252 SDNode OpNode> { 253 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 254 !strconcat(OpcStr, " $dst, $b, $c"), 255 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 256 def _l2rus : _FL2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 257 !strconcat(OpcStr, " $dst, $b, $c"), 258 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; 259} 260 261class FL3R<bits<9> opc, string OpcStr, SDNode OpNode> : 262 _FL3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 263 !strconcat(OpcStr, " $dst, $b, $c"), 264 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 265 266// Register - U6 267// Operand register - U6 268multiclass FRU6_LRU6_branch<bits<6> opc, string OpcStr> { 269 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b), 270 !strconcat(OpcStr, " $a, $b"), []>; 271 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b), 272 !strconcat(OpcStr, " $a, $b"), []>; 273} 274 275multiclass FRU6_LRU6_backwards_branch<bits<6> opc, string OpcStr> { 276 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget_neg:$b), 277 !strconcat(OpcStr, " $a, $b"), []>; 278 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget_neg:$b), 279 !strconcat(OpcStr, " $a, $b"), []>; 280} 281 282multiclass FRU6_LRU6_cp<bits<6> opc, string OpcStr> { 283 def _ru6: _FRU6<opc, (outs RRegs:$a), (ins i32imm:$b), 284 !strconcat(OpcStr, " $a, cp[$b]"), []>; 285 def _lru6: _FLRU6<opc, (outs RRegs:$a), (ins i32imm:$b), 286 !strconcat(OpcStr, " $a, cp[$b]"), []>; 287} 288 289// U6 290multiclass FU6_LU6<bits<10> opc, string OpcStr, SDNode OpNode> { 291 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), 292 [(OpNode immU6:$a)]>; 293 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), 294 [(OpNode immU16:$a)]>; 295} 296 297multiclass FU6_LU6_int<bits<10> opc, string OpcStr, Intrinsic Int> { 298 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), 299 [(Int immU6:$a)]>; 300 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), 301 [(Int immU16:$a)]>; 302} 303 304multiclass FU6_LU6_np<bits<10> opc, string OpcStr> { 305 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>; 306 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>; 307} 308 309// Two operand short 310 311class F2R_np<bits<6> opc, string OpcStr> : 312 _F2R<opc, (outs GRRegs:$dst), (ins GRRegs:$b), 313 !strconcat(OpcStr, " $dst, $b"), []>; 314 315// Two operand long 316 317//===----------------------------------------------------------------------===// 318// Pseudo Instructions 319//===----------------------------------------------------------------------===// 320 321let Defs = [SP], Uses = [SP] in { 322def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt), 323 "# ADJCALLSTACKDOWN $amt", 324 [(callseq_start timm:$amt)]>; 325def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2), 326 "# ADJCALLSTACKUP $amt1", 327 [(callseq_end timm:$amt1, timm:$amt2)]>; 328} 329 330def LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr), 331 "# LDWFI $dst, $addr", 332 [(set GRRegs:$dst, (load ADDRspii:$addr))]>; 333 334def LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr), 335 "# LDAWFI $dst, $addr", 336 [(set GRRegs:$dst, ADDRspii:$addr)]>; 337 338def STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr), 339 "# STWFI $src, $addr", 340 [(store GRRegs:$src, ADDRspii:$addr)]>; 341 342// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 343// instruction selection into a branch sequence. 344let usesCustomInserter = 1 in { 345 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst), 346 (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F), 347 "# SELECT_CC PSEUDO!", 348 [(set GRRegs:$dst, 349 (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>; 350} 351 352//===----------------------------------------------------------------------===// 353// Instructions 354//===----------------------------------------------------------------------===// 355 356// Three operand short 357defm ADD : F3R_2RUS<0b00010, 0b10010, "add", add>; 358defm SUB : F3R_2RUS<0b00011, 0b10011, "sub", sub>; 359let neverHasSideEffects = 1 in { 360defm EQ : F3R_2RUS_np<0b00110, 0b10110, "eq">; 361def LSS_3r : F3R_np<0b11000, "lss">; 362def LSU_3r : F3R_np<0b11001, "lsu">; 363} 364def AND_3r : F3R<0b00111, "and", and>; 365def OR_3r : F3R<0b01000, "or", or>; 366 367let mayLoad=1 in { 368def LDW_3r : _F3R<0b01001, (outs GRRegs:$dst), 369 (ins GRRegs:$addr, GRRegs:$offset), 370 "ldw $dst, $addr[$offset]", []>; 371 372def LDW_2rus : _F2RUS<0b00001, (outs GRRegs:$dst), 373 (ins GRRegs:$addr, i32imm:$offset), 374 "ldw $dst, $addr[$offset]", []>; 375 376def LD16S_3r : _F3R<0b10000, (outs GRRegs:$dst), 377 (ins GRRegs:$addr, GRRegs:$offset), 378 "ld16s $dst, $addr[$offset]", []>; 379 380def LD8U_3r : _F3R<0b10001, (outs GRRegs:$dst), 381 (ins GRRegs:$addr, GRRegs:$offset), 382 "ld8u $dst, $addr[$offset]", []>; 383} 384 385let mayStore=1 in { 386def STW_l3r : _FL3R<0b000001100, (outs), 387 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 388 "stw $val, $addr[$offset]", []>; 389 390def STW_2rus : _F2RUS<0b0000, (outs), 391 (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset), 392 "stw $val, $addr[$offset]", []>; 393} 394 395defm SHL : F3R_2RBITP<0b00100, 0b10100, "shl", shl>; 396defm SHR : F3R_2RBITP<0b00101, 0b10101, "shr", srl>; 397 398// The first operand is treated as an immediate since it refers to a register 399// number in another thread. 400def TSETR_3r : _F3RImm<0b10111, (outs), (ins i32imm:$a, GRRegs:$b, GRRegs:$c), 401 "set t[$c]:r$a, $b", []>; 402 403// Three operand long 404def LDAWF_l3r : _FL3R<0b000111100, (outs GRRegs:$dst), 405 (ins GRRegs:$addr, GRRegs:$offset), 406 "ldaw $dst, $addr[$offset]", 407 [(set GRRegs:$dst, 408 (ldawf GRRegs:$addr, GRRegs:$offset))]>; 409 410let neverHasSideEffects = 1 in 411def LDAWF_l2rus : _FL2RUS<0b100111100, (outs GRRegs:$dst), 412 (ins GRRegs:$addr, i32imm:$offset), 413 "ldaw $dst, $addr[$offset]", []>; 414 415def LDAWB_l3r : _FL3R<0b001001100, (outs GRRegs:$dst), 416 (ins GRRegs:$addr, GRRegs:$offset), 417 "ldaw $dst, $addr[-$offset]", 418 [(set GRRegs:$dst, 419 (ldawb GRRegs:$addr, GRRegs:$offset))]>; 420 421let neverHasSideEffects = 1 in 422def LDAWB_l2rus : _FL2RUS<0b101001100, (outs GRRegs:$dst), 423 (ins GRRegs:$addr, i32imm:$offset), 424 "ldaw $dst, $addr[-$offset]", []>; 425 426def LDA16F_l3r : _FL3R<0b001011100, (outs GRRegs:$dst), 427 (ins GRRegs:$addr, GRRegs:$offset), 428 "lda16 $dst, $addr[$offset]", 429 [(set GRRegs:$dst, 430 (lda16f GRRegs:$addr, GRRegs:$offset))]>; 431 432def LDA16B_l3r : _FL3R<0b001101100, (outs GRRegs:$dst), 433 (ins GRRegs:$addr, GRRegs:$offset), 434 "lda16 $dst, $addr[-$offset]", 435 [(set GRRegs:$dst, 436 (lda16b GRRegs:$addr, GRRegs:$offset))]>; 437 438def MUL_l3r : FL3R<0b001111100, "mul", mul>; 439// Instructions which may trap are marked as side effecting. 440let hasSideEffects = 1 in { 441def DIVS_l3r : FL3R<0b010001100, "divs", sdiv>; 442def DIVU_l3r : FL3R<0b010011100, "divu", udiv>; 443def REMS_l3r : FL3R<0b110001100, "rems", srem>; 444def REMU_l3r : FL3R<0b110011100, "remu", urem>; 445} 446def XOR_l3r : FL3R<0b000011100, "xor", xor>; 447defm ASHR : FL3R_L2RBITP<0b000101100, 0b100101100, "ashr", sra>; 448 449let Constraints = "$src1 = $dst" in 450def CRC_l3r : _FL3RSrcDst<0b101011100, (outs GRRegs:$dst), 451 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 452 "crc32 $dst, $src2, $src3", 453 [(set GRRegs:$dst, 454 (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2, 455 GRRegs:$src3))]>; 456 457let mayStore=1 in { 458def ST16_l3r : _FL3R<0b100001100, (outs), 459 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 460 "st16 $val, $addr[$offset]", []>; 461 462def ST8_l3r : _FL3R<0b100011100, (outs), 463 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 464 "st8 $val, $addr[$offset]", []>; 465} 466 467def INPW_l2rus : _FL2RUSBitp<0b100101110, (outs GRRegs:$a), 468 (ins GRRegs:$b, i32imm:$c), "inpw $a, res[$b], $c", 469 []>; 470 471def OUTPW_l2rus : _FL2RUSBitp<0b100101101, (outs), 472 (ins GRRegs:$a, GRRegs:$b, i32imm:$c), 473 "outpw res[$b], $a, $c", []>; 474 475// Four operand long 476let Constraints = "$e = $a,$f = $b" in { 477def MACCU_l4r : _FL4RSrcDstSrcDst< 478 0b000001, (outs GRRegs:$a, GRRegs:$b), 479 (ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccu $a, $b, $c, $d", []>; 480 481def MACCS_l4r : _FL4RSrcDstSrcDst< 482 0b000010, (outs GRRegs:$a, GRRegs:$b), 483 (ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccs $a, $b, $c, $d", []>; 484} 485 486let Constraints = "$e = $b" in 487def CRC8_l4r : _FL4RSrcDst<0b000000, (outs GRRegs:$a, GRRegs:$b), 488 (ins GRRegs:$e, GRRegs:$c, GRRegs:$d), 489 "crc8 $b, $a, $c, $d", []>; 490 491// Five operand long 492 493def LADD_l5r : _FL5R<0b000001, (outs GRRegs:$dst1, GRRegs:$dst2), 494 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 495 "ladd $dst2, $dst1, $src1, $src2, $src3", 496 []>; 497 498def LSUB_l5r : _FL5R<0b000010, (outs GRRegs:$dst1, GRRegs:$dst2), 499 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 500 "lsub $dst2, $dst1, $src1, $src2, $src3", []>; 501 502def LDIVU_l5r : _FL5R<0b000000, (outs GRRegs:$dst1, GRRegs:$dst2), 503 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 504 "ldivu $dst1, $dst2, $src3, $src1, $src2", []>; 505 506// Six operand long 507 508def LMUL_l6r : _FL6R< 509 0b00000, (outs GRRegs:$dst1, GRRegs:$dst2), 510 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, GRRegs:$src4), 511 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4", []>; 512 513// Register - U6 514 515//let Uses = [DP] in ... 516let neverHasSideEffects = 1, isReMaterializable = 1 in 517def LDAWDP_ru6: _FRU6<0b011000, (outs RRegs:$a), (ins i32imm:$b), 518 "ldaw $a, dp[$b]", []>; 519 520let isReMaterializable = 1 in 521def LDAWDP_lru6: _FLRU6<0b011000, (outs RRegs:$a), (ins i32imm:$b), 522 "ldaw $a, dp[$b]", 523 [(set RRegs:$a, (dprelwrapper tglobaladdr:$b))]>; 524 525let mayLoad=1 in 526def LDWDP_ru6: _FRU6<0b010110, (outs RRegs:$a), (ins i32imm:$b), 527 "ldw $a, dp[$b]", []>; 528 529def LDWDP_lru6: _FLRU6<0b010110, (outs RRegs:$a), (ins i32imm:$b), 530 "ldw $a, dp[$b]", 531 [(set RRegs:$a, (load (dprelwrapper tglobaladdr:$b)))]>; 532 533let mayStore=1 in 534def STWDP_ru6 : _FRU6<0b010100, (outs), (ins RRegs:$a, i32imm:$b), 535 "stw $a, dp[$b]", []>; 536 537def STWDP_lru6 : _FLRU6<0b010100, (outs), (ins RRegs:$a, i32imm:$b), 538 "stw $a, dp[$b]", 539 [(store RRegs:$a, (dprelwrapper tglobaladdr:$b))]>; 540 541//let Uses = [CP] in .. 542let mayLoad = 1, isReMaterializable = 1, neverHasSideEffects = 1 in 543defm LDWCP : FRU6_LRU6_cp<0b011011, "ldw">; 544 545let Uses = [SP] in { 546let mayStore=1 in { 547def STWSP_ru6 : _FRU6<0b010101, (outs), (ins RRegs:$a, i32imm:$b), 548 "stw $a, sp[$b]", 549 [(XCoreStwsp RRegs:$a, immU6:$b)]>; 550 551def STWSP_lru6 : _FLRU6<0b010101, (outs), (ins RRegs:$a, i32imm:$b), 552 "stw $a, sp[$b]", 553 [(XCoreStwsp RRegs:$a, immU16:$b)]>; 554} 555 556let mayLoad=1 in { 557def LDWSP_ru6 : _FRU6<0b010111, (outs RRegs:$a), (ins i32imm:$b), 558 "ldw $a, sp[$b]", []>; 559 560def LDWSP_lru6 : _FLRU6<0b010111, (outs RRegs:$a), (ins i32imm:$b), 561 "ldw $a, sp[$b]", []>; 562} 563 564let neverHasSideEffects = 1 in { 565def LDAWSP_ru6 : _FRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b), 566 "ldaw $a, sp[$b]", []>; 567 568def LDAWSP_lru6 : _FLRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b), 569 "ldaw $a, sp[$b]", []>; 570} 571} 572 573let isReMaterializable = 1 in { 574def LDC_ru6 : _FRU6<0b011010, (outs RRegs:$a), (ins i32imm:$b), 575 "ldc $a, $b", [(set RRegs:$a, immU6:$b)]>; 576 577def LDC_lru6 : _FLRU6<0b011010, (outs RRegs:$a), (ins i32imm:$b), 578 "ldc $a, $b", [(set RRegs:$a, immU16:$b)]>; 579} 580 581def SETC_ru6 : _FRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b), 582 "setc res[$a], $b", 583 [(int_xcore_setc GRRegs:$a, immU6:$b)]>; 584 585def SETC_lru6 : _FLRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b), 586 "setc res[$a], $b", 587 [(int_xcore_setc GRRegs:$a, immU16:$b)]>; 588 589// Operand register - U6 590let isBranch = 1, isTerminator = 1 in { 591defm BRFT: FRU6_LRU6_branch<0b011100, "bt">; 592defm BRBT: FRU6_LRU6_backwards_branch<0b011101, "bt">; 593defm BRFF: FRU6_LRU6_branch<0b011110, "bf">; 594defm BRBF: FRU6_LRU6_backwards_branch<0b011111, "bf">; 595} 596 597// U6 598let Defs = [SP], Uses = [SP] in { 599let neverHasSideEffects = 1 in 600defm EXTSP : FU6_LU6_np<0b0111011110, "extsp">; 601 602let mayStore = 1 in 603defm ENTSP : FU6_LU6_np<0b0111011101, "entsp">; 604 605let isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in { 606defm RETSP : FU6_LU6<0b0111011111, "retsp", XCoreRetsp>; 607} 608} 609 610let neverHasSideEffects = 1 in 611defm EXTDP : FU6_LU6_np<0b0111001110, "extdp">; 612 613let Uses = [R11], isCall=1 in 614defm BLAT : FU6_LU6_np<0b0111001101, "blat">; 615 616let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 617def BRBU_u6 : _FU6<0b0111011100, (outs), (ins brtarget_neg:$a), "bu $a", []>; 618 619def BRBU_lu6 : _FLU6<0b0111011100, (outs), (ins brtarget_neg:$a), "bu $a", []>; 620 621def BRFU_u6 : _FU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>; 622 623def BRFU_lu6 : _FLU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>; 624} 625 626//let Uses = [CP] in ... 627let Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in 628def LDAWCP_u6: _FU6<0b0111111101, (outs), (ins i32imm:$a), "ldaw r11, cp[$a]", 629 []>; 630 631let Defs = [R11], isReMaterializable = 1 in 632def LDAWCP_lu6: _FLU6<0b0111111101, (outs), (ins i32imm:$a), "ldaw r11, cp[$a]", 633 [(set R11, (cprelwrapper tglobaladdr:$a))]>; 634 635let Defs = [R11] in 636defm GETSR : FU6_LU6_np<0b0111111100, "getsr r11,">; 637 638defm SETSR : FU6_LU6_int<0b0111101101, "setsr", int_xcore_setsr>; 639 640defm CLRSR : FU6_LU6_int<0b0111101100, "clrsr", int_xcore_clrsr>; 641 642// setsr may cause a branch if it is used to enable events. clrsr may 643// branch if it is executed while events are enabled. 644let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1, 645 isCodeGenOnly = 1 in { 646defm SETSR_branch : FU6_LU6_np<0b0111101101, "setsr">; 647defm CLRSR_branch : FU6_LU6_np<0b0111101100, "clrsr">; 648} 649 650defm KCALL : FU6_LU6_np<0b0111001111, "kcall">; 651 652let Uses = [SP], Defs = [SP], mayStore = 1 in 653defm KENTSP : FU6_LU6_np<0b0111101110, "kentsp">; 654 655let Uses = [SP], Defs = [SP], mayLoad = 1 in 656defm KRESTSP : FU6_LU6_np<0b0111101111, "krestsp">; 657 658// U10 659 660let Defs = [R11], isReMaterializable = 1 in { 661let neverHasSideEffects = 1 in 662def LDAPF_u10 : _FU10<0b110110, (outs), (ins pcrel_imm:$a), "ldap r11, $a", []>; 663 664def LDAPF_lu10 : _FLU10<0b110110, (outs), (ins pcrel_imm:$a), "ldap r11, $a", 665 [(set R11, (pcrelwrapper tglobaladdr:$a))]>; 666 667let neverHasSideEffects = 1 in 668def LDAPB_u10 : _FU10<0b110111, (outs), (ins pcrel_imm_neg:$a), "ldap r11, $a", 669 []>; 670 671let neverHasSideEffects = 1 in 672def LDAPB_lu10 : _FLU10<0b110111, (outs), (ins pcrel_imm_neg:$a), 673 "ldap r11, $a", 674 [(set R11, (pcrelwrapper tglobaladdr:$a))]>; 675 676let isCodeGenOnly = 1 in 677def LDAPF_lu10_ba : _FLU10<0b110110, (outs), (ins pcrel_imm:$a), "ldap r11, $a", 678 [(set R11, (pcrelwrapper tblockaddress:$a))]>; 679} 680 681let isCall=1, 682// All calls clobber the link register and the non-callee-saved registers: 683Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in { 684def BLACP_u10 : _FU10<0b111000, (outs), (ins i32imm:$a), "bla cp[$a]", []>; 685 686def BLACP_lu10 : _FLU10<0b111000, (outs), (ins i32imm:$a), "bla cp[$a]", []>; 687 688def BLRF_u10 : _FU10<0b110100, (outs), (ins pcrel_imm:$a), "bl $a", 689 [(XCoreBranchLink immU10:$a)]>; 690 691def BLRF_lu10 : _FLU10<0b110100, (outs), (ins pcrel_imm:$a), "bl $a", 692 [(XCoreBranchLink immU20:$a)]>; 693 694def BLRB_u10 : _FU10<0b110101, (outs), (ins pcrel_imm_neg:$a), "bl $a", []>; 695 696def BLRB_lu10 : _FLU10<0b110101, (outs), (ins pcrel_imm_neg:$a), "bl $a", []>; 697} 698 699let Defs = [R11], mayLoad = 1, isReMaterializable = 1, 700 neverHasSideEffects = 1 in { 701def LDWCP_u10 : _FU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]", []>; 702 703def LDWCP_lu10 : _FLU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]", 704 []>; 705} 706 707// Two operand short 708def NOT : _F2R<0b100010, (outs GRRegs:$dst), (ins GRRegs:$b), 709 "not $dst, $b", [(set GRRegs:$dst, (not GRRegs:$b))]>; 710 711def NEG : _F2R<0b100100, (outs GRRegs:$dst), (ins GRRegs:$b), 712 "neg $dst, $b", [(set GRRegs:$dst, (ineg GRRegs:$b))]>; 713 714let Constraints = "$src1 = $dst" in { 715def SEXT_rus : 716 _FRUSSrcDstBitp<0b001101, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), 717 "sext $dst, $src2", 718 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, 719 immBitp:$src2))]>; 720 721def SEXT_2r : 722 _F2RSrcDst<0b001100, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), 723 "sext $dst, $src2", 724 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, GRRegs:$src2))]>; 725 726def ZEXT_rus : 727 _FRUSSrcDstBitp<0b010001, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), 728 "zext $dst, $src2", 729 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, 730 immBitp:$src2))]>; 731 732def ZEXT_2r : 733 _F2RSrcDst<0b010000, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), 734 "zext $dst, $src2", 735 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, GRRegs:$src2))]>; 736 737def ANDNOT_2r : 738 _F2RSrcDst<0b001010, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), 739 "andnot $dst, $src2", 740 [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>; 741} 742 743let isReMaterializable = 1, neverHasSideEffects = 1 in 744def MKMSK_rus : _FRUSBitp<0b101001, (outs GRRegs:$dst), (ins i32imm:$size), 745 "mkmsk $dst, $size", []>; 746 747def MKMSK_2r : _F2R<0b101000, (outs GRRegs:$dst), (ins GRRegs:$size), 748 "mkmsk $dst, $size", 749 [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), -1))]>; 750 751def GETR_rus : _FRUS<0b100000, (outs GRRegs:$dst), (ins i32imm:$type), 752 "getr $dst, $type", 753 [(set GRRegs:$dst, (int_xcore_getr immUs:$type))]>; 754 755def GETTS_2r : _F2R<0b001110, (outs GRRegs:$dst), (ins GRRegs:$r), 756 "getts $dst, res[$r]", 757 [(set GRRegs:$dst, (int_xcore_getts GRRegs:$r))]>; 758 759def SETPT_2r : _FR2R<0b001111, (outs), (ins GRRegs:$r, GRRegs:$val), 760 "setpt res[$r], $val", 761 [(int_xcore_setpt GRRegs:$r, GRRegs:$val)]>; 762 763def OUTCT_2r : _F2R<0b010010, (outs), (ins GRRegs:$r, GRRegs:$val), 764 "outct res[$r], $val", 765 [(int_xcore_outct GRRegs:$r, GRRegs:$val)]>; 766 767def OUTCT_rus : _FRUS<0b010011, (outs), (ins GRRegs:$r, i32imm:$val), 768 "outct res[$r], $val", 769 [(int_xcore_outct GRRegs:$r, immUs:$val)]>; 770 771def OUTT_2r : _FR2R<0b000011, (outs), (ins GRRegs:$r, GRRegs:$val), 772 "outt res[$r], $val", 773 [(int_xcore_outt GRRegs:$r, GRRegs:$val)]>; 774 775def OUT_2r : _FR2R<0b101010, (outs), (ins GRRegs:$r, GRRegs:$val), 776 "out res[$r], $val", 777 [(int_xcore_out GRRegs:$r, GRRegs:$val)]>; 778 779let Constraints = "$src = $dst" in 780def OUTSHR_2r : 781 _F2RSrcDst<0b101011, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r), 782 "outshr res[$r], $src", 783 [(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r, GRRegs:$src))]>; 784 785def INCT_2r : _F2R<0b100001, (outs GRRegs:$dst), (ins GRRegs:$r), 786 "inct $dst, res[$r]", 787 [(set GRRegs:$dst, (int_xcore_inct GRRegs:$r))]>; 788 789def INT_2r : _F2R<0b100011, (outs GRRegs:$dst), (ins GRRegs:$r), 790 "int $dst, res[$r]", 791 [(set GRRegs:$dst, (int_xcore_int GRRegs:$r))]>; 792 793def IN_2r : _F2R<0b101100, (outs GRRegs:$dst), (ins GRRegs:$r), 794 "in $dst, res[$r]", 795 [(set GRRegs:$dst, (int_xcore_in GRRegs:$r))]>; 796 797let Constraints = "$src = $dst" in 798def INSHR_2r : 799 _F2RSrcDst<0b101101, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r), 800 "inshr $dst, res[$r]", 801 [(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r, GRRegs:$src))]>; 802 803def CHKCT_2r : _F2R<0b110010, (outs), (ins GRRegs:$r, GRRegs:$val), 804 "chkct res[$r], $val", 805 [(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>; 806 807def CHKCT_rus : _FRUSBitp<0b110011, (outs), (ins GRRegs:$r, i32imm:$val), 808 "chkct res[$r], $val", 809 [(int_xcore_chkct GRRegs:$r, immUs:$val)]>; 810 811def TESTCT_2r : _F2R<0b101111, (outs GRRegs:$dst), (ins GRRegs:$src), 812 "testct $dst, res[$src]", 813 [(set GRRegs:$dst, (int_xcore_testct GRRegs:$src))]>; 814 815def TESTWCT_2r : _F2R<0b110001, (outs GRRegs:$dst), (ins GRRegs:$src), 816 "testwct $dst, res[$src]", 817 [(set GRRegs:$dst, (int_xcore_testwct GRRegs:$src))]>; 818 819def SETD_2r : _FR2R<0b000101, (outs), (ins GRRegs:$r, GRRegs:$val), 820 "setd res[$r], $val", 821 [(int_xcore_setd GRRegs:$r, GRRegs:$val)]>; 822 823def SETPSC_2r : _FR2R<0b110000, (outs), (ins GRRegs:$src1, GRRegs:$src2), 824 "setpsc res[$src1], $src2", 825 [(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>; 826 827def GETST_2r : _F2R<0b000001, (outs GRRegs:$dst), (ins GRRegs:$r), 828 "getst $dst, res[$r]", 829 [(set GRRegs:$dst, (int_xcore_getst GRRegs:$r))]>; 830 831def INITSP_2r : _F2R<0b000100, (outs), (ins GRRegs:$src, GRRegs:$t), 832 "init t[$t]:sp, $src", 833 [(int_xcore_initsp GRRegs:$t, GRRegs:$src)]>; 834 835def INITPC_2r : _F2R<0b000000, (outs), (ins GRRegs:$src, GRRegs:$t), 836 "init t[$t]:pc, $src", 837 [(int_xcore_initpc GRRegs:$t, GRRegs:$src)]>; 838 839def INITCP_2r : _F2R<0b000110, (outs), (ins GRRegs:$src, GRRegs:$t), 840 "init t[$t]:cp, $src", 841 [(int_xcore_initcp GRRegs:$t, GRRegs:$src)]>; 842 843def INITDP_2r : _F2R<0b000010, (outs), (ins GRRegs:$src, GRRegs:$t), 844 "init t[$t]:dp, $src", 845 [(int_xcore_initdp GRRegs:$t, GRRegs:$src)]>; 846 847def PEEK_2r : _F2R<0b101110, (outs GRRegs:$dst), (ins GRRegs:$src), 848 "peek $dst, res[$src]", 849 [(set GRRegs:$dst, (int_xcore_peek GRRegs:$src))]>; 850 851def ENDIN_2r : _F2R<0b100101, (outs GRRegs:$dst), (ins GRRegs:$src), 852 "endin $dst, res[$src]", 853 [(set GRRegs:$dst, (int_xcore_endin GRRegs:$src))]>; 854 855def EEF_2r : _F2R<0b001011, (outs), (ins GRRegs:$a, GRRegs:$b), 856 "eef $a, res[$b]", []>; 857 858def EET_2r : _F2R<0b001001, (outs), (ins GRRegs:$a, GRRegs:$b), 859 "eet $a, res[$b]", []>; 860 861def TSETMR_2r : _F2RImm<0b000111, (outs), (ins i32imm:$a, GRRegs:$b), 862 "tsetmr r$a, $b", []>; 863 864// Two operand long 865def BITREV_l2r : _FL2R<0b0000011000, (outs GRRegs:$dst), (ins GRRegs:$src), 866 "bitrev $dst, $src", 867 [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>; 868 869def BYTEREV_l2r : _FL2R<0b0000011001, (outs GRRegs:$dst), (ins GRRegs:$src), 870 "byterev $dst, $src", 871 [(set GRRegs:$dst, (bswap GRRegs:$src))]>; 872 873def CLZ_l2r : _FL2R<0b000111000, (outs GRRegs:$dst), (ins GRRegs:$src), 874 "clz $dst, $src", 875 [(set GRRegs:$dst, (ctlz GRRegs:$src))]>; 876 877def GETD_l2r : _FL2R<0b0001111001, (outs GRRegs:$dst), (ins GRRegs:$src), 878 "getd $dst, res[$src]", []>; 879 880def GETN_l2r : _FL2R<0b0011011001, (outs GRRegs:$dst), (ins GRRegs:$src), 881 "getn $dst, res[$src]", []>; 882 883def SETC_l2r : _FL2R<0b0010111001, (outs), (ins GRRegs:$r, GRRegs:$val), 884 "setc res[$r], $val", 885 [(int_xcore_setc GRRegs:$r, GRRegs:$val)]>; 886 887def SETTW_l2r : _FLR2R<0b0010011001, (outs), (ins GRRegs:$r, GRRegs:$val), 888 "settw res[$r], $val", 889 [(int_xcore_settw GRRegs:$r, GRRegs:$val)]>; 890 891def GETPS_l2r : _FL2R<0b0001011001, (outs GRRegs:$dst), (ins GRRegs:$src), 892 "get $dst, ps[$src]", 893 [(set GRRegs:$dst, (int_xcore_getps GRRegs:$src))]>; 894 895def SETPS_l2r : _FLR2R<0b0001111000, (outs), (ins GRRegs:$src1, GRRegs:$src2), 896 "set ps[$src1], $src2", 897 [(int_xcore_setps GRRegs:$src1, GRRegs:$src2)]>; 898 899def INITLR_l2r : _FL2R<0b0001011000, (outs), (ins GRRegs:$src, GRRegs:$t), 900 "init t[$t]:lr, $src", 901 [(int_xcore_initlr GRRegs:$t, GRRegs:$src)]>; 902 903def SETCLK_l2r : _FLR2R<0b0000111001, (outs), (ins GRRegs:$src1, GRRegs:$src2), 904 "setclk res[$src1], $src2", 905 [(int_xcore_setclk GRRegs:$src1, GRRegs:$src2)]>; 906 907def SETN_l2r : _FLR2R<0b0011011000, (outs), (ins GRRegs:$src1, GRRegs:$src2), 908 "setn res[$src1], $src2", []>; 909 910def SETRDY_l2r : _FLR2R<0b0010111000, (outs), (ins GRRegs:$src1, GRRegs:$src2), 911 "setrdy res[$src1], $src2", 912 [(int_xcore_setrdy GRRegs:$src1, GRRegs:$src2)]>; 913 914def TESTLCL_l2r : _FL2R<0b0010011000, (outs GRRegs:$dst), (ins GRRegs:$src), 915 "testlcl $dst, res[$src]", []>; 916 917// One operand short 918def MSYNC_1r : _F1R<0b000111, (outs), (ins GRRegs:$a), 919 "msync res[$a]", 920 [(int_xcore_msync GRRegs:$a)]>; 921def MJOIN_1r : _F1R<0b000101, (outs), (ins GRRegs:$a), 922 "mjoin res[$a]", 923 [(int_xcore_mjoin GRRegs:$a)]>; 924 925let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 926def BAU_1r : _F1R<0b001001, (outs), (ins GRRegs:$a), 927 "bau $a", 928 [(brind GRRegs:$a)]>; 929 930let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 931def BR_JT : PseudoInstXCore<(outs), (ins InlineJT:$t, GRRegs:$i), 932 "bru $i\n$t", 933 [(XCoreBR_JT tjumptable:$t, GRRegs:$i)]>; 934 935let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 936def BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i), 937 "bru $i\n$t", 938 [(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>; 939 940let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 941def BRU_1r : _F1R<0b001010, (outs), (ins GRRegs:$a), "bru $a", []>; 942 943let Defs=[SP], neverHasSideEffects=1 in 944def SETSP_1r : _F1R<0b001011, (outs), (ins GRRegs:$a), "set sp, $a", []>; 945 946let neverHasSideEffects=1 in 947def SETDP_1r : _F1R<0b001100, (outs), (ins GRRegs:$a), "set dp, $a", []>; 948 949let neverHasSideEffects=1 in 950def SETCP_1r : _F1R<0b001101, (outs), (ins GRRegs:$a), "set cp, $a", []>; 951 952let hasCtrlDep = 1 in 953def ECALLT_1r : _F1R<0b010011, (outs), (ins GRRegs:$a), 954 "ecallt $a", 955 []>; 956 957let hasCtrlDep = 1 in 958def ECALLF_1r : _F1R<0b010010, (outs), (ins GRRegs:$a), 959 "ecallf $a", 960 []>; 961 962let isCall=1, 963// All calls clobber the link register and the non-callee-saved registers: 964Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in { 965def BLA_1r : _F1R<0b001000, (outs), (ins GRRegs:$a), 966 "bla $a", 967 [(XCoreBranchLink GRRegs:$a)]>; 968} 969 970def SYNCR_1r : _F1R<0b100001, (outs), (ins GRRegs:$a), 971 "syncr res[$a]", 972 [(int_xcore_syncr GRRegs:$a)]>; 973 974def FREER_1r : _F1R<0b000100, (outs), (ins GRRegs:$a), 975 "freer res[$a]", 976 [(int_xcore_freer GRRegs:$a)]>; 977 978let Uses=[R11] in { 979def SETV_1r : _F1R<0b010001, (outs), (ins GRRegs:$a), 980 "setv res[$a], r11", 981 [(int_xcore_setv GRRegs:$a, R11)]>; 982 983def SETEV_1r : _F1R<0b001111, (outs), (ins GRRegs:$a), 984 "setev res[$a], r11", 985 [(int_xcore_setev GRRegs:$a, R11)]>; 986} 987 988def DGETREG_1r : _F1R<0b001110, (outs GRRegs:$a), (ins), "dgetreg $a", []>; 989 990def EDU_1r : _F1R<0b000000, (outs), (ins GRRegs:$a), "edu res[$a]", []>; 991 992def EEU_1r : _F1R<0b000001, (outs), (ins GRRegs:$a), 993 "eeu res[$a]", 994 [(int_xcore_eeu GRRegs:$a)]>; 995 996def KCALL_1r : _F1R<0b010000, (outs), (ins GRRegs:$a), "kcall $a", []>; 997 998def WAITEF_1R : _F1R<0b000011, (outs), (ins GRRegs:$a), "waitef $a", []>; 999 1000def WAITET_1R : _F1R<0b000010, (outs), (ins GRRegs:$a), "waitet $a", []>; 1001 1002def TSTART_1R : _F1R<0b000110, (outs), (ins GRRegs:$a), "start t[$a]", []>; 1003 1004def CLRPT_1R : _F1R<0b100000, (outs), (ins GRRegs:$a), "clrpt res[$a]", []>; 1005 1006// Zero operand short 1007 1008def CLRE_0R : _F0R<0b0000001101, (outs), (ins), "clre", [(int_xcore_clre)]>; 1009 1010def DCALL_0R : _F0R<0b0000011100, (outs), (ins), "dcall", []>; 1011 1012let Defs = [SP], Uses = [SP] in 1013def DENTSP_0R : _F0R<0b0001001100, (outs), (ins), "dentsp", []>; 1014 1015let Defs = [SP] in 1016def DRESTSP_0R : _F0R<0b0001001101, (outs), (ins), "drestsp", []>; 1017 1018def DRET_0R : _F0R<0b0000011110, (outs), (ins), "dret", []>; 1019 1020def FREET_0R : _F0R<0b0000001111, (outs), (ins), "freet", []>; 1021 1022let Defs = [R11] in { 1023def GETID_0R : _F0R<0b0001001110, (outs), (ins), 1024 "get r11, id", 1025 [(set R11, (int_xcore_getid))]>; 1026 1027def GETED_0R : _F0R<0b0000111110, (outs), (ins), 1028 "get r11, ed", 1029 [(set R11, (int_xcore_geted))]>; 1030 1031def GETET_0R : _F0R<0b0000111111, (outs), (ins), 1032 "get r11, et", 1033 [(set R11, (int_xcore_getet))]>; 1034 1035def GETKEP_0R : _F0R<0b0001001111, (outs), (ins), 1036 "get r11, kep", []>; 1037 1038def GETKSP_0R : _F0R<0b0001011100, (outs), (ins), 1039 "get r11, ksp", []>; 1040} 1041 1042let Defs = [SP] in 1043def KRET_0R : _F0R<0b0000011101, (outs), (ins), "kret", []>; 1044 1045let Uses = [SP], mayLoad = 1 in { 1046def LDET_0R : _F0R<0b0001011110, (outs), (ins), "ldw et, sp[4]", []>; 1047 1048def LDSED_0R : _F0R<0b0001011101, (outs), (ins), "ldw sed, sp[3]", []>; 1049 1050def LDSPC_0R : _F0R<0b0000101100, (outs), (ins), "ldw spc, sp[1]", []>; 1051 1052def LDSSR_0R : _F0R<0b0000101110, (outs), (ins), "ldw ssr, sp[2]", []>; 1053} 1054 1055let Uses=[R11] in 1056def SETKEP_0R : _F0R<0b0000011111, (outs), (ins), "set kep, r11", []>; 1057 1058def SSYNC_0r : _F0R<0b0000001110, (outs), (ins), 1059 "ssync", 1060 [(int_xcore_ssync)]>; 1061 1062let Uses = [SP], mayStore = 1 in { 1063def STET_0R : _F0R<0b0000111101, (outs), (ins), "stw et, sp[4]", []>; 1064 1065def STSED_0R : _F0R<0b0000111100, (outs), (ins), "stw sed, sp[3]", []>; 1066 1067def STSPC_0R : _F0R<0b0000101101, (outs), (ins), "stw spc, sp[1]", []>; 1068 1069def STSSR_0R : _F0R<0b0000101111, (outs), (ins), "stw ssr, sp[2]", []>; 1070} 1071 1072let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1, 1073 hasSideEffects = 1 in 1074def WAITEU_0R : _F0R<0b0000001100, (outs), (ins), 1075 "waiteu", 1076 [(brind (int_xcore_waitevent))]>; 1077 1078//===----------------------------------------------------------------------===// 1079// Non-Instruction Patterns 1080//===----------------------------------------------------------------------===// 1081 1082def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BLRF_lu10 tglobaladdr:$addr)>; 1083def : Pat<(XCoreBranchLink texternalsym:$addr), (BLRF_lu10 texternalsym:$addr)>; 1084 1085/// sext_inreg 1086def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>; 1087def : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>; 1088def : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>; 1089 1090/// loads 1091def : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)), 1092 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>; 1093def : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>; 1094 1095def : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)), 1096 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>; 1097def : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>; 1098 1099def : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)), 1100 (LDW_3r GRRegs:$addr, GRRegs:$offset)>; 1101def : Pat<(load (add GRRegs:$addr, immUs4:$offset)), 1102 (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 1103def : Pat<(load GRRegs:$addr), (LDW_2rus GRRegs:$addr, 0)>; 1104 1105/// anyext 1106def : Pat<(extloadi8 (add GRRegs:$addr, GRRegs:$offset)), 1107 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>; 1108def : Pat<(extloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>; 1109def : Pat<(extloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)), 1110 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>; 1111def : Pat<(extloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>; 1112 1113/// stores 1114def : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)), 1115 (ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 1116def : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr), 1117 (ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>; 1118 1119def : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)), 1120 (ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 1121def : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr), 1122 (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>; 1123 1124def : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)), 1125 (STW_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 1126def : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)), 1127 (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>; 1128def : Pat<(store GRRegs:$val, GRRegs:$addr), 1129 (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>; 1130 1131/// cttz 1132def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>; 1133 1134/// trap 1135def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>; 1136 1137/// 1138/// branch patterns 1139/// 1140 1141// unconditional branch 1142def : Pat<(br bb:$addr), (BRFU_lu6 bb:$addr)>; 1143 1144// direct match equal/notequal zero brcond 1145def : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst), 1146 (BRFT_lru6 GRRegs:$lhs, bb:$dst)>; 1147def : Pat<(brcond (seteq GRRegs:$lhs, 0), bb:$dst), 1148 (BRFF_lru6 GRRegs:$lhs, bb:$dst)>; 1149 1150def : Pat<(brcond (setle GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1151 (BRFF_lru6 (LSS_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>; 1152def : Pat<(brcond (setule GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1153 (BRFF_lru6 (LSU_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>; 1154def : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1155 (BRFF_lru6 (LSS_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 1156def : Pat<(brcond (setuge GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1157 (BRFF_lru6 (LSU_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 1158def : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1159 (BRFF_lru6 (EQ_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 1160def : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst), 1161 (BRFF_lru6 (EQ_2rus GRRegs:$lhs, immUs:$rhs), bb:$dst)>; 1162 1163// generic brcond pattern 1164def : Pat<(brcond GRRegs:$cond, bb:$addr), (BRFT_lru6 GRRegs:$cond, bb:$addr)>; 1165 1166 1167/// 1168/// Select patterns 1169/// 1170 1171// direct match equal/notequal zero select 1172def : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1173 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>; 1174 1175def : Pat<(select (seteq GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1176 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>; 1177 1178def : Pat<(select (setle GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1179 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>; 1180def : Pat<(select (setule GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1181 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>; 1182def : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1183 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 1184def : Pat<(select (setuge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1185 (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 1186def : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1187 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 1188def : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F), 1189 (SELECT_CC (EQ_2rus GRRegs:$lhs, immUs:$rhs), GRRegs:$F, GRRegs:$T)>; 1190 1191/// 1192/// setcc patterns, only matched when none of the above brcond 1193/// patterns match 1194/// 1195 1196// setcc 2 register operands 1197def : Pat<(setle GRRegs:$lhs, GRRegs:$rhs), 1198 (EQ_2rus (LSS_3r GRRegs:$rhs, GRRegs:$lhs), 0)>; 1199def : Pat<(setule GRRegs:$lhs, GRRegs:$rhs), 1200 (EQ_2rus (LSU_3r GRRegs:$rhs, GRRegs:$lhs), 0)>; 1201 1202def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs), 1203 (LSS_3r GRRegs:$rhs, GRRegs:$lhs)>; 1204def : Pat<(setugt GRRegs:$lhs, GRRegs:$rhs), 1205 (LSU_3r GRRegs:$rhs, GRRegs:$lhs)>; 1206 1207def : Pat<(setge GRRegs:$lhs, GRRegs:$rhs), 1208 (EQ_2rus (LSS_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 1209def : Pat<(setuge GRRegs:$lhs, GRRegs:$rhs), 1210 (EQ_2rus (LSU_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 1211 1212def : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs), 1213 (LSS_3r GRRegs:$lhs, GRRegs:$rhs)>; 1214def : Pat<(setult GRRegs:$lhs, GRRegs:$rhs), 1215 (LSU_3r GRRegs:$lhs, GRRegs:$rhs)>; 1216 1217def : Pat<(setne GRRegs:$lhs, GRRegs:$rhs), 1218 (EQ_2rus (EQ_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 1219 1220def : Pat<(seteq GRRegs:$lhs, GRRegs:$rhs), 1221 (EQ_3r GRRegs:$lhs, GRRegs:$rhs)>; 1222 1223// setcc reg/imm operands 1224def : Pat<(seteq GRRegs:$lhs, immUs:$rhs), 1225 (EQ_2rus GRRegs:$lhs, immUs:$rhs)>; 1226def : Pat<(setne GRRegs:$lhs, immUs:$rhs), 1227 (EQ_2rus (EQ_2rus GRRegs:$lhs, immUs:$rhs), 0)>; 1228 1229// misc 1230def : Pat<(add GRRegs:$addr, immUs4:$offset), 1231 (LDAWF_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 1232 1233def : Pat<(sub GRRegs:$addr, immUs4:$offset), 1234 (LDAWB_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 1235 1236def : Pat<(and GRRegs:$val, immMskBitp:$mask), 1237 (ZEXT_rus GRRegs:$val, (msksize_xform immMskBitp:$mask))>; 1238 1239// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 1240def : Pat<(add GRRegs:$src1, immUsNeg:$src2), 1241 (SUB_2rus GRRegs:$src1, (neg_xform immUsNeg:$src2))>; 1242 1243def : Pat<(add GRRegs:$src1, immUs4Neg:$src2), 1244 (LDAWB_l2rus GRRegs:$src1, (div4neg_xform immUs4Neg:$src2))>; 1245 1246/// 1247/// Some peepholes 1248/// 1249 1250def : Pat<(mul GRRegs:$src, 3), 1251 (LDA16F_l3r GRRegs:$src, GRRegs:$src)>; 1252 1253def : Pat<(mul GRRegs:$src, 5), 1254 (LDAWF_l3r GRRegs:$src, GRRegs:$src)>; 1255 1256def : Pat<(mul GRRegs:$src, -3), 1257 (LDAWB_l3r GRRegs:$src, GRRegs:$src)>; 1258 1259// ashr X, 32 is equivalent to ashr X, 31 on the XCore. 1260def : Pat<(sra GRRegs:$src, 31), 1261 (ASHR_l2rus GRRegs:$src, 32)>; 1262 1263def : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst), 1264 (BRFT_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>; 1265 1266// setge X, 0 is canonicalized to setgt X, -1 1267def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst), 1268 (BRFF_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>; 1269 1270def : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1271 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>; 1272 1273def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F), 1274 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$F, GRRegs:$T)>; 1275 1276def : Pat<(setgt GRRegs:$lhs, -1), 1277 (EQ_2rus (ASHR_l2rus GRRegs:$lhs, 32), 0)>; 1278 1279def : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm), 1280 (SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>; 1281