XCoreInstrInfo.cpp revision 212904
18876Srgrimes//===- XCoreInstrInfo.cpp - XCore Instruction Information -------*- C++ -*-===// 24Srgrimes// 34Srgrimes// The LLVM Compiler Infrastructure 44Srgrimes// 58876Srgrimes// This file is distributed under the University of Illinois Open Source 64Srgrimes// License. See LICENSE.TXT for details. 74Srgrimes// 84Srgrimes//===----------------------------------------------------------------------===// 94Srgrimes// 104Srgrimes// This file contains the XCore implementation of the TargetInstrInfo class. 118876Srgrimes// 128876Srgrimes//===----------------------------------------------------------------------===// 134Srgrimes 144Srgrimes#include "XCoreMachineFunctionInfo.h" 158876Srgrimes#include "XCoreInstrInfo.h" 164Srgrimes#include "XCore.h" 178876Srgrimes#include "llvm/MC/MCContext.h" 184Srgrimes#include "llvm/CodeGen/MachineInstrBuilder.h" 194Srgrimes#include "llvm/CodeGen/MachineFrameInfo.h" 204Srgrimes#include "llvm/CodeGen/MachineLocation.h" 214Srgrimes#include "XCoreGenInstrInfo.inc" 228876Srgrimes#include "llvm/ADT/STLExtras.h" 234Srgrimes#include "llvm/Support/Debug.h" 244Srgrimes#include "llvm/Support/ErrorHandling.h" 254Srgrimes 2647098Sbdenamespace llvm { 274Srgrimesnamespace XCore { 28623Srgrimes 294Srgrimes // XCore Condition Codes 304Srgrimes enum CondCode { 314Srgrimes COND_TRUE, 324Srgrimes COND_FALSE, 334Srgrimes COND_INVALID 342056Swollman }; 3547098Sbde} 3612734Sbde} 372056Swollman 384Srgrimesusing namespace llvm; 394Srgrimes 404SrgrimesXCoreInstrInfo::XCoreInstrInfo() 4112515Sphk : TargetInstrInfoImpl(XCoreInsts, array_lengthof(XCoreInsts)), 4212473Sbde RI(*this) { 434Srgrimes} 4412515Sphk 4512515Sphkstatic bool isZeroImm(const MachineOperand &op) { 4612515Sphk return op.isImm() && op.getImm() == 0; 4712515Sphk} 4812515Sphk 494Srgrimes/// isLoadFromStackSlot - If the specified machine instruction is a direct 5037504Sbde/// load from a stack slot, return the virtual or physical register number of 514Srgrimes/// the destination along with the FrameIndex of the loaded stack slot. If 524Srgrimes/// not, return 0. This predicate must return 0 if the instruction has 534Srgrimes/// any side effects other than loading from the stack slot. 5412515Sphkunsigned 5512515SphkXCoreInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const{ 564Srgrimes int Opcode = MI->getOpcode(); 5712515Sphk if (Opcode == XCore::LDWFI) 584Srgrimes { 594Srgrimes if ((MI->getOperand(1).isFI()) && // is a stack slot 604Srgrimes (MI->getOperand(2).isImm()) && // the imm is zero 614Srgrimes (isZeroImm(MI->getOperand(2)))) 624Srgrimes { 634Srgrimes FrameIndex = MI->getOperand(1).getIndex(); 644Srgrimes return MI->getOperand(0).getReg(); 654Srgrimes } 664Srgrimes } 674Srgrimes return 0; 684Srgrimes} 694Srgrimes 704Srgrimes /// isStoreToStackSlot - If the specified machine instruction is a direct 714Srgrimes /// store to a stack slot, return the virtual or physical register number of 724Srgrimes /// the source reg along with the FrameIndex of the loaded stack slot. If 734Srgrimes /// not, return 0. This predicate must return 0 if the instruction has 744Srgrimes /// any side effects other than storing to the stack slot. 754Srgrimesunsigned 764SrgrimesXCoreInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 774Srgrimes int &FrameIndex) const { 784Srgrimes int Opcode = MI->getOpcode(); 794Srgrimes if (Opcode == XCore::STWFI) 804Srgrimes { 814Srgrimes if ((MI->getOperand(1).isFI()) && // is a stack slot 824Srgrimes (MI->getOperand(2).isImm()) && // the imm is zero 834Srgrimes (isZeroImm(MI->getOperand(2)))) 844Srgrimes { 854Srgrimes FrameIndex = MI->getOperand(1).getIndex(); 864Srgrimes return MI->getOperand(0).getReg(); 874Srgrimes } 884Srgrimes } 894Srgrimes return 0; 904Srgrimes} 914Srgrimes 924Srgrimes//===----------------------------------------------------------------------===// 934Srgrimes// Branch Analysis 944Srgrimes//===----------------------------------------------------------------------===// 954Srgrimes 964Srgrimesstatic inline bool IsBRU(unsigned BrOpc) { 9712515Sphk return BrOpc == XCore::BRFU_u6 9812515Sphk || BrOpc == XCore::BRFU_lu6 994Srgrimes || BrOpc == XCore::BRBU_u6 1004Srgrimes || BrOpc == XCore::BRBU_lu6; 1014Srgrimes} 1024Srgrimes 1034Srgrimesstatic inline bool IsBRT(unsigned BrOpc) { 1044Srgrimes return BrOpc == XCore::BRFT_ru6 1054Srgrimes || BrOpc == XCore::BRFT_lru6 1064Srgrimes || BrOpc == XCore::BRBT_ru6 1074Srgrimes || BrOpc == XCore::BRBT_lru6; 1084Srgrimes} 1094Srgrimes 1104Srgrimesstatic inline bool IsBRF(unsigned BrOpc) { 11112515Sphk return BrOpc == XCore::BRFF_ru6 1124Srgrimes || BrOpc == XCore::BRFF_lru6 113798Swollman || BrOpc == XCore::BRBF_ru6 1144Srgrimes || BrOpc == XCore::BRBF_lru6; 1154Srgrimes} 1164Srgrimes 1174Srgrimesstatic inline bool IsCondBranch(unsigned BrOpc) { 11812473Sbde return IsBRF(BrOpc) || IsBRT(BrOpc); 1194Srgrimes} 1204Srgrimes 1214Srgrimesstatic inline bool IsBR_JT(unsigned BrOpc) { 1224Srgrimes return BrOpc == XCore::BR_JT 1234Srgrimes || BrOpc == XCore::BR_JT32; 1244Srgrimes} 1254Srgrimes 126798Swollman/// GetCondFromBranchOpc - Return the XCore CC that matches 1274Srgrimes/// the correspondent Branch instruction opcode. 1284Srgrimesstatic XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc) 1294Srgrimes{ 1304Srgrimes if (IsBRT(BrOpc)) { 13112473Sbde return XCore::COND_TRUE; 1324Srgrimes } else if (IsBRF(BrOpc)) { 1334Srgrimes return XCore::COND_FALSE; 1344Srgrimes } else { 1354Srgrimes return XCore::COND_INVALID; 1364Srgrimes } 1374Srgrimes} 1384Srgrimes 1394Srgrimes/// GetCondBranchFromCond - Return the Branch instruction 14012473Sbde/// opcode that matches the cc. 14112473Sbdestatic inline unsigned GetCondBranchFromCond(XCore::CondCode CC) 14212473Sbde{ 14312473Sbde switch (CC) { 14412473Sbde default: llvm_unreachable("Illegal condition code!"); 1454Srgrimes case XCore::COND_TRUE : return XCore::BRFT_lru6; 1464Srgrimes case XCore::COND_FALSE : return XCore::BRFF_lru6; 1474Srgrimes } 1484Srgrimes} 1494Srgrimes 1504Srgrimes/// GetOppositeBranchCondition - Return the inverse of the specified 1514Srgrimes/// condition, e.g. turning COND_E to COND_NE. 1524Srgrimesstatic inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC) 1534Srgrimes{ 1544Srgrimes switch (CC) { 1554Srgrimes default: llvm_unreachable("Illegal condition code!"); 1564Srgrimes case XCore::COND_TRUE : return XCore::COND_FALSE; 1574Srgrimes case XCore::COND_FALSE : return XCore::COND_TRUE; 1584Srgrimes } 1594Srgrimes} 1604Srgrimes 1614Srgrimes/// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 1624Srgrimes/// true if it cannot be understood (e.g. it's a switch dispatch or isn't 1634Srgrimes/// implemented for a target). Upon success, this returns false and returns 1644Srgrimes/// with the following information in various cases: 1654Srgrimes/// 1664Srgrimes/// 1. If this block ends with no branches (it just falls through to its succ) 1674Srgrimes/// just return false, leaving TBB/FBB null. 1684Srgrimes/// 2. If this block ends with only an unconditional branch, it sets TBB to be 1694Srgrimes/// the destination block. 1704Srgrimes/// 3. If this block ends with an conditional branch and it falls through to 1714Srgrimes/// an successor block, it sets TBB to be the branch destination block and a 1724Srgrimes/// list of operands that evaluate the condition. These 1734Srgrimes/// operands can be passed to other TargetInstrInfo methods to create new 174/// branches. 175/// 4. If this block ends with an conditional branch and an unconditional 176/// block, it returns the 'true' destination in TBB, the 'false' destination 177/// in FBB, and a list of operands that evaluate the condition. These 178/// operands can be passed to other TargetInstrInfo methods to create new 179/// branches. 180/// 181/// Note that RemoveBranch and InsertBranch must be implemented to support 182/// cases where this method returns success. 183/// 184bool 185XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 186 MachineBasicBlock *&FBB, 187 SmallVectorImpl<MachineOperand> &Cond, 188 bool AllowModify) const { 189 // If the block has no terminators, it just falls into the block after it. 190 MachineBasicBlock::iterator I = MBB.end(); 191 if (I == MBB.begin()) 192 return false; 193 --I; 194 while (I->isDebugValue()) { 195 if (I == MBB.begin()) 196 return false; 197 --I; 198 } 199 if (!isUnpredicatedTerminator(I)) 200 return false; 201 202 // Get the last instruction in the block. 203 MachineInstr *LastInst = I; 204 205 // If there is only one terminator instruction, process it. 206 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 207 if (IsBRU(LastInst->getOpcode())) { 208 TBB = LastInst->getOperand(0).getMBB(); 209 return false; 210 } 211 212 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); 213 if (BranchCode == XCore::COND_INVALID) 214 return true; // Can't handle indirect branch. 215 216 // Conditional branch 217 // Block ends with fall-through condbranch. 218 219 TBB = LastInst->getOperand(1).getMBB(); 220 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 221 Cond.push_back(LastInst->getOperand(0)); 222 return false; 223 } 224 225 // Get the instruction before it if it's a terminator. 226 MachineInstr *SecondLastInst = I; 227 228 // If there are three terminators, we don't know what sort of block this is. 229 if (SecondLastInst && I != MBB.begin() && 230 isUnpredicatedTerminator(--I)) 231 return true; 232 233 unsigned SecondLastOpc = SecondLastInst->getOpcode(); 234 XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc); 235 236 // If the block ends with conditional branch followed by unconditional, 237 // handle it. 238 if (BranchCode != XCore::COND_INVALID 239 && IsBRU(LastInst->getOpcode())) { 240 241 TBB = SecondLastInst->getOperand(1).getMBB(); 242 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 243 Cond.push_back(SecondLastInst->getOperand(0)); 244 245 FBB = LastInst->getOperand(0).getMBB(); 246 return false; 247 } 248 249 // If the block ends with two unconditional branches, handle it. The second 250 // one is not executed, so remove it. 251 if (IsBRU(SecondLastInst->getOpcode()) && 252 IsBRU(LastInst->getOpcode())) { 253 TBB = SecondLastInst->getOperand(0).getMBB(); 254 I = LastInst; 255 if (AllowModify) 256 I->eraseFromParent(); 257 return false; 258 } 259 260 // Likewise if it ends with a branch table followed by an unconditional branch. 261 if (IsBR_JT(SecondLastInst->getOpcode()) && IsBRU(LastInst->getOpcode())) { 262 I = LastInst; 263 if (AllowModify) 264 I->eraseFromParent(); 265 return true; 266 } 267 268 // Otherwise, can't handle this. 269 return true; 270} 271 272unsigned 273XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, 274 MachineBasicBlock *FBB, 275 const SmallVectorImpl<MachineOperand> &Cond, 276 DebugLoc DL)const{ 277 // Shouldn't be a fall through. 278 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 279 assert((Cond.size() == 2 || Cond.size() == 0) && 280 "Unexpected number of components!"); 281 282 if (FBB == 0) { // One way branch. 283 if (Cond.empty()) { 284 // Unconditional branch 285 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB); 286 } else { 287 // Conditional branch. 288 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); 289 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) 290 .addMBB(TBB); 291 } 292 return 1; 293 } 294 295 // Two-way Conditional branch. 296 assert(Cond.size() == 2 && "Unexpected number of components!"); 297 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); 298 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) 299 .addMBB(TBB); 300 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB); 301 return 2; 302} 303 304unsigned 305XCoreInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 306 MachineBasicBlock::iterator I = MBB.end(); 307 if (I == MBB.begin()) return 0; 308 --I; 309 while (I->isDebugValue()) { 310 if (I == MBB.begin()) 311 return 0; 312 --I; 313 } 314 if (!IsBRU(I->getOpcode()) && !IsCondBranch(I->getOpcode())) 315 return 0; 316 317 // Remove the branch. 318 I->eraseFromParent(); 319 320 I = MBB.end(); 321 322 if (I == MBB.begin()) return 1; 323 --I; 324 if (!IsCondBranch(I->getOpcode())) 325 return 1; 326 327 // Remove the branch. 328 I->eraseFromParent(); 329 return 2; 330} 331 332void XCoreInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 333 MachineBasicBlock::iterator I, DebugLoc DL, 334 unsigned DestReg, unsigned SrcReg, 335 bool KillSrc) const { 336 bool GRDest = XCore::GRRegsRegClass.contains(DestReg); 337 bool GRSrc = XCore::GRRegsRegClass.contains(SrcReg); 338 339 if (GRDest && GRSrc) { 340 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg) 341 .addReg(SrcReg, getKillRegState(KillSrc)) 342 .addImm(0); 343 return; 344 } 345 346 if (GRDest && SrcReg == XCore::SP) { 347 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0); 348 return; 349 } 350 351 if (DestReg == XCore::SP && GRSrc) { 352 BuildMI(MBB, I, DL, get(XCore::SETSP_1r)) 353 .addReg(SrcReg, getKillRegState(KillSrc)); 354 return; 355 } 356 llvm_unreachable("Impossible reg-to-reg copy"); 357} 358 359void XCoreInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 360 MachineBasicBlock::iterator I, 361 unsigned SrcReg, bool isKill, 362 int FrameIndex, 363 const TargetRegisterClass *RC, 364 const TargetRegisterInfo *TRI) const 365{ 366 DebugLoc DL; 367 if (I != MBB.end()) DL = I->getDebugLoc(); 368 BuildMI(MBB, I, DL, get(XCore::STWFI)) 369 .addReg(SrcReg, getKillRegState(isKill)) 370 .addFrameIndex(FrameIndex) 371 .addImm(0); 372} 373 374void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 375 MachineBasicBlock::iterator I, 376 unsigned DestReg, int FrameIndex, 377 const TargetRegisterClass *RC, 378 const TargetRegisterInfo *TRI) const 379{ 380 DebugLoc DL; 381 if (I != MBB.end()) DL = I->getDebugLoc(); 382 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg) 383 .addFrameIndex(FrameIndex) 384 .addImm(0); 385} 386 387bool XCoreInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 388 MachineBasicBlock::iterator MI, 389 const std::vector<CalleeSavedInfo> &CSI, 390 const TargetRegisterInfo *TRI) const { 391 if (CSI.empty()) { 392 return true; 393 } 394 MachineFunction *MF = MBB.getParent(); 395 XCoreFunctionInfo *XFI = MF->getInfo<XCoreFunctionInfo>(); 396 397 bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(*MF); 398 399 DebugLoc DL; 400 if (MI != MBB.end()) DL = MI->getDebugLoc(); 401 402 for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin(); 403 it != CSI.end(); ++it) { 404 // Add the callee-saved register as live-in. It's killed at the spill. 405 MBB.addLiveIn(it->getReg()); 406 407 unsigned Reg = it->getReg(); 408 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 409 storeRegToStackSlot(MBB, MI, Reg, true, 410 it->getFrameIdx(), RC, &RI); 411 if (emitFrameMoves) { 412 MCSymbol *SaveLabel = MF->getContext().CreateTempSymbol(); 413 BuildMI(MBB, MI, DL, get(XCore::PROLOG_LABEL)).addSym(SaveLabel); 414 XFI->getSpillLabels().push_back(std::make_pair(SaveLabel, *it)); 415 } 416 } 417 return true; 418} 419 420bool XCoreInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 421 MachineBasicBlock::iterator MI, 422 const std::vector<CalleeSavedInfo> &CSI, 423 const TargetRegisterInfo *TRI) const 424{ 425 bool AtStart = MI == MBB.begin(); 426 MachineBasicBlock::iterator BeforeI = MI; 427 if (!AtStart) 428 --BeforeI; 429 for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin(); 430 it != CSI.end(); ++it) { 431 unsigned Reg = it->getReg(); 432 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 433 loadRegFromStackSlot(MBB, MI, it->getReg(), 434 it->getFrameIdx(), 435 RC, &RI); 436 assert(MI != MBB.begin() && 437 "loadRegFromStackSlot didn't insert any code!"); 438 // Insert in reverse order. loadRegFromStackSlot can insert multiple 439 // instructions. 440 if (AtStart) 441 MI = MBB.begin(); 442 else { 443 MI = BeforeI; 444 ++MI; 445 } 446 } 447 return true; 448} 449 450/// ReverseBranchCondition - Return the inverse opcode of the 451/// specified Branch instruction. 452bool XCoreInstrInfo:: 453ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const 454{ 455 assert((Cond.size() == 2) && 456 "Invalid XCore branch condition!"); 457 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm())); 458 return false; 459} 460