XCoreISelLowering.cpp revision 201360
1193323Sed//===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ------===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file implements the XCoreTargetLowering class. 11193323Sed// 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14193323Sed#define DEBUG_TYPE "xcore-lower" 15193323Sed 16193323Sed#include "XCoreISelLowering.h" 17193323Sed#include "XCoreMachineFunctionInfo.h" 18193323Sed#include "XCore.h" 19198090Srdivacky#include "XCoreTargetObjectFile.h" 20193323Sed#include "XCoreTargetMachine.h" 21193323Sed#include "XCoreSubtarget.h" 22193323Sed#include "llvm/DerivedTypes.h" 23193323Sed#include "llvm/Function.h" 24193323Sed#include "llvm/Intrinsics.h" 25193323Sed#include "llvm/CallingConv.h" 26193323Sed#include "llvm/GlobalVariable.h" 27193323Sed#include "llvm/GlobalAlias.h" 28193323Sed#include "llvm/CodeGen/CallingConvLower.h" 29193323Sed#include "llvm/CodeGen/MachineFrameInfo.h" 30193323Sed#include "llvm/CodeGen/MachineFunction.h" 31193323Sed#include "llvm/CodeGen/MachineInstrBuilder.h" 32193323Sed#include "llvm/CodeGen/MachineRegisterInfo.h" 33193323Sed#include "llvm/CodeGen/SelectionDAGISel.h" 34193323Sed#include "llvm/CodeGen/ValueTypes.h" 35193323Sed#include "llvm/Support/Debug.h" 36198090Srdivacky#include "llvm/Support/ErrorHandling.h" 37198090Srdivacky#include "llvm/Support/raw_ostream.h" 38193323Sed#include "llvm/ADT/VectorExtras.h" 39193323Sed#include <queue> 40193323Sed#include <set> 41193323Sedusing namespace llvm; 42193323Sed 43193323Sedconst char *XCoreTargetLowering:: 44193323SedgetTargetNodeName(unsigned Opcode) const 45193323Sed{ 46193323Sed switch (Opcode) 47193323Sed { 48193323Sed case XCoreISD::BL : return "XCoreISD::BL"; 49193323Sed case XCoreISD::PCRelativeWrapper : return "XCoreISD::PCRelativeWrapper"; 50193323Sed case XCoreISD::DPRelativeWrapper : return "XCoreISD::DPRelativeWrapper"; 51193323Sed case XCoreISD::CPRelativeWrapper : return "XCoreISD::CPRelativeWrapper"; 52193323Sed case XCoreISD::STWSP : return "XCoreISD::STWSP"; 53193323Sed case XCoreISD::RETSP : return "XCoreISD::RETSP"; 54198090Srdivacky case XCoreISD::LADD : return "XCoreISD::LADD"; 55198090Srdivacky case XCoreISD::LSUB : return "XCoreISD::LSUB"; 56193323Sed default : return NULL; 57193323Sed } 58193323Sed} 59193323Sed 60193323SedXCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM) 61198090Srdivacky : TargetLowering(XTM, new XCoreTargetObjectFile()), 62193323Sed TM(XTM), 63193323Sed Subtarget(*XTM.getSubtargetImpl()) { 64193323Sed 65193323Sed // Set up the register classes. 66193323Sed addRegisterClass(MVT::i32, XCore::GRRegsRegisterClass); 67193323Sed 68193323Sed // Compute derived properties from the register classes 69193323Sed computeRegisterProperties(); 70193323Sed 71193323Sed // Division is expensive 72193323Sed setIntDivIsCheap(false); 73193323Sed 74193323Sed setShiftAmountType(MVT::i32); 75193323Sed setStackPointerRegisterToSaveRestore(XCore::SP); 76193323Sed 77193323Sed setSchedulingPreference(SchedulingForRegPressure); 78193323Sed 79193323Sed // Use i32 for setcc operations results (slt, sgt, ...). 80193323Sed setBooleanContents(ZeroOrOneBooleanContent); 81193323Sed 82193323Sed // XCore does not have the NodeTypes below. 83193323Sed setOperationAction(ISD::BR_CC, MVT::Other, Expand); 84193323Sed setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 85193323Sed setOperationAction(ISD::ADDC, MVT::i32, Expand); 86193323Sed setOperationAction(ISD::ADDE, MVT::i32, Expand); 87193323Sed setOperationAction(ISD::SUBC, MVT::i32, Expand); 88193323Sed setOperationAction(ISD::SUBE, MVT::i32, Expand); 89193323Sed 90193323Sed // Stop the combiner recombining select and set_cc 91193323Sed setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 92193323Sed 93193323Sed // 64bit 94198090Srdivacky setOperationAction(ISD::ADD, MVT::i64, Custom); 95198090Srdivacky setOperationAction(ISD::SUB, MVT::i64, Custom); 96193323Sed setOperationAction(ISD::MULHS, MVT::i32, Expand); 97193323Sed setOperationAction(ISD::MULHU, MVT::i32, Expand); 98193323Sed setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 99193323Sed setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 100193323Sed setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 101193323Sed 102193323Sed // Bit Manipulation 103193323Sed setOperationAction(ISD::CTPOP, MVT::i32, Expand); 104193323Sed setOperationAction(ISD::ROTL , MVT::i32, Expand); 105193323Sed setOperationAction(ISD::ROTR , MVT::i32, Expand); 106193323Sed 107193323Sed setOperationAction(ISD::TRAP, MVT::Other, Legal); 108193323Sed 109193323Sed // Expand jump tables for now 110193323Sed setOperationAction(ISD::BR_JT, MVT::Other, Expand); 111193323Sed setOperationAction(ISD::JumpTable, MVT::i32, Custom); 112193323Sed 113193323Sed setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 114199511Srdivacky setOperationAction(ISD::BlockAddress, MVT::i32 , Custom); 115199511Srdivacky 116193323Sed // Thread Local Storage 117193323Sed setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 118193323Sed 119193323Sed // Conversion of i64 -> double produces constantpool nodes 120193323Sed setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 121193323Sed 122193323Sed // Loads 123193323Sed setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 124193323Sed setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 125193323Sed setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 126193323Sed 127193323Sed setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); 128193323Sed setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand); 129198090Srdivacky 130198090Srdivacky // Custom expand misaligned loads / stores. 131198090Srdivacky setOperationAction(ISD::LOAD, MVT::i32, Custom); 132198090Srdivacky setOperationAction(ISD::STORE, MVT::i32, Custom); 133198090Srdivacky 134193323Sed // Varargs 135193323Sed setOperationAction(ISD::VAEND, MVT::Other, Expand); 136193323Sed setOperationAction(ISD::VACOPY, MVT::Other, Expand); 137193323Sed setOperationAction(ISD::VAARG, MVT::Other, Custom); 138193323Sed setOperationAction(ISD::VASTART, MVT::Other, Custom); 139193323Sed 140193323Sed // Dynamic stack 141193323Sed setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 142193323Sed setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 143193323Sed setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 144193323Sed 145198090Srdivacky maxStoresPerMemset = 4; 146198090Srdivacky maxStoresPerMemmove = maxStoresPerMemcpy = 2; 147198090Srdivacky 148198090Srdivacky // We have target-specific dag combine patterns for the following nodes: 149198090Srdivacky setTargetDAGCombine(ISD::STORE); 150193323Sed} 151193323Sed 152193323SedSDValue XCoreTargetLowering:: 153193323SedLowerOperation(SDValue Op, SelectionDAG &DAG) { 154193323Sed switch (Op.getOpcode()) 155193323Sed { 156193323Sed case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 157193323Sed case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 158199511Srdivacky case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 159193323Sed case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 160193323Sed case ISD::JumpTable: return LowerJumpTable(Op, DAG); 161198090Srdivacky case ISD::LOAD: return LowerLOAD(Op, DAG); 162198090Srdivacky case ISD::STORE: return LowerSTORE(Op, DAG); 163193323Sed case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 164193323Sed case ISD::VAARG: return LowerVAARG(Op, DAG); 165193323Sed case ISD::VASTART: return LowerVASTART(Op, DAG); 166193323Sed // FIXME: Remove these when LegalizeDAGTypes lands. 167193323Sed case ISD::ADD: 168193323Sed case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG); 169193323Sed case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 170193323Sed default: 171198090Srdivacky llvm_unreachable("unimplemented operand"); 172193323Sed return SDValue(); 173193323Sed } 174193323Sed} 175193323Sed 176193323Sed/// ReplaceNodeResults - Replace the results of node with an illegal result 177193323Sed/// type with new values built out of custom code. 178193323Sedvoid XCoreTargetLowering::ReplaceNodeResults(SDNode *N, 179193323Sed SmallVectorImpl<SDValue>&Results, 180193323Sed SelectionDAG &DAG) { 181193323Sed switch (N->getOpcode()) { 182193323Sed default: 183198090Srdivacky llvm_unreachable("Don't know how to custom expand this!"); 184193323Sed return; 185193323Sed case ISD::ADD: 186193323Sed case ISD::SUB: 187193323Sed Results.push_back(ExpandADDSUB(N, DAG)); 188193323Sed return; 189193323Sed } 190193323Sed} 191193323Sed 192195340Sed/// getFunctionAlignment - Return the Log2 alignment of this function. 193195340Sedunsigned XCoreTargetLowering:: 194195340SedgetFunctionAlignment(const Function *) const { 195195340Sed return 1; 196195340Sed} 197195340Sed 198193323Sed//===----------------------------------------------------------------------===// 199193323Sed// Misc Lower Operation implementation 200193323Sed//===----------------------------------------------------------------------===// 201193323Sed 202193323SedSDValue XCoreTargetLowering:: 203193323SedLowerSELECT_CC(SDValue Op, SelectionDAG &DAG) 204193323Sed{ 205193323Sed DebugLoc dl = Op.getDebugLoc(); 206193323Sed SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i32, Op.getOperand(2), 207193323Sed Op.getOperand(3), Op.getOperand(4)); 208193323Sed return DAG.getNode(ISD::SELECT, dl, MVT::i32, Cond, Op.getOperand(0), 209193323Sed Op.getOperand(1)); 210193323Sed} 211193323Sed 212193323SedSDValue XCoreTargetLowering:: 213193323SedgetGlobalAddressWrapper(SDValue GA, GlobalValue *GV, SelectionDAG &DAG) 214193323Sed{ 215193323Sed // FIXME there is no actual debug info here 216193323Sed DebugLoc dl = GA.getDebugLoc(); 217193323Sed if (isa<Function>(GV)) { 218193323Sed return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA); 219193323Sed } 220198090Srdivacky const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); 221198090Srdivacky if (!GVar) { 222198090Srdivacky // If GV is an alias then use the aliasee to determine constness 223198090Srdivacky if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 224198090Srdivacky GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal()); 225198090Srdivacky } 226198090Srdivacky bool isConst = GVar && GVar->isConstant(); 227198090Srdivacky if (isConst) { 228198090Srdivacky return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA); 229198090Srdivacky } 230193323Sed return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA); 231193323Sed} 232193323Sed 233193323SedSDValue XCoreTargetLowering:: 234193323SedLowerGlobalAddress(SDValue Op, SelectionDAG &DAG) 235193323Sed{ 236193323Sed GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 237193323Sed SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 238193323Sed // If it's a debug information descriptor, don't mess with it. 239193323Sed if (DAG.isVerifiedDebugInfoDesc(Op)) 240193323Sed return GA; 241193323Sed return getGlobalAddressWrapper(GA, GV, DAG); 242193323Sed} 243193323Sed 244193323Sedstatic inline SDValue BuildGetId(SelectionDAG &DAG, DebugLoc dl) { 245193323Sed return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32, 246193323Sed DAG.getConstant(Intrinsic::xcore_getid, MVT::i32)); 247193323Sed} 248193323Sed 249193323Sedstatic inline bool isZeroLengthArray(const Type *Ty) { 250193323Sed const ArrayType *AT = dyn_cast_or_null<ArrayType>(Ty); 251193323Sed return AT && (AT->getNumElements() == 0); 252193323Sed} 253193323Sed 254193323SedSDValue XCoreTargetLowering:: 255193323SedLowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) 256193323Sed{ 257193323Sed // FIXME there isn't really debug info here 258193323Sed DebugLoc dl = Op.getDebugLoc(); 259193323Sed // transform to label + getid() * size 260193323Sed GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 261193323Sed SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 262193323Sed const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); 263193323Sed if (!GVar) { 264193323Sed // If GV is an alias then use the aliasee to determine size 265193323Sed if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 266193323Sed GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal()); 267193323Sed } 268193323Sed if (! GVar) { 269198090Srdivacky llvm_unreachable("Thread local object not a GlobalVariable?"); 270193323Sed return SDValue(); 271193323Sed } 272193323Sed const Type *Ty = cast<PointerType>(GV->getType())->getElementType(); 273193323Sed if (!Ty->isSized() || isZeroLengthArray(Ty)) { 274198090Srdivacky#ifndef NDEBUG 275198090Srdivacky errs() << "Size of thread local object " << GVar->getName() 276198090Srdivacky << " is unknown\n"; 277198090Srdivacky#endif 278198090Srdivacky llvm_unreachable(0); 279193323Sed } 280193323Sed SDValue base = getGlobalAddressWrapper(GA, GV, DAG); 281193323Sed const TargetData *TD = TM.getTargetData(); 282193323Sed unsigned Size = TD->getTypeAllocSize(Ty); 283193323Sed SDValue offset = DAG.getNode(ISD::MUL, dl, MVT::i32, BuildGetId(DAG, dl), 284193323Sed DAG.getConstant(Size, MVT::i32)); 285193323Sed return DAG.getNode(ISD::ADD, dl, MVT::i32, base, offset); 286193323Sed} 287193323Sed 288193323SedSDValue XCoreTargetLowering:: 289199511SrdivackyLowerBlockAddress(SDValue Op, SelectionDAG &DAG) 290199511Srdivacky{ 291199511Srdivacky DebugLoc DL = Op.getDebugLoc(); 292199511Srdivacky 293199511Srdivacky BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 294199989Srdivacky SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), /*isTarget=*/true); 295199511Srdivacky 296199511Srdivacky return DAG.getNode(XCoreISD::PCRelativeWrapper, DL, getPointerTy(), Result); 297199511Srdivacky} 298199511Srdivacky 299199511SrdivackySDValue XCoreTargetLowering:: 300193323SedLowerConstantPool(SDValue Op, SelectionDAG &DAG) 301193323Sed{ 302193323Sed ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 303193323Sed // FIXME there isn't really debug info here 304193323Sed DebugLoc dl = CP->getDebugLoc(); 305198090Srdivacky EVT PtrVT = Op.getValueType(); 306198090Srdivacky SDValue Res; 307198090Srdivacky if (CP->isMachineConstantPoolEntry()) { 308198090Srdivacky Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, 309198090Srdivacky CP->getAlignment()); 310193323Sed } else { 311198090Srdivacky Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, 312198090Srdivacky CP->getAlignment()); 313193323Sed } 314198090Srdivacky return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res); 315193323Sed} 316193323Sed 317193323SedSDValue XCoreTargetLowering:: 318193323SedLowerJumpTable(SDValue Op, SelectionDAG &DAG) 319193323Sed{ 320193323Sed // FIXME there isn't really debug info here 321193323Sed DebugLoc dl = Op.getDebugLoc(); 322198090Srdivacky EVT PtrVT = Op.getValueType(); 323193323Sed JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 324193323Sed SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); 325193323Sed return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, JTI); 326193323Sed} 327193323Sed 328198090Srdivackystatic bool 329198090SrdivackyIsWordAlignedBasePlusConstantOffset(SDValue Addr, SDValue &AlignedBase, 330198090Srdivacky int64_t &Offset) 331198090Srdivacky{ 332198090Srdivacky if (Addr.getOpcode() != ISD::ADD) { 333198090Srdivacky return false; 334198090Srdivacky } 335198090Srdivacky ConstantSDNode *CN = 0; 336198090Srdivacky if (!(CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) { 337198090Srdivacky return false; 338198090Srdivacky } 339198090Srdivacky int64_t off = CN->getSExtValue(); 340198090Srdivacky const SDValue &Base = Addr.getOperand(0); 341198090Srdivacky const SDValue *Root = &Base; 342198090Srdivacky if (Base.getOpcode() == ISD::ADD && 343198090Srdivacky Base.getOperand(1).getOpcode() == ISD::SHL) { 344198090Srdivacky ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Base.getOperand(1) 345198090Srdivacky .getOperand(1)); 346198090Srdivacky if (CN && (CN->getSExtValue() >= 2)) { 347198090Srdivacky Root = &Base.getOperand(0); 348198090Srdivacky } 349198090Srdivacky } 350198090Srdivacky if (isa<FrameIndexSDNode>(*Root)) { 351198090Srdivacky // All frame indicies are word aligned 352198090Srdivacky AlignedBase = Base; 353198090Srdivacky Offset = off; 354198090Srdivacky return true; 355198090Srdivacky } 356198090Srdivacky if (Root->getOpcode() == XCoreISD::DPRelativeWrapper || 357198090Srdivacky Root->getOpcode() == XCoreISD::CPRelativeWrapper) { 358198090Srdivacky // All dp / cp relative addresses are word aligned 359198090Srdivacky AlignedBase = Base; 360198090Srdivacky Offset = off; 361198090Srdivacky return true; 362198090Srdivacky } 363198090Srdivacky return false; 364198090Srdivacky} 365198090Srdivacky 366193323SedSDValue XCoreTargetLowering:: 367198090SrdivackyLowerLOAD(SDValue Op, SelectionDAG &DAG) 368198090Srdivacky{ 369198090Srdivacky LoadSDNode *LD = cast<LoadSDNode>(Op); 370198090Srdivacky assert(LD->getExtensionType() == ISD::NON_EXTLOAD && 371198090Srdivacky "Unexpected extension type"); 372198090Srdivacky assert(LD->getMemoryVT() == MVT::i32 && "Unexpected load EVT"); 373198090Srdivacky if (allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 374198090Srdivacky return SDValue(); 375198090Srdivacky } 376198090Srdivacky unsigned ABIAlignment = getTargetData()-> 377198090Srdivacky getABITypeAlignment(LD->getMemoryVT().getTypeForEVT(*DAG.getContext())); 378198090Srdivacky // Leave aligned load alone. 379198090Srdivacky if (LD->getAlignment() >= ABIAlignment) { 380198090Srdivacky return SDValue(); 381198090Srdivacky } 382198090Srdivacky SDValue Chain = LD->getChain(); 383198090Srdivacky SDValue BasePtr = LD->getBasePtr(); 384198090Srdivacky DebugLoc dl = Op.getDebugLoc(); 385198090Srdivacky 386198090Srdivacky SDValue Base; 387198090Srdivacky int64_t Offset; 388198090Srdivacky if (!LD->isVolatile() && 389198090Srdivacky IsWordAlignedBasePlusConstantOffset(BasePtr, Base, Offset)) { 390198090Srdivacky if (Offset % 4 == 0) { 391198090Srdivacky // We've managed to infer better alignment information than the load 392198090Srdivacky // already has. Use an aligned load. 393198090Srdivacky return DAG.getLoad(getPointerTy(), dl, Chain, BasePtr, NULL, 4); 394198090Srdivacky } 395198090Srdivacky // Lower to 396198090Srdivacky // ldw low, base[offset >> 2] 397198090Srdivacky // ldw high, base[(offset >> 2) + 1] 398198090Srdivacky // shr low_shifted, low, (offset & 0x3) * 8 399198090Srdivacky // shl high_shifted, high, 32 - (offset & 0x3) * 8 400198090Srdivacky // or result, low_shifted, high_shifted 401198090Srdivacky SDValue LowOffset = DAG.getConstant(Offset & ~0x3, MVT::i32); 402198090Srdivacky SDValue HighOffset = DAG.getConstant((Offset & ~0x3) + 4, MVT::i32); 403198090Srdivacky SDValue LowShift = DAG.getConstant((Offset & 0x3) * 8, MVT::i32); 404198090Srdivacky SDValue HighShift = DAG.getConstant(32 - (Offset & 0x3) * 8, MVT::i32); 405198090Srdivacky 406198090Srdivacky SDValue LowAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Base, LowOffset); 407198090Srdivacky SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Base, HighOffset); 408198090Srdivacky 409198090Srdivacky SDValue Low = DAG.getLoad(getPointerTy(), dl, Chain, 410198090Srdivacky LowAddr, NULL, 4); 411198090Srdivacky SDValue High = DAG.getLoad(getPointerTy(), dl, Chain, 412198090Srdivacky HighAddr, NULL, 4); 413198090Srdivacky SDValue LowShifted = DAG.getNode(ISD::SRL, dl, MVT::i32, Low, LowShift); 414198090Srdivacky SDValue HighShifted = DAG.getNode(ISD::SHL, dl, MVT::i32, High, HighShift); 415198090Srdivacky SDValue Result = DAG.getNode(ISD::OR, dl, MVT::i32, LowShifted, HighShifted); 416198090Srdivacky Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Low.getValue(1), 417198090Srdivacky High.getValue(1)); 418198090Srdivacky SDValue Ops[] = { Result, Chain }; 419198090Srdivacky return DAG.getMergeValues(Ops, 2, dl); 420198090Srdivacky } 421198090Srdivacky 422198090Srdivacky if (LD->getAlignment() == 2) { 423198090Srdivacky int SVOffset = LD->getSrcValueOffset(); 424198090Srdivacky SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain, 425198090Srdivacky BasePtr, LD->getSrcValue(), SVOffset, MVT::i16, 426198090Srdivacky LD->isVolatile(), 2); 427198090Srdivacky SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr, 428198090Srdivacky DAG.getConstant(2, MVT::i32)); 429198090Srdivacky SDValue High = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::i32, Chain, 430198090Srdivacky HighAddr, LD->getSrcValue(), SVOffset + 2, 431198090Srdivacky MVT::i16, LD->isVolatile(), 2); 432198090Srdivacky SDValue HighShifted = DAG.getNode(ISD::SHL, dl, MVT::i32, High, 433198090Srdivacky DAG.getConstant(16, MVT::i32)); 434198090Srdivacky SDValue Result = DAG.getNode(ISD::OR, dl, MVT::i32, Low, HighShifted); 435198090Srdivacky Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Low.getValue(1), 436198090Srdivacky High.getValue(1)); 437198090Srdivacky SDValue Ops[] = { Result, Chain }; 438198090Srdivacky return DAG.getMergeValues(Ops, 2, dl); 439198090Srdivacky } 440198090Srdivacky 441198090Srdivacky // Lower to a call to __misaligned_load(BasePtr). 442198090Srdivacky const Type *IntPtrTy = getTargetData()->getIntPtrType(*DAG.getContext()); 443198090Srdivacky TargetLowering::ArgListTy Args; 444198090Srdivacky TargetLowering::ArgListEntry Entry; 445198090Srdivacky 446198090Srdivacky Entry.Ty = IntPtrTy; 447198090Srdivacky Entry.Node = BasePtr; 448198090Srdivacky Args.push_back(Entry); 449198090Srdivacky 450198090Srdivacky std::pair<SDValue, SDValue> CallResult = 451198090Srdivacky LowerCallTo(Chain, IntPtrTy, false, false, 452198090Srdivacky false, false, 0, CallingConv::C, false, 453198090Srdivacky /*isReturnValueUsed=*/true, 454198090Srdivacky DAG.getExternalSymbol("__misaligned_load", getPointerTy()), 455201360Srdivacky Args, DAG, dl, DAG.GetOrdering(Chain.getNode())); 456198090Srdivacky 457198090Srdivacky SDValue Ops[] = 458198090Srdivacky { CallResult.first, CallResult.second }; 459198090Srdivacky 460198090Srdivacky return DAG.getMergeValues(Ops, 2, dl); 461198090Srdivacky} 462198090Srdivacky 463198090SrdivackySDValue XCoreTargetLowering:: 464198090SrdivackyLowerSTORE(SDValue Op, SelectionDAG &DAG) 465198090Srdivacky{ 466198090Srdivacky StoreSDNode *ST = cast<StoreSDNode>(Op); 467198090Srdivacky assert(!ST->isTruncatingStore() && "Unexpected store type"); 468198090Srdivacky assert(ST->getMemoryVT() == MVT::i32 && "Unexpected store EVT"); 469198090Srdivacky if (allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 470198090Srdivacky return SDValue(); 471198090Srdivacky } 472198090Srdivacky unsigned ABIAlignment = getTargetData()-> 473198090Srdivacky getABITypeAlignment(ST->getMemoryVT().getTypeForEVT(*DAG.getContext())); 474198090Srdivacky // Leave aligned store alone. 475198090Srdivacky if (ST->getAlignment() >= ABIAlignment) { 476198090Srdivacky return SDValue(); 477198090Srdivacky } 478198090Srdivacky SDValue Chain = ST->getChain(); 479198090Srdivacky SDValue BasePtr = ST->getBasePtr(); 480198090Srdivacky SDValue Value = ST->getValue(); 481198090Srdivacky DebugLoc dl = Op.getDebugLoc(); 482198090Srdivacky 483198090Srdivacky if (ST->getAlignment() == 2) { 484198090Srdivacky int SVOffset = ST->getSrcValueOffset(); 485198090Srdivacky SDValue Low = Value; 486198090Srdivacky SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value, 487198090Srdivacky DAG.getConstant(16, MVT::i32)); 488198090Srdivacky SDValue StoreLow = DAG.getTruncStore(Chain, dl, Low, BasePtr, 489198090Srdivacky ST->getSrcValue(), SVOffset, MVT::i16, 490198090Srdivacky ST->isVolatile(), 2); 491198090Srdivacky SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr, 492198090Srdivacky DAG.getConstant(2, MVT::i32)); 493198090Srdivacky SDValue StoreHigh = DAG.getTruncStore(Chain, dl, High, HighAddr, 494198090Srdivacky ST->getSrcValue(), SVOffset + 2, 495198090Srdivacky MVT::i16, ST->isVolatile(), 2); 496198090Srdivacky return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, StoreLow, StoreHigh); 497198090Srdivacky } 498198090Srdivacky 499198090Srdivacky // Lower to a call to __misaligned_store(BasePtr, Value). 500198090Srdivacky const Type *IntPtrTy = getTargetData()->getIntPtrType(*DAG.getContext()); 501198090Srdivacky TargetLowering::ArgListTy Args; 502198090Srdivacky TargetLowering::ArgListEntry Entry; 503198090Srdivacky 504198090Srdivacky Entry.Ty = IntPtrTy; 505198090Srdivacky Entry.Node = BasePtr; 506198090Srdivacky Args.push_back(Entry); 507198090Srdivacky 508198090Srdivacky Entry.Node = Value; 509198090Srdivacky Args.push_back(Entry); 510198090Srdivacky 511198090Srdivacky std::pair<SDValue, SDValue> CallResult = 512198090Srdivacky LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()), false, false, 513198090Srdivacky false, false, 0, CallingConv::C, false, 514198090Srdivacky /*isReturnValueUsed=*/true, 515198090Srdivacky DAG.getExternalSymbol("__misaligned_store", getPointerTy()), 516201360Srdivacky Args, DAG, dl, DAG.GetOrdering(Chain.getNode())); 517198090Srdivacky 518198090Srdivacky return CallResult.second; 519198090Srdivacky} 520198090Srdivacky 521198090SrdivackySDValue XCoreTargetLowering:: 522193323SedExpandADDSUB(SDNode *N, SelectionDAG &DAG) 523193323Sed{ 524193323Sed assert(N->getValueType(0) == MVT::i64 && 525193323Sed (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && 526193323Sed "Unknown operand to lower!"); 527193323Sed DebugLoc dl = N->getDebugLoc(); 528193323Sed 529193323Sed // Extract components 530193323Sed SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 531193323Sed N->getOperand(0), DAG.getConstant(0, MVT::i32)); 532193323Sed SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 533193323Sed N->getOperand(0), DAG.getConstant(1, MVT::i32)); 534193323Sed SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 535193323Sed N->getOperand(1), DAG.getConstant(0, MVT::i32)); 536193323Sed SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 537193323Sed N->getOperand(1), DAG.getConstant(1, MVT::i32)); 538193323Sed 539193323Sed // Expand 540193323Sed unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD : 541193323Sed XCoreISD::LSUB; 542193323Sed SDValue Zero = DAG.getConstant(0, MVT::i32); 543193323Sed SDValue Carry = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), 544193323Sed LHSL, RHSL, Zero); 545193323Sed SDValue Lo(Carry.getNode(), 1); 546193323Sed 547193323Sed SDValue Ignored = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), 548193323Sed LHSH, RHSH, Carry); 549193323Sed SDValue Hi(Ignored.getNode(), 1); 550193323Sed // Merge the pieces 551193323Sed return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 552193323Sed} 553193323Sed 554193323SedSDValue XCoreTargetLowering:: 555193323SedLowerVAARG(SDValue Op, SelectionDAG &DAG) 556193323Sed{ 557198090Srdivacky llvm_unreachable("unimplemented"); 558193323Sed // FIX Arguments passed by reference need a extra dereference. 559193323Sed SDNode *Node = Op.getNode(); 560193323Sed DebugLoc dl = Node->getDebugLoc(); 561193323Sed const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 562198090Srdivacky EVT VT = Node->getValueType(0); 563193323Sed SDValue VAList = DAG.getLoad(getPointerTy(), dl, Node->getOperand(0), 564193323Sed Node->getOperand(1), V, 0); 565193323Sed // Increment the pointer, VAList, to the next vararg 566193323Sed SDValue Tmp3 = DAG.getNode(ISD::ADD, dl, getPointerTy(), VAList, 567193323Sed DAG.getConstant(VT.getSizeInBits(), 568193323Sed getPointerTy())); 569193323Sed // Store the incremented VAList to the legalized pointer 570193323Sed Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Node->getOperand(1), V, 0); 571193323Sed // Load the actual argument out of the pointer VAList 572193323Sed return DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0); 573193323Sed} 574193323Sed 575193323SedSDValue XCoreTargetLowering:: 576193323SedLowerVASTART(SDValue Op, SelectionDAG &DAG) 577193323Sed{ 578193323Sed DebugLoc dl = Op.getDebugLoc(); 579193323Sed // vastart stores the address of the VarArgsFrameIndex slot into the 580193323Sed // memory location argument 581193323Sed MachineFunction &MF = DAG.getMachineFunction(); 582193323Sed XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>(); 583193323Sed SDValue Addr = DAG.getFrameIndex(XFI->getVarArgsFrameIndex(), MVT::i32); 584193323Sed const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 585193323Sed return DAG.getStore(Op.getOperand(0), dl, Addr, Op.getOperand(1), SV, 0); 586193323Sed} 587193323Sed 588193323SedSDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { 589193323Sed DebugLoc dl = Op.getDebugLoc(); 590193323Sed // Depths > 0 not supported yet! 591193323Sed if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0) 592193323Sed return SDValue(); 593193323Sed 594193323Sed MachineFunction &MF = DAG.getMachineFunction(); 595193323Sed const TargetRegisterInfo *RegInfo = getTargetMachine().getRegisterInfo(); 596193323Sed return DAG.getCopyFromReg(DAG.getEntryNode(), dl, 597193323Sed RegInfo->getFrameRegister(MF), MVT::i32); 598193323Sed} 599193323Sed 600193323Sed//===----------------------------------------------------------------------===// 601193323Sed// Calling Convention Implementation 602193323Sed//===----------------------------------------------------------------------===// 603193323Sed 604193323Sed#include "XCoreGenCallingConv.inc" 605193323Sed 606193323Sed//===----------------------------------------------------------------------===// 607198090Srdivacky// Call Calling Convention Implementation 608193323Sed//===----------------------------------------------------------------------===// 609193323Sed 610198090Srdivacky/// XCore call implementation 611198090SrdivackySDValue 612198090SrdivackyXCoreTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 613198090Srdivacky CallingConv::ID CallConv, bool isVarArg, 614198090Srdivacky bool isTailCall, 615198090Srdivacky const SmallVectorImpl<ISD::OutputArg> &Outs, 616198090Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 617198090Srdivacky DebugLoc dl, SelectionDAG &DAG, 618198090Srdivacky SmallVectorImpl<SDValue> &InVals) { 619198090Srdivacky 620193323Sed // For now, only CallingConv::C implemented 621198090Srdivacky switch (CallConv) 622193323Sed { 623193323Sed default: 624198090Srdivacky llvm_unreachable("Unsupported calling convention"); 625193323Sed case CallingConv::Fast: 626193323Sed case CallingConv::C: 627198090Srdivacky return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall, 628198090Srdivacky Outs, Ins, dl, DAG, InVals); 629193323Sed } 630193323Sed} 631193323Sed 632193323Sed/// LowerCCCCallTo - functions arguments are copied from virtual 633193323Sed/// regs to (physical regs)/(stack frame), CALLSEQ_START and 634193323Sed/// CALLSEQ_END are emitted. 635193323Sed/// TODO: isTailCall, sret. 636198090SrdivackySDValue 637198090SrdivackyXCoreTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee, 638198090Srdivacky CallingConv::ID CallConv, bool isVarArg, 639198090Srdivacky bool isTailCall, 640198090Srdivacky const SmallVectorImpl<ISD::OutputArg> &Outs, 641198090Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 642198090Srdivacky DebugLoc dl, SelectionDAG &DAG, 643198090Srdivacky SmallVectorImpl<SDValue> &InVals) { 644193323Sed 645193323Sed // Analyze operands of the call, assigning locations to each operand. 646193323Sed SmallVector<CCValAssign, 16> ArgLocs; 647198090Srdivacky CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 648198090Srdivacky ArgLocs, *DAG.getContext()); 649193323Sed 650193323Sed // The ABI dictates there should be one stack slot available to the callee 651193323Sed // on function entry (for saving lr). 652193323Sed CCInfo.AllocateStack(4, 4); 653193323Sed 654198090Srdivacky CCInfo.AnalyzeCallOperands(Outs, CC_XCore); 655193323Sed 656193323Sed // Get a count of how many bytes are to be pushed on the stack. 657193323Sed unsigned NumBytes = CCInfo.getNextStackOffset(); 658193323Sed 659193323Sed Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, 660193323Sed getPointerTy(), true)); 661193323Sed 662193323Sed SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass; 663193323Sed SmallVector<SDValue, 12> MemOpChains; 664193323Sed 665193323Sed // Walk the register/memloc assignments, inserting copies/loads. 666193323Sed for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 667193323Sed CCValAssign &VA = ArgLocs[i]; 668198090Srdivacky SDValue Arg = Outs[i].Val; 669193323Sed 670193323Sed // Promote the value if needed. 671193323Sed switch (VA.getLocInfo()) { 672198090Srdivacky default: llvm_unreachable("Unknown loc info!"); 673193323Sed case CCValAssign::Full: break; 674193323Sed case CCValAssign::SExt: 675193323Sed Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 676193323Sed break; 677193323Sed case CCValAssign::ZExt: 678193323Sed Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 679193323Sed break; 680193323Sed case CCValAssign::AExt: 681193323Sed Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 682193323Sed break; 683193323Sed } 684193323Sed 685193323Sed // Arguments that can be passed on register must be kept at 686193323Sed // RegsToPass vector 687193323Sed if (VA.isRegLoc()) { 688193323Sed RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 689193323Sed } else { 690193323Sed assert(VA.isMemLoc()); 691193323Sed 692193323Sed int Offset = VA.getLocMemOffset(); 693193323Sed 694193323Sed MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, MVT::Other, 695193323Sed Chain, Arg, 696193323Sed DAG.getConstant(Offset/4, MVT::i32))); 697193323Sed } 698193323Sed } 699193323Sed 700193323Sed // Transform all store nodes into one single node because 701193323Sed // all store nodes are independent of each other. 702193323Sed if (!MemOpChains.empty()) 703193323Sed Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 704193323Sed &MemOpChains[0], MemOpChains.size()); 705193323Sed 706193323Sed // Build a sequence of copy-to-reg nodes chained together with token 707193323Sed // chain and flag operands which copy the outgoing args into registers. 708193323Sed // The InFlag in necessary since all emited instructions must be 709193323Sed // stuck together. 710193323Sed SDValue InFlag; 711193323Sed for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 712193323Sed Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 713193323Sed RegsToPass[i].second, InFlag); 714193323Sed InFlag = Chain.getValue(1); 715193323Sed } 716193323Sed 717193323Sed // If the callee is a GlobalAddress node (quite common, every direct call is) 718193323Sed // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 719193323Sed // Likewise ExternalSymbol -> TargetExternalSymbol. 720193323Sed if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 721193323Sed Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 722193323Sed else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 723193323Sed Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 724193323Sed 725193323Sed // XCoreBranchLink = #chain, #target_address, #opt_in_flags... 726193323Sed // = Chain, Callee, Reg#1, Reg#2, ... 727193323Sed // 728193323Sed // Returns a chain & a flag for retval copy to use. 729193323Sed SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 730193323Sed SmallVector<SDValue, 8> Ops; 731193323Sed Ops.push_back(Chain); 732193323Sed Ops.push_back(Callee); 733193323Sed 734193323Sed // Add argument registers to the end of the list so that they are 735193323Sed // known live into the call. 736193323Sed for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 737193323Sed Ops.push_back(DAG.getRegister(RegsToPass[i].first, 738193323Sed RegsToPass[i].second.getValueType())); 739193323Sed 740193323Sed if (InFlag.getNode()) 741193323Sed Ops.push_back(InFlag); 742193323Sed 743193323Sed Chain = DAG.getNode(XCoreISD::BL, dl, NodeTys, &Ops[0], Ops.size()); 744193323Sed InFlag = Chain.getValue(1); 745193323Sed 746193323Sed // Create the CALLSEQ_END node. 747193323Sed Chain = DAG.getCALLSEQ_END(Chain, 748193323Sed DAG.getConstant(NumBytes, getPointerTy(), true), 749193323Sed DAG.getConstant(0, getPointerTy(), true), 750193323Sed InFlag); 751193323Sed InFlag = Chain.getValue(1); 752193323Sed 753193323Sed // Handle result values, copying them out of physregs into vregs that we 754193323Sed // return. 755198090Srdivacky return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 756198090Srdivacky Ins, dl, DAG, InVals); 757193323Sed} 758193323Sed 759198090Srdivacky/// LowerCallResult - Lower the result values of a call into the 760198090Srdivacky/// appropriate copies out of appropriate physical registers. 761198090SrdivackySDValue 762198090SrdivackyXCoreTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 763198090Srdivacky CallingConv::ID CallConv, bool isVarArg, 764198090Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 765198090Srdivacky DebugLoc dl, SelectionDAG &DAG, 766198090Srdivacky SmallVectorImpl<SDValue> &InVals) { 767193323Sed 768193323Sed // Assign locations to each value returned by this call. 769193323Sed SmallVector<CCValAssign, 16> RVLocs; 770198090Srdivacky CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 771198090Srdivacky RVLocs, *DAG.getContext()); 772193323Sed 773198090Srdivacky CCInfo.AnalyzeCallResult(Ins, RetCC_XCore); 774193323Sed 775193323Sed // Copy all of the result registers out of their specified physreg. 776193323Sed for (unsigned i = 0; i != RVLocs.size(); ++i) { 777193323Sed Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 778193323Sed RVLocs[i].getValVT(), InFlag).getValue(1); 779193323Sed InFlag = Chain.getValue(2); 780198090Srdivacky InVals.push_back(Chain.getValue(0)); 781193323Sed } 782193323Sed 783198090Srdivacky return Chain; 784193323Sed} 785193323Sed 786193323Sed//===----------------------------------------------------------------------===// 787198090Srdivacky// Formal Arguments Calling Convention Implementation 788193323Sed//===----------------------------------------------------------------------===// 789193323Sed 790198090Srdivacky/// XCore formal arguments implementation 791198090SrdivackySDValue 792198090SrdivackyXCoreTargetLowering::LowerFormalArguments(SDValue Chain, 793198090Srdivacky CallingConv::ID CallConv, 794198090Srdivacky bool isVarArg, 795198090Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 796198090Srdivacky DebugLoc dl, 797198090Srdivacky SelectionDAG &DAG, 798198090Srdivacky SmallVectorImpl<SDValue> &InVals) { 799198090Srdivacky switch (CallConv) 800193323Sed { 801193323Sed default: 802198090Srdivacky llvm_unreachable("Unsupported calling convention"); 803193323Sed case CallingConv::C: 804193323Sed case CallingConv::Fast: 805198090Srdivacky return LowerCCCArguments(Chain, CallConv, isVarArg, 806198090Srdivacky Ins, dl, DAG, InVals); 807193323Sed } 808193323Sed} 809193323Sed 810193323Sed/// LowerCCCArguments - transform physical registers into 811193323Sed/// virtual registers and generate load operations for 812193323Sed/// arguments places on the stack. 813193323Sed/// TODO: sret 814198090SrdivackySDValue 815198090SrdivackyXCoreTargetLowering::LowerCCCArguments(SDValue Chain, 816198090Srdivacky CallingConv::ID CallConv, 817198090Srdivacky bool isVarArg, 818198090Srdivacky const SmallVectorImpl<ISD::InputArg> 819198090Srdivacky &Ins, 820198090Srdivacky DebugLoc dl, 821198090Srdivacky SelectionDAG &DAG, 822198090Srdivacky SmallVectorImpl<SDValue> &InVals) { 823193323Sed MachineFunction &MF = DAG.getMachineFunction(); 824193323Sed MachineFrameInfo *MFI = MF.getFrameInfo(); 825193323Sed MachineRegisterInfo &RegInfo = MF.getRegInfo(); 826193323Sed 827193323Sed // Assign locations to all of the incoming arguments. 828193323Sed SmallVector<CCValAssign, 16> ArgLocs; 829198090Srdivacky CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 830198090Srdivacky ArgLocs, *DAG.getContext()); 831193323Sed 832198090Srdivacky CCInfo.AnalyzeFormalArguments(Ins, CC_XCore); 833193323Sed 834193323Sed unsigned StackSlotSize = XCoreFrameInfo::stackSlotSize(); 835193323Sed 836193323Sed unsigned LRSaveSize = StackSlotSize; 837193323Sed 838193323Sed for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 839193323Sed 840193323Sed CCValAssign &VA = ArgLocs[i]; 841193323Sed 842193323Sed if (VA.isRegLoc()) { 843193323Sed // Arguments passed in registers 844198090Srdivacky EVT RegVT = VA.getLocVT(); 845198090Srdivacky switch (RegVT.getSimpleVT().SimpleTy) { 846193323Sed default: 847198090Srdivacky { 848198090Srdivacky#ifndef NDEBUG 849198090Srdivacky errs() << "LowerFormalArguments Unhandled argument type: " 850198090Srdivacky << RegVT.getSimpleVT().SimpleTy << "\n"; 851198090Srdivacky#endif 852198090Srdivacky llvm_unreachable(0); 853198090Srdivacky } 854193323Sed case MVT::i32: 855193323Sed unsigned VReg = RegInfo.createVirtualRegister( 856193323Sed XCore::GRRegsRegisterClass); 857193323Sed RegInfo.addLiveIn(VA.getLocReg(), VReg); 858198090Srdivacky InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); 859193323Sed } 860193323Sed } else { 861193323Sed // sanity check 862193323Sed assert(VA.isMemLoc()); 863193323Sed // Load the argument to a virtual register 864193323Sed unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; 865193323Sed if (ObjSize > StackSlotSize) { 866198090Srdivacky errs() << "LowerFormalArguments Unhandled argument type: " 867198090Srdivacky << (unsigned)VA.getLocVT().getSimpleVT().SimpleTy 868198090Srdivacky << "\n"; 869193323Sed } 870193323Sed // Create the frame index object for this incoming parameter... 871193323Sed int FI = MFI->CreateFixedObject(ObjSize, 872199481Srdivacky LRSaveSize + VA.getLocMemOffset(), 873199481Srdivacky true, false); 874193323Sed 875193323Sed // Create the SelectionDAG nodes corresponding to a load 876193323Sed //from this parameter 877193323Sed SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); 878198090Srdivacky InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, NULL, 0)); 879193323Sed } 880193323Sed } 881193323Sed 882193323Sed if (isVarArg) { 883193323Sed /* Argument registers */ 884193323Sed static const unsigned ArgRegs[] = { 885193323Sed XCore::R0, XCore::R1, XCore::R2, XCore::R3 886193323Sed }; 887193323Sed XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>(); 888193323Sed unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs, 889193323Sed array_lengthof(ArgRegs)); 890193323Sed if (FirstVAReg < array_lengthof(ArgRegs)) { 891193323Sed SmallVector<SDValue, 4> MemOps; 892193323Sed int offset = 0; 893193323Sed // Save remaining registers, storing higher register numbers at a higher 894193323Sed // address 895193323Sed for (unsigned i = array_lengthof(ArgRegs) - 1; i >= FirstVAReg; --i) { 896193323Sed // Create a stack slot 897199481Srdivacky int FI = MFI->CreateFixedObject(4, offset, true, false); 898193323Sed if (i == FirstVAReg) { 899193323Sed XFI->setVarArgsFrameIndex(FI); 900193323Sed } 901193323Sed offset -= StackSlotSize; 902193323Sed SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); 903193323Sed // Move argument from phys reg -> virt reg 904193323Sed unsigned VReg = RegInfo.createVirtualRegister( 905193323Sed XCore::GRRegsRegisterClass); 906193323Sed RegInfo.addLiveIn(ArgRegs[i], VReg); 907198090Srdivacky SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 908193323Sed // Move argument from virt reg -> stack 909193323Sed SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0); 910193323Sed MemOps.push_back(Store); 911193323Sed } 912193323Sed if (!MemOps.empty()) 913198090Srdivacky Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 914198090Srdivacky &MemOps[0], MemOps.size()); 915193323Sed } else { 916193323Sed // This will point to the next argument passed via stack. 917193323Sed XFI->setVarArgsFrameIndex( 918199481Srdivacky MFI->CreateFixedObject(4, LRSaveSize + CCInfo.getNextStackOffset(), 919199481Srdivacky true, false)); 920193323Sed } 921193323Sed } 922193323Sed 923198090Srdivacky return Chain; 924193323Sed} 925193323Sed 926193323Sed//===----------------------------------------------------------------------===// 927193323Sed// Return Value Calling Convention Implementation 928193323Sed//===----------------------------------------------------------------------===// 929193323Sed 930199481Srdivackybool XCoreTargetLowering:: 931199481SrdivackyCanLowerReturn(CallingConv::ID CallConv, bool isVarArg, 932199481Srdivacky const SmallVectorImpl<EVT> &OutTys, 933199481Srdivacky const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags, 934199481Srdivacky SelectionDAG &DAG) { 935199481Srdivacky SmallVector<CCValAssign, 16> RVLocs; 936199481Srdivacky CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 937199481Srdivacky RVLocs, *DAG.getContext()); 938199481Srdivacky return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_XCore); 939199481Srdivacky} 940199481Srdivacky 941198090SrdivackySDValue 942198090SrdivackyXCoreTargetLowering::LowerReturn(SDValue Chain, 943198090Srdivacky CallingConv::ID CallConv, bool isVarArg, 944198090Srdivacky const SmallVectorImpl<ISD::OutputArg> &Outs, 945198090Srdivacky DebugLoc dl, SelectionDAG &DAG) { 946198090Srdivacky 947193323Sed // CCValAssign - represent the assignment of 948193323Sed // the return value to a location 949193323Sed SmallVector<CCValAssign, 16> RVLocs; 950193323Sed 951193323Sed // CCState - Info about the registers and stack slot. 952198090Srdivacky CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 953198090Srdivacky RVLocs, *DAG.getContext()); 954193323Sed 955198090Srdivacky // Analize return values. 956198090Srdivacky CCInfo.AnalyzeReturn(Outs, RetCC_XCore); 957193323Sed 958193323Sed // If this is the first return lowered for this function, add 959193323Sed // the regs to the liveout set for the function. 960193323Sed if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 961193323Sed for (unsigned i = 0; i != RVLocs.size(); ++i) 962193323Sed if (RVLocs[i].isRegLoc()) 963193323Sed DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 964193323Sed } 965193323Sed 966193323Sed SDValue Flag; 967193323Sed 968193323Sed // Copy the result values into the output registers. 969193323Sed for (unsigned i = 0; i != RVLocs.size(); ++i) { 970193323Sed CCValAssign &VA = RVLocs[i]; 971193323Sed assert(VA.isRegLoc() && "Can only return in registers!"); 972193323Sed 973193323Sed Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 974198090Srdivacky Outs[i].Val, Flag); 975193323Sed 976193323Sed // guarantee that all emitted copies are 977193323Sed // stuck together, avoiding something bad 978193323Sed Flag = Chain.getValue(1); 979193323Sed } 980193323Sed 981193323Sed // Return on XCore is always a "retsp 0" 982193323Sed if (Flag.getNode()) 983193323Sed return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other, 984193323Sed Chain, DAG.getConstant(0, MVT::i32), Flag); 985193323Sed else // Return Void 986193323Sed return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other, 987193323Sed Chain, DAG.getConstant(0, MVT::i32)); 988193323Sed} 989193323Sed 990193323Sed//===----------------------------------------------------------------------===// 991193323Sed// Other Lowering Code 992193323Sed//===----------------------------------------------------------------------===// 993193323Sed 994193323SedMachineBasicBlock * 995193323SedXCoreTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 996198090Srdivacky MachineBasicBlock *BB, 997198090Srdivacky DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 998193323Sed const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 999193323Sed DebugLoc dl = MI->getDebugLoc(); 1000193323Sed assert((MI->getOpcode() == XCore::SELECT_CC) && 1001193323Sed "Unexpected instr type to insert"); 1002193323Sed 1003193323Sed // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 1004193323Sed // control-flow pattern. The incoming instruction knows the destination vreg 1005193323Sed // to set, the condition code register to branch on, the true/false values to 1006193323Sed // select between, and a branch opcode to use. 1007193323Sed const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1008193323Sed MachineFunction::iterator It = BB; 1009193323Sed ++It; 1010193323Sed 1011193323Sed // thisMBB: 1012193323Sed // ... 1013193323Sed // TrueVal = ... 1014193323Sed // cmpTY ccX, r1, r2 1015193323Sed // bCC copy1MBB 1016193323Sed // fallthrough --> copy0MBB 1017193323Sed MachineBasicBlock *thisMBB = BB; 1018193323Sed MachineFunction *F = BB->getParent(); 1019193323Sed MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 1020193323Sed MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 1021193323Sed BuildMI(BB, dl, TII.get(XCore::BRFT_lru6)) 1022193323Sed .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 1023193323Sed F->insert(It, copy0MBB); 1024193323Sed F->insert(It, sinkMBB); 1025198090Srdivacky // Update machine-CFG edges by first adding all successors of the current 1026193323Sed // block to the new block which will contain the Phi node for the select. 1027198090Srdivacky // Also inform sdisel of the edge changes. 1028198090Srdivacky for (MachineBasicBlock::succ_iterator I = BB->succ_begin(), 1029198090Srdivacky E = BB->succ_end(); I != E; ++I) { 1030198090Srdivacky EM->insert(std::make_pair(*I, sinkMBB)); 1031198090Srdivacky sinkMBB->addSuccessor(*I); 1032198090Srdivacky } 1033198090Srdivacky // Next, remove all successors of the current block, and add the true 1034198090Srdivacky // and fallthrough blocks as its successors. 1035198090Srdivacky while (!BB->succ_empty()) 1036198090Srdivacky BB->removeSuccessor(BB->succ_begin()); 1037193323Sed // Next, add the true and fallthrough blocks as its successors. 1038193323Sed BB->addSuccessor(copy0MBB); 1039193323Sed BB->addSuccessor(sinkMBB); 1040193323Sed 1041193323Sed // copy0MBB: 1042193323Sed // %FalseValue = ... 1043193323Sed // # fallthrough to sinkMBB 1044193323Sed BB = copy0MBB; 1045193323Sed 1046193323Sed // Update machine-CFG edges 1047193323Sed BB->addSuccessor(sinkMBB); 1048193323Sed 1049193323Sed // sinkMBB: 1050193323Sed // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1051193323Sed // ... 1052193323Sed BB = sinkMBB; 1053193323Sed BuildMI(BB, dl, TII.get(XCore::PHI), MI->getOperand(0).getReg()) 1054193323Sed .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 1055193323Sed .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 1056193323Sed 1057193323Sed F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 1058193323Sed return BB; 1059193323Sed} 1060193323Sed 1061193323Sed//===----------------------------------------------------------------------===// 1062198090Srdivacky// Target Optimization Hooks 1063198090Srdivacky//===----------------------------------------------------------------------===// 1064198090Srdivacky 1065198090SrdivackySDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N, 1066198090Srdivacky DAGCombinerInfo &DCI) const { 1067198090Srdivacky SelectionDAG &DAG = DCI.DAG; 1068198090Srdivacky DebugLoc dl = N->getDebugLoc(); 1069198090Srdivacky switch (N->getOpcode()) { 1070198090Srdivacky default: break; 1071198090Srdivacky case ISD::STORE: { 1072198090Srdivacky // Replace unaligned store of unaligned load with memmove. 1073198090Srdivacky StoreSDNode *ST = cast<StoreSDNode>(N); 1074198090Srdivacky if (!DCI.isBeforeLegalize() || 1075198090Srdivacky allowsUnalignedMemoryAccesses(ST->getMemoryVT()) || 1076198090Srdivacky ST->isVolatile() || ST->isIndexed()) { 1077198090Srdivacky break; 1078198090Srdivacky } 1079198090Srdivacky SDValue Chain = ST->getChain(); 1080198090Srdivacky 1081198090Srdivacky unsigned StoreBits = ST->getMemoryVT().getStoreSizeInBits(); 1082198090Srdivacky if (StoreBits % 8) { 1083198090Srdivacky break; 1084198090Srdivacky } 1085198090Srdivacky unsigned ABIAlignment = getTargetData()->getABITypeAlignment( 1086198090Srdivacky ST->getMemoryVT().getTypeForEVT(*DCI.DAG.getContext())); 1087198090Srdivacky unsigned Alignment = ST->getAlignment(); 1088198090Srdivacky if (Alignment >= ABIAlignment) { 1089198090Srdivacky break; 1090198090Srdivacky } 1091198090Srdivacky 1092198090Srdivacky if (LoadSDNode *LD = dyn_cast<LoadSDNode>(ST->getValue())) { 1093198090Srdivacky if (LD->hasNUsesOfValue(1, 0) && ST->getMemoryVT() == LD->getMemoryVT() && 1094198090Srdivacky LD->getAlignment() == Alignment && 1095198090Srdivacky !LD->isVolatile() && !LD->isIndexed() && 1096198090Srdivacky Chain.reachesChainWithoutSideEffects(SDValue(LD, 1))) { 1097198090Srdivacky return DAG.getMemmove(Chain, dl, ST->getBasePtr(), 1098198090Srdivacky LD->getBasePtr(), 1099198090Srdivacky DAG.getConstant(StoreBits/8, MVT::i32), 1100198090Srdivacky Alignment, ST->getSrcValue(), 1101198090Srdivacky ST->getSrcValueOffset(), LD->getSrcValue(), 1102198090Srdivacky LD->getSrcValueOffset()); 1103198090Srdivacky } 1104198090Srdivacky } 1105198090Srdivacky break; 1106198090Srdivacky } 1107198090Srdivacky } 1108198090Srdivacky return SDValue(); 1109198090Srdivacky} 1110198090Srdivacky 1111198090Srdivacky//===----------------------------------------------------------------------===// 1112193323Sed// Addressing mode description hooks 1113193323Sed//===----------------------------------------------------------------------===// 1114193323Sed 1115193323Sedstatic inline bool isImmUs(int64_t val) 1116193323Sed{ 1117193323Sed return (val >= 0 && val <= 11); 1118193323Sed} 1119193323Sed 1120193323Sedstatic inline bool isImmUs2(int64_t val) 1121193323Sed{ 1122193323Sed return (val%2 == 0 && isImmUs(val/2)); 1123193323Sed} 1124193323Sed 1125193323Sedstatic inline bool isImmUs4(int64_t val) 1126193323Sed{ 1127193323Sed return (val%4 == 0 && isImmUs(val/4)); 1128193323Sed} 1129193323Sed 1130193323Sed/// isLegalAddressingMode - Return true if the addressing mode represented 1131193323Sed/// by AM is legal for this target, for a load/store of the specified type. 1132193323Sedbool 1133193323SedXCoreTargetLowering::isLegalAddressingMode(const AddrMode &AM, 1134193323Sed const Type *Ty) const { 1135198090Srdivacky // Be conservative with void 1136198090Srdivacky // FIXME: Can we be more aggressive? 1137198090Srdivacky if (Ty->getTypeID() == Type::VoidTyID) 1138198090Srdivacky return false; 1139198090Srdivacky 1140198090Srdivacky const TargetData *TD = TM.getTargetData(); 1141198090Srdivacky unsigned Size = TD->getTypeAllocSize(Ty); 1142193323Sed if (AM.BaseGV) { 1143198090Srdivacky return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 && 1144193323Sed AM.BaseOffs%4 == 0; 1145193323Sed } 1146193323Sed 1147198090Srdivacky switch (Size) { 1148198090Srdivacky case 1: 1149193323Sed // reg + imm 1150193323Sed if (AM.Scale == 0) { 1151193323Sed return isImmUs(AM.BaseOffs); 1152193323Sed } 1153198090Srdivacky // reg + reg 1154193323Sed return AM.Scale == 1 && AM.BaseOffs == 0; 1155198090Srdivacky case 2: 1156198090Srdivacky case 3: 1157193323Sed // reg + imm 1158193323Sed if (AM.Scale == 0) { 1159193323Sed return isImmUs2(AM.BaseOffs); 1160193323Sed } 1161198090Srdivacky // reg + reg<<1 1162193323Sed return AM.Scale == 2 && AM.BaseOffs == 0; 1163198090Srdivacky default: 1164193323Sed // reg + imm 1165193323Sed if (AM.Scale == 0) { 1166193323Sed return isImmUs4(AM.BaseOffs); 1167193323Sed } 1168193323Sed // reg + reg<<2 1169193323Sed return AM.Scale == 4 && AM.BaseOffs == 0; 1170193323Sed } 1171193323Sed 1172193323Sed return false; 1173193323Sed} 1174193323Sed 1175193323Sed//===----------------------------------------------------------------------===// 1176193323Sed// XCore Inline Assembly Support 1177193323Sed//===----------------------------------------------------------------------===// 1178193323Sed 1179193323Sedstd::vector<unsigned> XCoreTargetLowering:: 1180193323SedgetRegClassForInlineAsmConstraint(const std::string &Constraint, 1181198090Srdivacky EVT VT) const 1182193323Sed{ 1183193323Sed if (Constraint.size() != 1) 1184193323Sed return std::vector<unsigned>(); 1185193323Sed 1186193323Sed switch (Constraint[0]) { 1187193323Sed default : break; 1188193323Sed case 'r': 1189193323Sed return make_vector<unsigned>(XCore::R0, XCore::R1, XCore::R2, 1190193323Sed XCore::R3, XCore::R4, XCore::R5, 1191193323Sed XCore::R6, XCore::R7, XCore::R8, 1192193323Sed XCore::R9, XCore::R10, XCore::R11, 0); 1193193323Sed break; 1194193323Sed } 1195193323Sed return std::vector<unsigned>(); 1196193323Sed} 1197