XCoreISelLowering.cpp revision 199481
1193323Sed//===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ------===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file implements the XCoreTargetLowering class. 11193323Sed// 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14193323Sed#define DEBUG_TYPE "xcore-lower" 15193323Sed 16193323Sed#include "XCoreISelLowering.h" 17193323Sed#include "XCoreMachineFunctionInfo.h" 18193323Sed#include "XCore.h" 19198090Srdivacky#include "XCoreTargetObjectFile.h" 20193323Sed#include "XCoreTargetMachine.h" 21193323Sed#include "XCoreSubtarget.h" 22193323Sed#include "llvm/DerivedTypes.h" 23193323Sed#include "llvm/Function.h" 24193323Sed#include "llvm/Intrinsics.h" 25193323Sed#include "llvm/CallingConv.h" 26193323Sed#include "llvm/GlobalVariable.h" 27193323Sed#include "llvm/GlobalAlias.h" 28193323Sed#include "llvm/CodeGen/CallingConvLower.h" 29193323Sed#include "llvm/CodeGen/MachineFrameInfo.h" 30193323Sed#include "llvm/CodeGen/MachineFunction.h" 31193323Sed#include "llvm/CodeGen/MachineInstrBuilder.h" 32193323Sed#include "llvm/CodeGen/MachineRegisterInfo.h" 33193323Sed#include "llvm/CodeGen/SelectionDAGISel.h" 34193323Sed#include "llvm/CodeGen/ValueTypes.h" 35193323Sed#include "llvm/Support/Debug.h" 36198090Srdivacky#include "llvm/Support/ErrorHandling.h" 37198090Srdivacky#include "llvm/Support/raw_ostream.h" 38193323Sed#include "llvm/ADT/VectorExtras.h" 39193323Sed#include <queue> 40193323Sed#include <set> 41193323Sedusing namespace llvm; 42193323Sed 43193323Sedconst char *XCoreTargetLowering:: 44193323SedgetTargetNodeName(unsigned Opcode) const 45193323Sed{ 46193323Sed switch (Opcode) 47193323Sed { 48193323Sed case XCoreISD::BL : return "XCoreISD::BL"; 49193323Sed case XCoreISD::PCRelativeWrapper : return "XCoreISD::PCRelativeWrapper"; 50193323Sed case XCoreISD::DPRelativeWrapper : return "XCoreISD::DPRelativeWrapper"; 51193323Sed case XCoreISD::CPRelativeWrapper : return "XCoreISD::CPRelativeWrapper"; 52193323Sed case XCoreISD::STWSP : return "XCoreISD::STWSP"; 53193323Sed case XCoreISD::RETSP : return "XCoreISD::RETSP"; 54198090Srdivacky case XCoreISD::LADD : return "XCoreISD::LADD"; 55198090Srdivacky case XCoreISD::LSUB : return "XCoreISD::LSUB"; 56193323Sed default : return NULL; 57193323Sed } 58193323Sed} 59193323Sed 60193323SedXCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM) 61198090Srdivacky : TargetLowering(XTM, new XCoreTargetObjectFile()), 62193323Sed TM(XTM), 63193323Sed Subtarget(*XTM.getSubtargetImpl()) { 64193323Sed 65193323Sed // Set up the register classes. 66193323Sed addRegisterClass(MVT::i32, XCore::GRRegsRegisterClass); 67193323Sed 68193323Sed // Compute derived properties from the register classes 69193323Sed computeRegisterProperties(); 70193323Sed 71193323Sed // Division is expensive 72193323Sed setIntDivIsCheap(false); 73193323Sed 74193323Sed setShiftAmountType(MVT::i32); 75193323Sed setStackPointerRegisterToSaveRestore(XCore::SP); 76193323Sed 77193323Sed setSchedulingPreference(SchedulingForRegPressure); 78193323Sed 79193323Sed // Use i32 for setcc operations results (slt, sgt, ...). 80193323Sed setBooleanContents(ZeroOrOneBooleanContent); 81193323Sed 82193323Sed // XCore does not have the NodeTypes below. 83193323Sed setOperationAction(ISD::BR_CC, MVT::Other, Expand); 84193323Sed setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 85193323Sed setOperationAction(ISD::ADDC, MVT::i32, Expand); 86193323Sed setOperationAction(ISD::ADDE, MVT::i32, Expand); 87193323Sed setOperationAction(ISD::SUBC, MVT::i32, Expand); 88193323Sed setOperationAction(ISD::SUBE, MVT::i32, Expand); 89193323Sed 90193323Sed // Stop the combiner recombining select and set_cc 91193323Sed setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 92193323Sed 93193323Sed // 64bit 94198090Srdivacky setOperationAction(ISD::ADD, MVT::i64, Custom); 95198090Srdivacky setOperationAction(ISD::SUB, MVT::i64, Custom); 96193323Sed setOperationAction(ISD::MULHS, MVT::i32, Expand); 97193323Sed setOperationAction(ISD::MULHU, MVT::i32, Expand); 98193323Sed setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 99193323Sed setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 100193323Sed setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 101193323Sed 102193323Sed // Bit Manipulation 103193323Sed setOperationAction(ISD::CTPOP, MVT::i32, Expand); 104193323Sed setOperationAction(ISD::ROTL , MVT::i32, Expand); 105193323Sed setOperationAction(ISD::ROTR , MVT::i32, Expand); 106193323Sed 107193323Sed setOperationAction(ISD::TRAP, MVT::Other, Legal); 108193323Sed 109193323Sed // Expand jump tables for now 110193323Sed setOperationAction(ISD::BR_JT, MVT::Other, Expand); 111193323Sed setOperationAction(ISD::JumpTable, MVT::i32, Custom); 112193323Sed 113193323Sed setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 114193323Sed 115193323Sed // Thread Local Storage 116193323Sed setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 117193323Sed 118193323Sed // Conversion of i64 -> double produces constantpool nodes 119193323Sed setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 120193323Sed 121193323Sed // Loads 122193323Sed setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 123193323Sed setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 124193323Sed setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 125193323Sed 126193323Sed setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); 127193323Sed setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand); 128198090Srdivacky 129198090Srdivacky // Custom expand misaligned loads / stores. 130198090Srdivacky setOperationAction(ISD::LOAD, MVT::i32, Custom); 131198090Srdivacky setOperationAction(ISD::STORE, MVT::i32, Custom); 132198090Srdivacky 133193323Sed // Varargs 134193323Sed setOperationAction(ISD::VAEND, MVT::Other, Expand); 135193323Sed setOperationAction(ISD::VACOPY, MVT::Other, Expand); 136193323Sed setOperationAction(ISD::VAARG, MVT::Other, Custom); 137193323Sed setOperationAction(ISD::VASTART, MVT::Other, Custom); 138193323Sed 139193323Sed // Dynamic stack 140193323Sed setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 141193323Sed setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 142193323Sed setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 143193323Sed 144193323Sed // Debug 145193323Sed setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); 146193323Sed setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 147198090Srdivacky 148198090Srdivacky maxStoresPerMemset = 4; 149198090Srdivacky maxStoresPerMemmove = maxStoresPerMemcpy = 2; 150198090Srdivacky 151198090Srdivacky // We have target-specific dag combine patterns for the following nodes: 152198090Srdivacky setTargetDAGCombine(ISD::STORE); 153193323Sed} 154193323Sed 155193323SedSDValue XCoreTargetLowering:: 156193323SedLowerOperation(SDValue Op, SelectionDAG &DAG) { 157193323Sed switch (Op.getOpcode()) 158193323Sed { 159193323Sed case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 160193323Sed case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 161193323Sed case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 162193323Sed case ISD::JumpTable: return LowerJumpTable(Op, DAG); 163198090Srdivacky case ISD::LOAD: return LowerLOAD(Op, DAG); 164198090Srdivacky case ISD::STORE: return LowerSTORE(Op, DAG); 165193323Sed case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 166193323Sed case ISD::VAARG: return LowerVAARG(Op, DAG); 167193323Sed case ISD::VASTART: return LowerVASTART(Op, DAG); 168193323Sed // FIXME: Remove these when LegalizeDAGTypes lands. 169193323Sed case ISD::ADD: 170193323Sed case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG); 171193323Sed case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 172193323Sed default: 173198090Srdivacky llvm_unreachable("unimplemented operand"); 174193323Sed return SDValue(); 175193323Sed } 176193323Sed} 177193323Sed 178193323Sed/// ReplaceNodeResults - Replace the results of node with an illegal result 179193323Sed/// type with new values built out of custom code. 180193323Sedvoid XCoreTargetLowering::ReplaceNodeResults(SDNode *N, 181193323Sed SmallVectorImpl<SDValue>&Results, 182193323Sed SelectionDAG &DAG) { 183193323Sed switch (N->getOpcode()) { 184193323Sed default: 185198090Srdivacky llvm_unreachable("Don't know how to custom expand this!"); 186193323Sed return; 187193323Sed case ISD::ADD: 188193323Sed case ISD::SUB: 189193323Sed Results.push_back(ExpandADDSUB(N, DAG)); 190193323Sed return; 191193323Sed } 192193323Sed} 193193323Sed 194195340Sed/// getFunctionAlignment - Return the Log2 alignment of this function. 195195340Sedunsigned XCoreTargetLowering:: 196195340SedgetFunctionAlignment(const Function *) const { 197195340Sed return 1; 198195340Sed} 199195340Sed 200193323Sed//===----------------------------------------------------------------------===// 201193323Sed// Misc Lower Operation implementation 202193323Sed//===----------------------------------------------------------------------===// 203193323Sed 204193323SedSDValue XCoreTargetLowering:: 205193323SedLowerSELECT_CC(SDValue Op, SelectionDAG &DAG) 206193323Sed{ 207193323Sed DebugLoc dl = Op.getDebugLoc(); 208193323Sed SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i32, Op.getOperand(2), 209193323Sed Op.getOperand(3), Op.getOperand(4)); 210193323Sed return DAG.getNode(ISD::SELECT, dl, MVT::i32, Cond, Op.getOperand(0), 211193323Sed Op.getOperand(1)); 212193323Sed} 213193323Sed 214193323SedSDValue XCoreTargetLowering:: 215193323SedgetGlobalAddressWrapper(SDValue GA, GlobalValue *GV, SelectionDAG &DAG) 216193323Sed{ 217193323Sed // FIXME there is no actual debug info here 218193323Sed DebugLoc dl = GA.getDebugLoc(); 219193323Sed if (isa<Function>(GV)) { 220193323Sed return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA); 221193323Sed } 222198090Srdivacky const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); 223198090Srdivacky if (!GVar) { 224198090Srdivacky // If GV is an alias then use the aliasee to determine constness 225198090Srdivacky if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 226198090Srdivacky GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal()); 227198090Srdivacky } 228198090Srdivacky bool isConst = GVar && GVar->isConstant(); 229198090Srdivacky if (isConst) { 230198090Srdivacky return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA); 231198090Srdivacky } 232193323Sed return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA); 233193323Sed} 234193323Sed 235193323SedSDValue XCoreTargetLowering:: 236193323SedLowerGlobalAddress(SDValue Op, SelectionDAG &DAG) 237193323Sed{ 238193323Sed GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 239193323Sed SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 240193323Sed // If it's a debug information descriptor, don't mess with it. 241193323Sed if (DAG.isVerifiedDebugInfoDesc(Op)) 242193323Sed return GA; 243193323Sed return getGlobalAddressWrapper(GA, GV, DAG); 244193323Sed} 245193323Sed 246193323Sedstatic inline SDValue BuildGetId(SelectionDAG &DAG, DebugLoc dl) { 247193323Sed return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32, 248193323Sed DAG.getConstant(Intrinsic::xcore_getid, MVT::i32)); 249193323Sed} 250193323Sed 251193323Sedstatic inline bool isZeroLengthArray(const Type *Ty) { 252193323Sed const ArrayType *AT = dyn_cast_or_null<ArrayType>(Ty); 253193323Sed return AT && (AT->getNumElements() == 0); 254193323Sed} 255193323Sed 256193323SedSDValue XCoreTargetLowering:: 257193323SedLowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) 258193323Sed{ 259193323Sed // FIXME there isn't really debug info here 260193323Sed DebugLoc dl = Op.getDebugLoc(); 261193323Sed // transform to label + getid() * size 262193323Sed GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 263193323Sed SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 264193323Sed const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); 265193323Sed if (!GVar) { 266193323Sed // If GV is an alias then use the aliasee to determine size 267193323Sed if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 268193323Sed GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal()); 269193323Sed } 270193323Sed if (! GVar) { 271198090Srdivacky llvm_unreachable("Thread local object not a GlobalVariable?"); 272193323Sed return SDValue(); 273193323Sed } 274193323Sed const Type *Ty = cast<PointerType>(GV->getType())->getElementType(); 275193323Sed if (!Ty->isSized() || isZeroLengthArray(Ty)) { 276198090Srdivacky#ifndef NDEBUG 277198090Srdivacky errs() << "Size of thread local object " << GVar->getName() 278198090Srdivacky << " is unknown\n"; 279198090Srdivacky#endif 280198090Srdivacky llvm_unreachable(0); 281193323Sed } 282193323Sed SDValue base = getGlobalAddressWrapper(GA, GV, DAG); 283193323Sed const TargetData *TD = TM.getTargetData(); 284193323Sed unsigned Size = TD->getTypeAllocSize(Ty); 285193323Sed SDValue offset = DAG.getNode(ISD::MUL, dl, MVT::i32, BuildGetId(DAG, dl), 286193323Sed DAG.getConstant(Size, MVT::i32)); 287193323Sed return DAG.getNode(ISD::ADD, dl, MVT::i32, base, offset); 288193323Sed} 289193323Sed 290193323SedSDValue XCoreTargetLowering:: 291193323SedLowerConstantPool(SDValue Op, SelectionDAG &DAG) 292193323Sed{ 293193323Sed ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 294193323Sed // FIXME there isn't really debug info here 295193323Sed DebugLoc dl = CP->getDebugLoc(); 296198090Srdivacky EVT PtrVT = Op.getValueType(); 297198090Srdivacky SDValue Res; 298198090Srdivacky if (CP->isMachineConstantPoolEntry()) { 299198090Srdivacky Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, 300198090Srdivacky CP->getAlignment()); 301193323Sed } else { 302198090Srdivacky Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, 303198090Srdivacky CP->getAlignment()); 304193323Sed } 305198090Srdivacky return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res); 306193323Sed} 307193323Sed 308193323SedSDValue XCoreTargetLowering:: 309193323SedLowerJumpTable(SDValue Op, SelectionDAG &DAG) 310193323Sed{ 311193323Sed // FIXME there isn't really debug info here 312193323Sed DebugLoc dl = Op.getDebugLoc(); 313198090Srdivacky EVT PtrVT = Op.getValueType(); 314193323Sed JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 315193323Sed SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); 316193323Sed return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, JTI); 317193323Sed} 318193323Sed 319198090Srdivackystatic bool 320198090SrdivackyIsWordAlignedBasePlusConstantOffset(SDValue Addr, SDValue &AlignedBase, 321198090Srdivacky int64_t &Offset) 322198090Srdivacky{ 323198090Srdivacky if (Addr.getOpcode() != ISD::ADD) { 324198090Srdivacky return false; 325198090Srdivacky } 326198090Srdivacky ConstantSDNode *CN = 0; 327198090Srdivacky if (!(CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) { 328198090Srdivacky return false; 329198090Srdivacky } 330198090Srdivacky int64_t off = CN->getSExtValue(); 331198090Srdivacky const SDValue &Base = Addr.getOperand(0); 332198090Srdivacky const SDValue *Root = &Base; 333198090Srdivacky if (Base.getOpcode() == ISD::ADD && 334198090Srdivacky Base.getOperand(1).getOpcode() == ISD::SHL) { 335198090Srdivacky ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Base.getOperand(1) 336198090Srdivacky .getOperand(1)); 337198090Srdivacky if (CN && (CN->getSExtValue() >= 2)) { 338198090Srdivacky Root = &Base.getOperand(0); 339198090Srdivacky } 340198090Srdivacky } 341198090Srdivacky if (isa<FrameIndexSDNode>(*Root)) { 342198090Srdivacky // All frame indicies are word aligned 343198090Srdivacky AlignedBase = Base; 344198090Srdivacky Offset = off; 345198090Srdivacky return true; 346198090Srdivacky } 347198090Srdivacky if (Root->getOpcode() == XCoreISD::DPRelativeWrapper || 348198090Srdivacky Root->getOpcode() == XCoreISD::CPRelativeWrapper) { 349198090Srdivacky // All dp / cp relative addresses are word aligned 350198090Srdivacky AlignedBase = Base; 351198090Srdivacky Offset = off; 352198090Srdivacky return true; 353198090Srdivacky } 354198090Srdivacky return false; 355198090Srdivacky} 356198090Srdivacky 357193323SedSDValue XCoreTargetLowering:: 358198090SrdivackyLowerLOAD(SDValue Op, SelectionDAG &DAG) 359198090Srdivacky{ 360198090Srdivacky LoadSDNode *LD = cast<LoadSDNode>(Op); 361198090Srdivacky assert(LD->getExtensionType() == ISD::NON_EXTLOAD && 362198090Srdivacky "Unexpected extension type"); 363198090Srdivacky assert(LD->getMemoryVT() == MVT::i32 && "Unexpected load EVT"); 364198090Srdivacky if (allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 365198090Srdivacky return SDValue(); 366198090Srdivacky } 367198090Srdivacky unsigned ABIAlignment = getTargetData()-> 368198090Srdivacky getABITypeAlignment(LD->getMemoryVT().getTypeForEVT(*DAG.getContext())); 369198090Srdivacky // Leave aligned load alone. 370198090Srdivacky if (LD->getAlignment() >= ABIAlignment) { 371198090Srdivacky return SDValue(); 372198090Srdivacky } 373198090Srdivacky SDValue Chain = LD->getChain(); 374198090Srdivacky SDValue BasePtr = LD->getBasePtr(); 375198090Srdivacky DebugLoc dl = Op.getDebugLoc(); 376198090Srdivacky 377198090Srdivacky SDValue Base; 378198090Srdivacky int64_t Offset; 379198090Srdivacky if (!LD->isVolatile() && 380198090Srdivacky IsWordAlignedBasePlusConstantOffset(BasePtr, Base, Offset)) { 381198090Srdivacky if (Offset % 4 == 0) { 382198090Srdivacky // We've managed to infer better alignment information than the load 383198090Srdivacky // already has. Use an aligned load. 384198090Srdivacky return DAG.getLoad(getPointerTy(), dl, Chain, BasePtr, NULL, 4); 385198090Srdivacky } 386198090Srdivacky // Lower to 387198090Srdivacky // ldw low, base[offset >> 2] 388198090Srdivacky // ldw high, base[(offset >> 2) + 1] 389198090Srdivacky // shr low_shifted, low, (offset & 0x3) * 8 390198090Srdivacky // shl high_shifted, high, 32 - (offset & 0x3) * 8 391198090Srdivacky // or result, low_shifted, high_shifted 392198090Srdivacky SDValue LowOffset = DAG.getConstant(Offset & ~0x3, MVT::i32); 393198090Srdivacky SDValue HighOffset = DAG.getConstant((Offset & ~0x3) + 4, MVT::i32); 394198090Srdivacky SDValue LowShift = DAG.getConstant((Offset & 0x3) * 8, MVT::i32); 395198090Srdivacky SDValue HighShift = DAG.getConstant(32 - (Offset & 0x3) * 8, MVT::i32); 396198090Srdivacky 397198090Srdivacky SDValue LowAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Base, LowOffset); 398198090Srdivacky SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Base, HighOffset); 399198090Srdivacky 400198090Srdivacky SDValue Low = DAG.getLoad(getPointerTy(), dl, Chain, 401198090Srdivacky LowAddr, NULL, 4); 402198090Srdivacky SDValue High = DAG.getLoad(getPointerTy(), dl, Chain, 403198090Srdivacky HighAddr, NULL, 4); 404198090Srdivacky SDValue LowShifted = DAG.getNode(ISD::SRL, dl, MVT::i32, Low, LowShift); 405198090Srdivacky SDValue HighShifted = DAG.getNode(ISD::SHL, dl, MVT::i32, High, HighShift); 406198090Srdivacky SDValue Result = DAG.getNode(ISD::OR, dl, MVT::i32, LowShifted, HighShifted); 407198090Srdivacky Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Low.getValue(1), 408198090Srdivacky High.getValue(1)); 409198090Srdivacky SDValue Ops[] = { Result, Chain }; 410198090Srdivacky return DAG.getMergeValues(Ops, 2, dl); 411198090Srdivacky } 412198090Srdivacky 413198090Srdivacky if (LD->getAlignment() == 2) { 414198090Srdivacky int SVOffset = LD->getSrcValueOffset(); 415198090Srdivacky SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain, 416198090Srdivacky BasePtr, LD->getSrcValue(), SVOffset, MVT::i16, 417198090Srdivacky LD->isVolatile(), 2); 418198090Srdivacky SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr, 419198090Srdivacky DAG.getConstant(2, MVT::i32)); 420198090Srdivacky SDValue High = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::i32, Chain, 421198090Srdivacky HighAddr, LD->getSrcValue(), SVOffset + 2, 422198090Srdivacky MVT::i16, LD->isVolatile(), 2); 423198090Srdivacky SDValue HighShifted = DAG.getNode(ISD::SHL, dl, MVT::i32, High, 424198090Srdivacky DAG.getConstant(16, MVT::i32)); 425198090Srdivacky SDValue Result = DAG.getNode(ISD::OR, dl, MVT::i32, Low, HighShifted); 426198090Srdivacky Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Low.getValue(1), 427198090Srdivacky High.getValue(1)); 428198090Srdivacky SDValue Ops[] = { Result, Chain }; 429198090Srdivacky return DAG.getMergeValues(Ops, 2, dl); 430198090Srdivacky } 431198090Srdivacky 432198090Srdivacky // Lower to a call to __misaligned_load(BasePtr). 433198090Srdivacky const Type *IntPtrTy = getTargetData()->getIntPtrType(*DAG.getContext()); 434198090Srdivacky TargetLowering::ArgListTy Args; 435198090Srdivacky TargetLowering::ArgListEntry Entry; 436198090Srdivacky 437198090Srdivacky Entry.Ty = IntPtrTy; 438198090Srdivacky Entry.Node = BasePtr; 439198090Srdivacky Args.push_back(Entry); 440198090Srdivacky 441198090Srdivacky std::pair<SDValue, SDValue> CallResult = 442198090Srdivacky LowerCallTo(Chain, IntPtrTy, false, false, 443198090Srdivacky false, false, 0, CallingConv::C, false, 444198090Srdivacky /*isReturnValueUsed=*/true, 445198090Srdivacky DAG.getExternalSymbol("__misaligned_load", getPointerTy()), 446198090Srdivacky Args, DAG, dl); 447198090Srdivacky 448198090Srdivacky SDValue Ops[] = 449198090Srdivacky { CallResult.first, CallResult.second }; 450198090Srdivacky 451198090Srdivacky return DAG.getMergeValues(Ops, 2, dl); 452198090Srdivacky} 453198090Srdivacky 454198090SrdivackySDValue XCoreTargetLowering:: 455198090SrdivackyLowerSTORE(SDValue Op, SelectionDAG &DAG) 456198090Srdivacky{ 457198090Srdivacky StoreSDNode *ST = cast<StoreSDNode>(Op); 458198090Srdivacky assert(!ST->isTruncatingStore() && "Unexpected store type"); 459198090Srdivacky assert(ST->getMemoryVT() == MVT::i32 && "Unexpected store EVT"); 460198090Srdivacky if (allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 461198090Srdivacky return SDValue(); 462198090Srdivacky } 463198090Srdivacky unsigned ABIAlignment = getTargetData()-> 464198090Srdivacky getABITypeAlignment(ST->getMemoryVT().getTypeForEVT(*DAG.getContext())); 465198090Srdivacky // Leave aligned store alone. 466198090Srdivacky if (ST->getAlignment() >= ABIAlignment) { 467198090Srdivacky return SDValue(); 468198090Srdivacky } 469198090Srdivacky SDValue Chain = ST->getChain(); 470198090Srdivacky SDValue BasePtr = ST->getBasePtr(); 471198090Srdivacky SDValue Value = ST->getValue(); 472198090Srdivacky DebugLoc dl = Op.getDebugLoc(); 473198090Srdivacky 474198090Srdivacky if (ST->getAlignment() == 2) { 475198090Srdivacky int SVOffset = ST->getSrcValueOffset(); 476198090Srdivacky SDValue Low = Value; 477198090Srdivacky SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value, 478198090Srdivacky DAG.getConstant(16, MVT::i32)); 479198090Srdivacky SDValue StoreLow = DAG.getTruncStore(Chain, dl, Low, BasePtr, 480198090Srdivacky ST->getSrcValue(), SVOffset, MVT::i16, 481198090Srdivacky ST->isVolatile(), 2); 482198090Srdivacky SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr, 483198090Srdivacky DAG.getConstant(2, MVT::i32)); 484198090Srdivacky SDValue StoreHigh = DAG.getTruncStore(Chain, dl, High, HighAddr, 485198090Srdivacky ST->getSrcValue(), SVOffset + 2, 486198090Srdivacky MVT::i16, ST->isVolatile(), 2); 487198090Srdivacky return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, StoreLow, StoreHigh); 488198090Srdivacky } 489198090Srdivacky 490198090Srdivacky // Lower to a call to __misaligned_store(BasePtr, Value). 491198090Srdivacky const Type *IntPtrTy = getTargetData()->getIntPtrType(*DAG.getContext()); 492198090Srdivacky TargetLowering::ArgListTy Args; 493198090Srdivacky TargetLowering::ArgListEntry Entry; 494198090Srdivacky 495198090Srdivacky Entry.Ty = IntPtrTy; 496198090Srdivacky Entry.Node = BasePtr; 497198090Srdivacky Args.push_back(Entry); 498198090Srdivacky 499198090Srdivacky Entry.Node = Value; 500198090Srdivacky Args.push_back(Entry); 501198090Srdivacky 502198090Srdivacky std::pair<SDValue, SDValue> CallResult = 503198090Srdivacky LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()), false, false, 504198090Srdivacky false, false, 0, CallingConv::C, false, 505198090Srdivacky /*isReturnValueUsed=*/true, 506198090Srdivacky DAG.getExternalSymbol("__misaligned_store", getPointerTy()), 507198090Srdivacky Args, DAG, dl); 508198090Srdivacky 509198090Srdivacky return CallResult.second; 510198090Srdivacky} 511198090Srdivacky 512198090SrdivackySDValue XCoreTargetLowering:: 513193323SedExpandADDSUB(SDNode *N, SelectionDAG &DAG) 514193323Sed{ 515193323Sed assert(N->getValueType(0) == MVT::i64 && 516193323Sed (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && 517193323Sed "Unknown operand to lower!"); 518193323Sed DebugLoc dl = N->getDebugLoc(); 519193323Sed 520193323Sed // Extract components 521193323Sed SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 522193323Sed N->getOperand(0), DAG.getConstant(0, MVT::i32)); 523193323Sed SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 524193323Sed N->getOperand(0), DAG.getConstant(1, MVT::i32)); 525193323Sed SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 526193323Sed N->getOperand(1), DAG.getConstant(0, MVT::i32)); 527193323Sed SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 528193323Sed N->getOperand(1), DAG.getConstant(1, MVT::i32)); 529193323Sed 530193323Sed // Expand 531193323Sed unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD : 532193323Sed XCoreISD::LSUB; 533193323Sed SDValue Zero = DAG.getConstant(0, MVT::i32); 534193323Sed SDValue Carry = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), 535193323Sed LHSL, RHSL, Zero); 536193323Sed SDValue Lo(Carry.getNode(), 1); 537193323Sed 538193323Sed SDValue Ignored = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), 539193323Sed LHSH, RHSH, Carry); 540193323Sed SDValue Hi(Ignored.getNode(), 1); 541193323Sed // Merge the pieces 542193323Sed return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 543193323Sed} 544193323Sed 545193323SedSDValue XCoreTargetLowering:: 546193323SedLowerVAARG(SDValue Op, SelectionDAG &DAG) 547193323Sed{ 548198090Srdivacky llvm_unreachable("unimplemented"); 549193323Sed // FIX Arguments passed by reference need a extra dereference. 550193323Sed SDNode *Node = Op.getNode(); 551193323Sed DebugLoc dl = Node->getDebugLoc(); 552193323Sed const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 553198090Srdivacky EVT VT = Node->getValueType(0); 554193323Sed SDValue VAList = DAG.getLoad(getPointerTy(), dl, Node->getOperand(0), 555193323Sed Node->getOperand(1), V, 0); 556193323Sed // Increment the pointer, VAList, to the next vararg 557193323Sed SDValue Tmp3 = DAG.getNode(ISD::ADD, dl, getPointerTy(), VAList, 558193323Sed DAG.getConstant(VT.getSizeInBits(), 559193323Sed getPointerTy())); 560193323Sed // Store the incremented VAList to the legalized pointer 561193323Sed Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Node->getOperand(1), V, 0); 562193323Sed // Load the actual argument out of the pointer VAList 563193323Sed return DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0); 564193323Sed} 565193323Sed 566193323SedSDValue XCoreTargetLowering:: 567193323SedLowerVASTART(SDValue Op, SelectionDAG &DAG) 568193323Sed{ 569193323Sed DebugLoc dl = Op.getDebugLoc(); 570193323Sed // vastart stores the address of the VarArgsFrameIndex slot into the 571193323Sed // memory location argument 572193323Sed MachineFunction &MF = DAG.getMachineFunction(); 573193323Sed XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>(); 574193323Sed SDValue Addr = DAG.getFrameIndex(XFI->getVarArgsFrameIndex(), MVT::i32); 575193323Sed const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 576193323Sed return DAG.getStore(Op.getOperand(0), dl, Addr, Op.getOperand(1), SV, 0); 577193323Sed} 578193323Sed 579193323SedSDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { 580193323Sed DebugLoc dl = Op.getDebugLoc(); 581193323Sed // Depths > 0 not supported yet! 582193323Sed if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0) 583193323Sed return SDValue(); 584193323Sed 585193323Sed MachineFunction &MF = DAG.getMachineFunction(); 586193323Sed const TargetRegisterInfo *RegInfo = getTargetMachine().getRegisterInfo(); 587193323Sed return DAG.getCopyFromReg(DAG.getEntryNode(), dl, 588193323Sed RegInfo->getFrameRegister(MF), MVT::i32); 589193323Sed} 590193323Sed 591193323Sed//===----------------------------------------------------------------------===// 592193323Sed// Calling Convention Implementation 593193323Sed//===----------------------------------------------------------------------===// 594193323Sed 595193323Sed#include "XCoreGenCallingConv.inc" 596193323Sed 597193323Sed//===----------------------------------------------------------------------===// 598198090Srdivacky// Call Calling Convention Implementation 599193323Sed//===----------------------------------------------------------------------===// 600193323Sed 601198090Srdivacky/// XCore call implementation 602198090SrdivackySDValue 603198090SrdivackyXCoreTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 604198090Srdivacky CallingConv::ID CallConv, bool isVarArg, 605198090Srdivacky bool isTailCall, 606198090Srdivacky const SmallVectorImpl<ISD::OutputArg> &Outs, 607198090Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 608198090Srdivacky DebugLoc dl, SelectionDAG &DAG, 609198090Srdivacky SmallVectorImpl<SDValue> &InVals) { 610198090Srdivacky 611193323Sed // For now, only CallingConv::C implemented 612198090Srdivacky switch (CallConv) 613193323Sed { 614193323Sed default: 615198090Srdivacky llvm_unreachable("Unsupported calling convention"); 616193323Sed case CallingConv::Fast: 617193323Sed case CallingConv::C: 618198090Srdivacky return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall, 619198090Srdivacky Outs, Ins, dl, DAG, InVals); 620193323Sed } 621193323Sed} 622193323Sed 623193323Sed/// LowerCCCCallTo - functions arguments are copied from virtual 624193323Sed/// regs to (physical regs)/(stack frame), CALLSEQ_START and 625193323Sed/// CALLSEQ_END are emitted. 626193323Sed/// TODO: isTailCall, sret. 627198090SrdivackySDValue 628198090SrdivackyXCoreTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee, 629198090Srdivacky CallingConv::ID CallConv, bool isVarArg, 630198090Srdivacky bool isTailCall, 631198090Srdivacky const SmallVectorImpl<ISD::OutputArg> &Outs, 632198090Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 633198090Srdivacky DebugLoc dl, SelectionDAG &DAG, 634198090Srdivacky SmallVectorImpl<SDValue> &InVals) { 635193323Sed 636193323Sed // Analyze operands of the call, assigning locations to each operand. 637193323Sed SmallVector<CCValAssign, 16> ArgLocs; 638198090Srdivacky CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 639198090Srdivacky ArgLocs, *DAG.getContext()); 640193323Sed 641193323Sed // The ABI dictates there should be one stack slot available to the callee 642193323Sed // on function entry (for saving lr). 643193323Sed CCInfo.AllocateStack(4, 4); 644193323Sed 645198090Srdivacky CCInfo.AnalyzeCallOperands(Outs, CC_XCore); 646193323Sed 647193323Sed // Get a count of how many bytes are to be pushed on the stack. 648193323Sed unsigned NumBytes = CCInfo.getNextStackOffset(); 649193323Sed 650193323Sed Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, 651193323Sed getPointerTy(), true)); 652193323Sed 653193323Sed SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass; 654193323Sed SmallVector<SDValue, 12> MemOpChains; 655193323Sed 656193323Sed // Walk the register/memloc assignments, inserting copies/loads. 657193323Sed for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 658193323Sed CCValAssign &VA = ArgLocs[i]; 659198090Srdivacky SDValue Arg = Outs[i].Val; 660193323Sed 661193323Sed // Promote the value if needed. 662193323Sed switch (VA.getLocInfo()) { 663198090Srdivacky default: llvm_unreachable("Unknown loc info!"); 664193323Sed case CCValAssign::Full: break; 665193323Sed case CCValAssign::SExt: 666193323Sed Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 667193323Sed break; 668193323Sed case CCValAssign::ZExt: 669193323Sed Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 670193323Sed break; 671193323Sed case CCValAssign::AExt: 672193323Sed Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 673193323Sed break; 674193323Sed } 675193323Sed 676193323Sed // Arguments that can be passed on register must be kept at 677193323Sed // RegsToPass vector 678193323Sed if (VA.isRegLoc()) { 679193323Sed RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 680193323Sed } else { 681193323Sed assert(VA.isMemLoc()); 682193323Sed 683193323Sed int Offset = VA.getLocMemOffset(); 684193323Sed 685193323Sed MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, MVT::Other, 686193323Sed Chain, Arg, 687193323Sed DAG.getConstant(Offset/4, MVT::i32))); 688193323Sed } 689193323Sed } 690193323Sed 691193323Sed // Transform all store nodes into one single node because 692193323Sed // all store nodes are independent of each other. 693193323Sed if (!MemOpChains.empty()) 694193323Sed Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 695193323Sed &MemOpChains[0], MemOpChains.size()); 696193323Sed 697193323Sed // Build a sequence of copy-to-reg nodes chained together with token 698193323Sed // chain and flag operands which copy the outgoing args into registers. 699193323Sed // The InFlag in necessary since all emited instructions must be 700193323Sed // stuck together. 701193323Sed SDValue InFlag; 702193323Sed for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 703193323Sed Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 704193323Sed RegsToPass[i].second, InFlag); 705193323Sed InFlag = Chain.getValue(1); 706193323Sed } 707193323Sed 708193323Sed // If the callee is a GlobalAddress node (quite common, every direct call is) 709193323Sed // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 710193323Sed // Likewise ExternalSymbol -> TargetExternalSymbol. 711193323Sed if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 712193323Sed Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 713193323Sed else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 714193323Sed Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 715193323Sed 716193323Sed // XCoreBranchLink = #chain, #target_address, #opt_in_flags... 717193323Sed // = Chain, Callee, Reg#1, Reg#2, ... 718193323Sed // 719193323Sed // Returns a chain & a flag for retval copy to use. 720193323Sed SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 721193323Sed SmallVector<SDValue, 8> Ops; 722193323Sed Ops.push_back(Chain); 723193323Sed Ops.push_back(Callee); 724193323Sed 725193323Sed // Add argument registers to the end of the list so that they are 726193323Sed // known live into the call. 727193323Sed for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 728193323Sed Ops.push_back(DAG.getRegister(RegsToPass[i].first, 729193323Sed RegsToPass[i].second.getValueType())); 730193323Sed 731193323Sed if (InFlag.getNode()) 732193323Sed Ops.push_back(InFlag); 733193323Sed 734193323Sed Chain = DAG.getNode(XCoreISD::BL, dl, NodeTys, &Ops[0], Ops.size()); 735193323Sed InFlag = Chain.getValue(1); 736193323Sed 737193323Sed // Create the CALLSEQ_END node. 738193323Sed Chain = DAG.getCALLSEQ_END(Chain, 739193323Sed DAG.getConstant(NumBytes, getPointerTy(), true), 740193323Sed DAG.getConstant(0, getPointerTy(), true), 741193323Sed InFlag); 742193323Sed InFlag = Chain.getValue(1); 743193323Sed 744193323Sed // Handle result values, copying them out of physregs into vregs that we 745193323Sed // return. 746198090Srdivacky return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 747198090Srdivacky Ins, dl, DAG, InVals); 748193323Sed} 749193323Sed 750198090Srdivacky/// LowerCallResult - Lower the result values of a call into the 751198090Srdivacky/// appropriate copies out of appropriate physical registers. 752198090SrdivackySDValue 753198090SrdivackyXCoreTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 754198090Srdivacky CallingConv::ID CallConv, bool isVarArg, 755198090Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 756198090Srdivacky DebugLoc dl, SelectionDAG &DAG, 757198090Srdivacky SmallVectorImpl<SDValue> &InVals) { 758193323Sed 759193323Sed // Assign locations to each value returned by this call. 760193323Sed SmallVector<CCValAssign, 16> RVLocs; 761198090Srdivacky CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 762198090Srdivacky RVLocs, *DAG.getContext()); 763193323Sed 764198090Srdivacky CCInfo.AnalyzeCallResult(Ins, RetCC_XCore); 765193323Sed 766193323Sed // Copy all of the result registers out of their specified physreg. 767193323Sed for (unsigned i = 0; i != RVLocs.size(); ++i) { 768193323Sed Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 769193323Sed RVLocs[i].getValVT(), InFlag).getValue(1); 770193323Sed InFlag = Chain.getValue(2); 771198090Srdivacky InVals.push_back(Chain.getValue(0)); 772193323Sed } 773193323Sed 774198090Srdivacky return Chain; 775193323Sed} 776193323Sed 777193323Sed//===----------------------------------------------------------------------===// 778198090Srdivacky// Formal Arguments Calling Convention Implementation 779193323Sed//===----------------------------------------------------------------------===// 780193323Sed 781198090Srdivacky/// XCore formal arguments implementation 782198090SrdivackySDValue 783198090SrdivackyXCoreTargetLowering::LowerFormalArguments(SDValue Chain, 784198090Srdivacky CallingConv::ID CallConv, 785198090Srdivacky bool isVarArg, 786198090Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 787198090Srdivacky DebugLoc dl, 788198090Srdivacky SelectionDAG &DAG, 789198090Srdivacky SmallVectorImpl<SDValue> &InVals) { 790198090Srdivacky switch (CallConv) 791193323Sed { 792193323Sed default: 793198090Srdivacky llvm_unreachable("Unsupported calling convention"); 794193323Sed case CallingConv::C: 795193323Sed case CallingConv::Fast: 796198090Srdivacky return LowerCCCArguments(Chain, CallConv, isVarArg, 797198090Srdivacky Ins, dl, DAG, InVals); 798193323Sed } 799193323Sed} 800193323Sed 801193323Sed/// LowerCCCArguments - transform physical registers into 802193323Sed/// virtual registers and generate load operations for 803193323Sed/// arguments places on the stack. 804193323Sed/// TODO: sret 805198090SrdivackySDValue 806198090SrdivackyXCoreTargetLowering::LowerCCCArguments(SDValue Chain, 807198090Srdivacky CallingConv::ID CallConv, 808198090Srdivacky bool isVarArg, 809198090Srdivacky const SmallVectorImpl<ISD::InputArg> 810198090Srdivacky &Ins, 811198090Srdivacky DebugLoc dl, 812198090Srdivacky SelectionDAG &DAG, 813198090Srdivacky SmallVectorImpl<SDValue> &InVals) { 814193323Sed MachineFunction &MF = DAG.getMachineFunction(); 815193323Sed MachineFrameInfo *MFI = MF.getFrameInfo(); 816193323Sed MachineRegisterInfo &RegInfo = MF.getRegInfo(); 817193323Sed 818193323Sed // Assign locations to all of the incoming arguments. 819193323Sed SmallVector<CCValAssign, 16> ArgLocs; 820198090Srdivacky CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 821198090Srdivacky ArgLocs, *DAG.getContext()); 822193323Sed 823198090Srdivacky CCInfo.AnalyzeFormalArguments(Ins, CC_XCore); 824193323Sed 825193323Sed unsigned StackSlotSize = XCoreFrameInfo::stackSlotSize(); 826193323Sed 827193323Sed unsigned LRSaveSize = StackSlotSize; 828193323Sed 829193323Sed for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 830193323Sed 831193323Sed CCValAssign &VA = ArgLocs[i]; 832193323Sed 833193323Sed if (VA.isRegLoc()) { 834193323Sed // Arguments passed in registers 835198090Srdivacky EVT RegVT = VA.getLocVT(); 836198090Srdivacky switch (RegVT.getSimpleVT().SimpleTy) { 837193323Sed default: 838198090Srdivacky { 839198090Srdivacky#ifndef NDEBUG 840198090Srdivacky errs() << "LowerFormalArguments Unhandled argument type: " 841198090Srdivacky << RegVT.getSimpleVT().SimpleTy << "\n"; 842198090Srdivacky#endif 843198090Srdivacky llvm_unreachable(0); 844198090Srdivacky } 845193323Sed case MVT::i32: 846193323Sed unsigned VReg = RegInfo.createVirtualRegister( 847193323Sed XCore::GRRegsRegisterClass); 848193323Sed RegInfo.addLiveIn(VA.getLocReg(), VReg); 849198090Srdivacky InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); 850193323Sed } 851193323Sed } else { 852193323Sed // sanity check 853193323Sed assert(VA.isMemLoc()); 854193323Sed // Load the argument to a virtual register 855193323Sed unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; 856193323Sed if (ObjSize > StackSlotSize) { 857198090Srdivacky errs() << "LowerFormalArguments Unhandled argument type: " 858198090Srdivacky << (unsigned)VA.getLocVT().getSimpleVT().SimpleTy 859198090Srdivacky << "\n"; 860193323Sed } 861193323Sed // Create the frame index object for this incoming parameter... 862193323Sed int FI = MFI->CreateFixedObject(ObjSize, 863199481Srdivacky LRSaveSize + VA.getLocMemOffset(), 864199481Srdivacky true, false); 865193323Sed 866193323Sed // Create the SelectionDAG nodes corresponding to a load 867193323Sed //from this parameter 868193323Sed SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); 869198090Srdivacky InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, NULL, 0)); 870193323Sed } 871193323Sed } 872193323Sed 873193323Sed if (isVarArg) { 874193323Sed /* Argument registers */ 875193323Sed static const unsigned ArgRegs[] = { 876193323Sed XCore::R0, XCore::R1, XCore::R2, XCore::R3 877193323Sed }; 878193323Sed XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>(); 879193323Sed unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs, 880193323Sed array_lengthof(ArgRegs)); 881193323Sed if (FirstVAReg < array_lengthof(ArgRegs)) { 882193323Sed SmallVector<SDValue, 4> MemOps; 883193323Sed int offset = 0; 884193323Sed // Save remaining registers, storing higher register numbers at a higher 885193323Sed // address 886193323Sed for (unsigned i = array_lengthof(ArgRegs) - 1; i >= FirstVAReg; --i) { 887193323Sed // Create a stack slot 888199481Srdivacky int FI = MFI->CreateFixedObject(4, offset, true, false); 889193323Sed if (i == FirstVAReg) { 890193323Sed XFI->setVarArgsFrameIndex(FI); 891193323Sed } 892193323Sed offset -= StackSlotSize; 893193323Sed SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); 894193323Sed // Move argument from phys reg -> virt reg 895193323Sed unsigned VReg = RegInfo.createVirtualRegister( 896193323Sed XCore::GRRegsRegisterClass); 897193323Sed RegInfo.addLiveIn(ArgRegs[i], VReg); 898198090Srdivacky SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 899193323Sed // Move argument from virt reg -> stack 900193323Sed SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0); 901193323Sed MemOps.push_back(Store); 902193323Sed } 903193323Sed if (!MemOps.empty()) 904198090Srdivacky Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 905198090Srdivacky &MemOps[0], MemOps.size()); 906193323Sed } else { 907193323Sed // This will point to the next argument passed via stack. 908193323Sed XFI->setVarArgsFrameIndex( 909199481Srdivacky MFI->CreateFixedObject(4, LRSaveSize + CCInfo.getNextStackOffset(), 910199481Srdivacky true, false)); 911193323Sed } 912193323Sed } 913193323Sed 914198090Srdivacky return Chain; 915193323Sed} 916193323Sed 917193323Sed//===----------------------------------------------------------------------===// 918193323Sed// Return Value Calling Convention Implementation 919193323Sed//===----------------------------------------------------------------------===// 920193323Sed 921199481Srdivackybool XCoreTargetLowering:: 922199481SrdivackyCanLowerReturn(CallingConv::ID CallConv, bool isVarArg, 923199481Srdivacky const SmallVectorImpl<EVT> &OutTys, 924199481Srdivacky const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags, 925199481Srdivacky SelectionDAG &DAG) { 926199481Srdivacky SmallVector<CCValAssign, 16> RVLocs; 927199481Srdivacky CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 928199481Srdivacky RVLocs, *DAG.getContext()); 929199481Srdivacky return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_XCore); 930199481Srdivacky} 931199481Srdivacky 932198090SrdivackySDValue 933198090SrdivackyXCoreTargetLowering::LowerReturn(SDValue Chain, 934198090Srdivacky CallingConv::ID CallConv, bool isVarArg, 935198090Srdivacky const SmallVectorImpl<ISD::OutputArg> &Outs, 936198090Srdivacky DebugLoc dl, SelectionDAG &DAG) { 937198090Srdivacky 938193323Sed // CCValAssign - represent the assignment of 939193323Sed // the return value to a location 940193323Sed SmallVector<CCValAssign, 16> RVLocs; 941193323Sed 942193323Sed // CCState - Info about the registers and stack slot. 943198090Srdivacky CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 944198090Srdivacky RVLocs, *DAG.getContext()); 945193323Sed 946198090Srdivacky // Analize return values. 947198090Srdivacky CCInfo.AnalyzeReturn(Outs, RetCC_XCore); 948193323Sed 949193323Sed // If this is the first return lowered for this function, add 950193323Sed // the regs to the liveout set for the function. 951193323Sed if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 952193323Sed for (unsigned i = 0; i != RVLocs.size(); ++i) 953193323Sed if (RVLocs[i].isRegLoc()) 954193323Sed DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 955193323Sed } 956193323Sed 957193323Sed SDValue Flag; 958193323Sed 959193323Sed // Copy the result values into the output registers. 960193323Sed for (unsigned i = 0; i != RVLocs.size(); ++i) { 961193323Sed CCValAssign &VA = RVLocs[i]; 962193323Sed assert(VA.isRegLoc() && "Can only return in registers!"); 963193323Sed 964193323Sed Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 965198090Srdivacky Outs[i].Val, Flag); 966193323Sed 967193323Sed // guarantee that all emitted copies are 968193323Sed // stuck together, avoiding something bad 969193323Sed Flag = Chain.getValue(1); 970193323Sed } 971193323Sed 972193323Sed // Return on XCore is always a "retsp 0" 973193323Sed if (Flag.getNode()) 974193323Sed return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other, 975193323Sed Chain, DAG.getConstant(0, MVT::i32), Flag); 976193323Sed else // Return Void 977193323Sed return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other, 978193323Sed Chain, DAG.getConstant(0, MVT::i32)); 979193323Sed} 980193323Sed 981193323Sed//===----------------------------------------------------------------------===// 982193323Sed// Other Lowering Code 983193323Sed//===----------------------------------------------------------------------===// 984193323Sed 985193323SedMachineBasicBlock * 986193323SedXCoreTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 987198090Srdivacky MachineBasicBlock *BB, 988198090Srdivacky DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 989193323Sed const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 990193323Sed DebugLoc dl = MI->getDebugLoc(); 991193323Sed assert((MI->getOpcode() == XCore::SELECT_CC) && 992193323Sed "Unexpected instr type to insert"); 993193323Sed 994193323Sed // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 995193323Sed // control-flow pattern. The incoming instruction knows the destination vreg 996193323Sed // to set, the condition code register to branch on, the true/false values to 997193323Sed // select between, and a branch opcode to use. 998193323Sed const BasicBlock *LLVM_BB = BB->getBasicBlock(); 999193323Sed MachineFunction::iterator It = BB; 1000193323Sed ++It; 1001193323Sed 1002193323Sed // thisMBB: 1003193323Sed // ... 1004193323Sed // TrueVal = ... 1005193323Sed // cmpTY ccX, r1, r2 1006193323Sed // bCC copy1MBB 1007193323Sed // fallthrough --> copy0MBB 1008193323Sed MachineBasicBlock *thisMBB = BB; 1009193323Sed MachineFunction *F = BB->getParent(); 1010193323Sed MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 1011193323Sed MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 1012193323Sed BuildMI(BB, dl, TII.get(XCore::BRFT_lru6)) 1013193323Sed .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 1014193323Sed F->insert(It, copy0MBB); 1015193323Sed F->insert(It, sinkMBB); 1016198090Srdivacky // Update machine-CFG edges by first adding all successors of the current 1017193323Sed // block to the new block which will contain the Phi node for the select. 1018198090Srdivacky // Also inform sdisel of the edge changes. 1019198090Srdivacky for (MachineBasicBlock::succ_iterator I = BB->succ_begin(), 1020198090Srdivacky E = BB->succ_end(); I != E; ++I) { 1021198090Srdivacky EM->insert(std::make_pair(*I, sinkMBB)); 1022198090Srdivacky sinkMBB->addSuccessor(*I); 1023198090Srdivacky } 1024198090Srdivacky // Next, remove all successors of the current block, and add the true 1025198090Srdivacky // and fallthrough blocks as its successors. 1026198090Srdivacky while (!BB->succ_empty()) 1027198090Srdivacky BB->removeSuccessor(BB->succ_begin()); 1028193323Sed // Next, add the true and fallthrough blocks as its successors. 1029193323Sed BB->addSuccessor(copy0MBB); 1030193323Sed BB->addSuccessor(sinkMBB); 1031193323Sed 1032193323Sed // copy0MBB: 1033193323Sed // %FalseValue = ... 1034193323Sed // # fallthrough to sinkMBB 1035193323Sed BB = copy0MBB; 1036193323Sed 1037193323Sed // Update machine-CFG edges 1038193323Sed BB->addSuccessor(sinkMBB); 1039193323Sed 1040193323Sed // sinkMBB: 1041193323Sed // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1042193323Sed // ... 1043193323Sed BB = sinkMBB; 1044193323Sed BuildMI(BB, dl, TII.get(XCore::PHI), MI->getOperand(0).getReg()) 1045193323Sed .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 1046193323Sed .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 1047193323Sed 1048193323Sed F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 1049193323Sed return BB; 1050193323Sed} 1051193323Sed 1052193323Sed//===----------------------------------------------------------------------===// 1053198090Srdivacky// Target Optimization Hooks 1054198090Srdivacky//===----------------------------------------------------------------------===// 1055198090Srdivacky 1056198090SrdivackySDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N, 1057198090Srdivacky DAGCombinerInfo &DCI) const { 1058198090Srdivacky SelectionDAG &DAG = DCI.DAG; 1059198090Srdivacky DebugLoc dl = N->getDebugLoc(); 1060198090Srdivacky switch (N->getOpcode()) { 1061198090Srdivacky default: break; 1062198090Srdivacky case ISD::STORE: { 1063198090Srdivacky // Replace unaligned store of unaligned load with memmove. 1064198090Srdivacky StoreSDNode *ST = cast<StoreSDNode>(N); 1065198090Srdivacky if (!DCI.isBeforeLegalize() || 1066198090Srdivacky allowsUnalignedMemoryAccesses(ST->getMemoryVT()) || 1067198090Srdivacky ST->isVolatile() || ST->isIndexed()) { 1068198090Srdivacky break; 1069198090Srdivacky } 1070198090Srdivacky SDValue Chain = ST->getChain(); 1071198090Srdivacky 1072198090Srdivacky unsigned StoreBits = ST->getMemoryVT().getStoreSizeInBits(); 1073198090Srdivacky if (StoreBits % 8) { 1074198090Srdivacky break; 1075198090Srdivacky } 1076198090Srdivacky unsigned ABIAlignment = getTargetData()->getABITypeAlignment( 1077198090Srdivacky ST->getMemoryVT().getTypeForEVT(*DCI.DAG.getContext())); 1078198090Srdivacky unsigned Alignment = ST->getAlignment(); 1079198090Srdivacky if (Alignment >= ABIAlignment) { 1080198090Srdivacky break; 1081198090Srdivacky } 1082198090Srdivacky 1083198090Srdivacky if (LoadSDNode *LD = dyn_cast<LoadSDNode>(ST->getValue())) { 1084198090Srdivacky if (LD->hasNUsesOfValue(1, 0) && ST->getMemoryVT() == LD->getMemoryVT() && 1085198090Srdivacky LD->getAlignment() == Alignment && 1086198090Srdivacky !LD->isVolatile() && !LD->isIndexed() && 1087198090Srdivacky Chain.reachesChainWithoutSideEffects(SDValue(LD, 1))) { 1088198090Srdivacky return DAG.getMemmove(Chain, dl, ST->getBasePtr(), 1089198090Srdivacky LD->getBasePtr(), 1090198090Srdivacky DAG.getConstant(StoreBits/8, MVT::i32), 1091198090Srdivacky Alignment, ST->getSrcValue(), 1092198090Srdivacky ST->getSrcValueOffset(), LD->getSrcValue(), 1093198090Srdivacky LD->getSrcValueOffset()); 1094198090Srdivacky } 1095198090Srdivacky } 1096198090Srdivacky break; 1097198090Srdivacky } 1098198090Srdivacky } 1099198090Srdivacky return SDValue(); 1100198090Srdivacky} 1101198090Srdivacky 1102198090Srdivacky//===----------------------------------------------------------------------===// 1103193323Sed// Addressing mode description hooks 1104193323Sed//===----------------------------------------------------------------------===// 1105193323Sed 1106193323Sedstatic inline bool isImmUs(int64_t val) 1107193323Sed{ 1108193323Sed return (val >= 0 && val <= 11); 1109193323Sed} 1110193323Sed 1111193323Sedstatic inline bool isImmUs2(int64_t val) 1112193323Sed{ 1113193323Sed return (val%2 == 0 && isImmUs(val/2)); 1114193323Sed} 1115193323Sed 1116193323Sedstatic inline bool isImmUs4(int64_t val) 1117193323Sed{ 1118193323Sed return (val%4 == 0 && isImmUs(val/4)); 1119193323Sed} 1120193323Sed 1121193323Sed/// isLegalAddressingMode - Return true if the addressing mode represented 1122193323Sed/// by AM is legal for this target, for a load/store of the specified type. 1123193323Sedbool 1124193323SedXCoreTargetLowering::isLegalAddressingMode(const AddrMode &AM, 1125193323Sed const Type *Ty) const { 1126198090Srdivacky // Be conservative with void 1127198090Srdivacky // FIXME: Can we be more aggressive? 1128198090Srdivacky if (Ty->getTypeID() == Type::VoidTyID) 1129198090Srdivacky return false; 1130198090Srdivacky 1131198090Srdivacky const TargetData *TD = TM.getTargetData(); 1132198090Srdivacky unsigned Size = TD->getTypeAllocSize(Ty); 1133193323Sed if (AM.BaseGV) { 1134198090Srdivacky return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 && 1135193323Sed AM.BaseOffs%4 == 0; 1136193323Sed } 1137193323Sed 1138198090Srdivacky switch (Size) { 1139198090Srdivacky case 1: 1140193323Sed // reg + imm 1141193323Sed if (AM.Scale == 0) { 1142193323Sed return isImmUs(AM.BaseOffs); 1143193323Sed } 1144198090Srdivacky // reg + reg 1145193323Sed return AM.Scale == 1 && AM.BaseOffs == 0; 1146198090Srdivacky case 2: 1147198090Srdivacky case 3: 1148193323Sed // reg + imm 1149193323Sed if (AM.Scale == 0) { 1150193323Sed return isImmUs2(AM.BaseOffs); 1151193323Sed } 1152198090Srdivacky // reg + reg<<1 1153193323Sed return AM.Scale == 2 && AM.BaseOffs == 0; 1154198090Srdivacky default: 1155193323Sed // reg + imm 1156193323Sed if (AM.Scale == 0) { 1157193323Sed return isImmUs4(AM.BaseOffs); 1158193323Sed } 1159193323Sed // reg + reg<<2 1160193323Sed return AM.Scale == 4 && AM.BaseOffs == 0; 1161193323Sed } 1162193323Sed 1163193323Sed return false; 1164193323Sed} 1165193323Sed 1166193323Sed//===----------------------------------------------------------------------===// 1167193323Sed// XCore Inline Assembly Support 1168193323Sed//===----------------------------------------------------------------------===// 1169193323Sed 1170193323Sedstd::vector<unsigned> XCoreTargetLowering:: 1171193323SedgetRegClassForInlineAsmConstraint(const std::string &Constraint, 1172198090Srdivacky EVT VT) const 1173193323Sed{ 1174193323Sed if (Constraint.size() != 1) 1175193323Sed return std::vector<unsigned>(); 1176193323Sed 1177193323Sed switch (Constraint[0]) { 1178193323Sed default : break; 1179193323Sed case 'r': 1180193323Sed return make_vector<unsigned>(XCore::R0, XCore::R1, XCore::R2, 1181193323Sed XCore::R3, XCore::R4, XCore::R5, 1182193323Sed XCore::R6, XCore::R7, XCore::R8, 1183193323Sed XCore::R9, XCore::R10, XCore::R11, 0); 1184193323Sed break; 1185193323Sed } 1186193323Sed return std::vector<unsigned>(); 1187193323Sed} 1188