XCoreISelDAGToDAG.cpp revision 221345 
1//===-- XCoreISelDAGToDAG.cpp - A dag to dag inst selector for XCore ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the XCore target.
11//
12//===----------------------------------------------------------------------===//
13
14#include "XCore.h"
15#include "XCoreTargetMachine.h"
16#include "llvm/DerivedTypes.h"
17#include "llvm/Function.h"
18#include "llvm/Intrinsics.h"
19#include "llvm/CallingConv.h"
20#include "llvm/Constants.h"
21#include "llvm/LLVMContext.h"
22#include "llvm/CodeGen/MachineFrameInfo.h"
23#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/MachineInstrBuilder.h"
25#include "llvm/CodeGen/MachineRegisterInfo.h"
26#include "llvm/CodeGen/SelectionDAG.h"
27#include "llvm/CodeGen/SelectionDAGISel.h"
28#include "llvm/Target/TargetLowering.h"
29#include "llvm/Support/Compiler.h"
30#include "llvm/Support/Debug.h"
31#include "llvm/Support/ErrorHandling.h"
32#include "llvm/Support/raw_ostream.h"
33using namespace llvm;
34
35/// XCoreDAGToDAGISel - XCore specific code to select XCore machine
36/// instructions for SelectionDAG operations.
37///
38namespace {
39  class XCoreDAGToDAGISel : public SelectionDAGISel {
40    const XCoreTargetLowering &Lowering;
41    const XCoreSubtarget &Subtarget;
42
43  public:
44    XCoreDAGToDAGISel(XCoreTargetMachine &TM)
45      : SelectionDAGISel(TM),
46        Lowering(*TM.getTargetLowering()),
47        Subtarget(*TM.getSubtargetImpl()) { }
48
49    SDNode *Select(SDNode *N);
50    SDNode *SelectBRIND(SDNode *N);
51
52    /// getI32Imm - Return a target constant with the specified value, of type
53    /// i32.
54    inline SDValue getI32Imm(unsigned Imm) {
55      return CurDAG->getTargetConstant(Imm, MVT::i32);
56    }
57
58    inline bool immMskBitp(SDNode *inN) const {
59      ConstantSDNode *N = cast<ConstantSDNode>(inN);
60      uint32_t value = (uint32_t)N->getZExtValue();
61      if (!isMask_32(value)) {
62        return false;
63      }
64      int msksize = 32 - CountLeadingZeros_32(value);
65      return (msksize >= 1 && msksize <= 8) ||
66              msksize == 16 || msksize == 24 || msksize == 32;
67    }
68
69    // Complex Pattern Selectors.
70    bool SelectADDRspii(SDValue Addr, SDValue &Base, SDValue &Offset);
71    bool SelectADDRdpii(SDValue Addr, SDValue &Base, SDValue &Offset);
72    bool SelectADDRcpii(SDValue Addr, SDValue &Base, SDValue &Offset);
73
74    virtual const char *getPassName() const {
75      return "XCore DAG->DAG Pattern Instruction Selection";
76    }
77
78    // Include the pieces autogenerated from the target description.
79  #include "XCoreGenDAGISel.inc"
80  };
81}  // end anonymous namespace
82
83/// createXCoreISelDag - This pass converts a legalized DAG into a
84/// XCore-specific DAG, ready for instruction scheduling.
85///
86FunctionPass *llvm::createXCoreISelDag(XCoreTargetMachine &TM) {
87  return new XCoreDAGToDAGISel(TM);
88}
89
90bool XCoreDAGToDAGISel::SelectADDRspii(SDValue Addr, SDValue &Base,
91                                       SDValue &Offset) {
92  FrameIndexSDNode *FIN = 0;
93  if ((FIN = dyn_cast<FrameIndexSDNode>(Addr))) {
94    Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
95    Offset = CurDAG->getTargetConstant(0, MVT::i32);
96    return true;
97  }
98  if (Addr.getOpcode() == ISD::ADD) {
99    ConstantSDNode *CN = 0;
100    if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
101      && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
102      && (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) {
103      // Constant positive word offset from frame index
104      Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
105      Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
106      return true;
107    }
108  }
109  return false;
110}
111
112bool XCoreDAGToDAGISel::SelectADDRdpii(SDValue Addr, SDValue &Base,
113                                       SDValue &Offset) {
114  if (Addr.getOpcode() == XCoreISD::DPRelativeWrapper) {
115    Base = Addr.getOperand(0);
116    Offset = CurDAG->getTargetConstant(0, MVT::i32);
117    return true;
118  }
119  if (Addr.getOpcode() == ISD::ADD) {
120    ConstantSDNode *CN = 0;
121    if ((Addr.getOperand(0).getOpcode() == XCoreISD::DPRelativeWrapper)
122      && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
123      && (CN->getSExtValue() % 4 == 0)) {
124      // Constant word offset from a object in the data region
125      Base = Addr.getOperand(0).getOperand(0);
126      Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
127      return true;
128    }
129  }
130  return false;
131}
132
133bool XCoreDAGToDAGISel::SelectADDRcpii(SDValue Addr, SDValue &Base,
134                                       SDValue &Offset) {
135  if (Addr.getOpcode() == XCoreISD::CPRelativeWrapper) {
136    Base = Addr.getOperand(0);
137    Offset = CurDAG->getTargetConstant(0, MVT::i32);
138    return true;
139  }
140  if (Addr.getOpcode() == ISD::ADD) {
141    ConstantSDNode *CN = 0;
142    if ((Addr.getOperand(0).getOpcode() == XCoreISD::CPRelativeWrapper)
143      && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
144      && (CN->getSExtValue() % 4 == 0)) {
145      // Constant word offset from a object in the data region
146      Base = Addr.getOperand(0).getOperand(0);
147      Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
148      return true;
149    }
150  }
151  return false;
152}
153
154SDNode *XCoreDAGToDAGISel::Select(SDNode *N) {
155  DebugLoc dl = N->getDebugLoc();
156  switch (N->getOpcode()) {
157  default: break;
158  case ISD::Constant: {
159    uint64_t Val = cast<ConstantSDNode>(N)->getZExtValue();
160    if (immMskBitp(N)) {
161      // Transformation function: get the size of a mask
162      // Look for the first non-zero bit
163      SDValue MskSize = getI32Imm(32 - CountLeadingZeros_32(Val));
164      return CurDAG->getMachineNode(XCore::MKMSK_rus, dl,
165                                    MVT::i32, MskSize);
166    }
167    else if (!isUInt<16>(Val)) {
168      SDValue CPIdx =
169        CurDAG->getTargetConstantPool(ConstantInt::get(
170                              Type::getInt32Ty(*CurDAG->getContext()), Val),
171                                      TLI.getPointerTy());
172      return CurDAG->getMachineNode(XCore::LDWCP_lru6, dl, MVT::i32,
173                                    MVT::Other, CPIdx,
174                                    CurDAG->getEntryNode());
175    }
176    break;
177  }
178  case XCoreISD::LADD: {
179    SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
180                        N->getOperand(2) };
181    return CurDAG->getMachineNode(XCore::LADD_l5r, dl, MVT::i32, MVT::i32,
182                                  Ops, 3);
183  }
184  case XCoreISD::LSUB: {
185    SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
186                        N->getOperand(2) };
187    return CurDAG->getMachineNode(XCore::LSUB_l5r, dl, MVT::i32, MVT::i32,
188                                  Ops, 3);
189  }
190  case XCoreISD::MACCU: {
191    SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
192                      N->getOperand(2), N->getOperand(3) };
193    return CurDAG->getMachineNode(XCore::MACCU_l4r, dl, MVT::i32, MVT::i32,
194                                  Ops, 4);
195  }
196  case XCoreISD::MACCS: {
197    SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
198                      N->getOperand(2), N->getOperand(3) };
199    return CurDAG->getMachineNode(XCore::MACCS_l4r, dl, MVT::i32, MVT::i32,
200                                  Ops, 4);
201  }
202  case XCoreISD::LMUL: {
203    SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
204                      N->getOperand(2), N->getOperand(3) };
205    return CurDAG->getMachineNode(XCore::LMUL_l6r, dl, MVT::i32, MVT::i32,
206                                  Ops, 4);
207  }
208  case ISD::BRIND:
209    if (SDNode *ResNode = SelectBRIND(N))
210      return ResNode;
211    break;
212  // Other cases are autogenerated.
213  }
214  return SelectCode(N);
215}
216
217/// Given a chain return a new chain where any appearance of Old is replaced
218/// by New. There must be at most one instruction between Old and Chain and
219/// this instruction must be a TokenFactor. Returns an empty SDValue if
220/// these conditions don't hold.
221static SDValue
222replaceInChain(SelectionDAG *CurDAG, SDValue Chain, SDValue Old, SDValue New)
223{
224  if (Chain == Old)
225    return New;
226  if (Chain->getOpcode() != ISD::TokenFactor)
227    return SDValue();
228  SmallVector<SDValue, 8> Ops;
229  bool found = false;
230  for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) {
231    if (Chain->getOperand(i) == Old) {
232      Ops.push_back(New);
233      found = true;
234    } else {
235      Ops.push_back(Chain->getOperand(i));
236    }
237  }
238  if (!found)
239    return SDValue();
240  return CurDAG->getNode(ISD::TokenFactor, Chain->getDebugLoc(), MVT::Other,
241                         &Ops[0], Ops.size());
242}
243
244SDNode *XCoreDAGToDAGISel::SelectBRIND(SDNode *N) {
245  DebugLoc dl = N->getDebugLoc();
246  // (brind (int_xcore_checkevent (addr)))
247  SDValue Chain = N->getOperand(0);
248  SDValue Addr = N->getOperand(1);
249  if (Addr->getOpcode() != ISD::INTRINSIC_W_CHAIN)
250    return 0;
251  unsigned IntNo = cast<ConstantSDNode>(Addr->getOperand(1))->getZExtValue();
252  if (IntNo != Intrinsic::xcore_checkevent)
253    return 0;
254  SDValue nextAddr = Addr->getOperand(2);
255  SDValue CheckEventChainOut(Addr.getNode(), 1);
256  if (!CheckEventChainOut.use_empty()) {
257    // If the chain out of the checkevent intrinsic is an operand of the
258    // indirect branch or used in a TokenFactor which is the operand of the
259    // indirect branch then build a new chain which uses the chain coming into
260    // the checkevent intrinsic instead.
261    SDValue CheckEventChainIn = Addr->getOperand(0);
262    SDValue NewChain = replaceInChain(CurDAG, Chain, CheckEventChainOut,
263                                      CheckEventChainIn);
264    if (!NewChain.getNode())
265      return 0;
266    Chain = NewChain;
267  }
268  // Enable events on the thread using setsr 1 and then disable them immediately
269  // after with clrsr 1. If any resources owned by the thread are ready an event
270  // will be taken. If no resource is ready we branch to the address which was
271  // the operand to the checkevent intrinsic.
272  SDValue constOne = getI32Imm(1);
273  SDValue Glue =
274    SDValue(CurDAG->getMachineNode(XCore::SETSR_branch_u6, dl, MVT::Glue,
275                                   constOne, Chain), 0);
276  Glue =
277    SDValue(CurDAG->getMachineNode(XCore::CLRSR_branch_u6, dl, MVT::Glue,
278                                   constOne, Glue), 0);
279  if (nextAddr->getOpcode() == XCoreISD::PCRelativeWrapper &&
280      nextAddr->getOperand(0)->getOpcode() == ISD::TargetBlockAddress) {
281    return CurDAG->SelectNodeTo(N, XCore::BRFU_lu6, MVT::Other,
282                                nextAddr->getOperand(0), Glue);
283  }
284  return CurDAG->SelectNodeTo(N, XCore::BAU_1r, MVT::Other, nextAddr, Glue);
285}
286