X86Subtarget.cpp revision 249423 
1//===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the X86 specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "subtarget"
15#include "X86Subtarget.h"
16#include "X86InstrInfo.h"
17#include "llvm/IR/Attributes.h"
18#include "llvm/IR/Function.h"
19#include "llvm/IR/GlobalValue.h"
20#include "llvm/Support/Debug.h"
21#include "llvm/Support/ErrorHandling.h"
22#include "llvm/Support/Host.h"
23#include "llvm/Support/raw_ostream.h"
24#include "llvm/Target/TargetMachine.h"
25#include "llvm/Target/TargetOptions.h"
26
27#define GET_SUBTARGETINFO_TARGET_DESC
28#define GET_SUBTARGETINFO_CTOR
29#include "X86GenSubtargetInfo.inc"
30
31using namespace llvm;
32
33#if defined(_MSC_VER)
34#include <intrin.h>
35#endif
36
37/// ClassifyBlockAddressReference - Classify a blockaddress reference for the
38/// current subtarget according to how we should reference it in a non-pcrel
39/// context.
40unsigned char X86Subtarget::ClassifyBlockAddressReference() const {
41  if (isPICStyleGOT())    // 32-bit ELF targets.
42    return X86II::MO_GOTOFF;
43
44  if (isPICStyleStubPIC())   // Darwin/32 in PIC mode.
45    return X86II::MO_PIC_BASE_OFFSET;
46
47  // Direct static reference to label.
48  return X86II::MO_NO_FLAG;
49}
50
51/// ClassifyGlobalReference - Classify a global variable reference for the
52/// current subtarget according to how we should reference it in a non-pcrel
53/// context.
54unsigned char X86Subtarget::
55ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const {
56  // DLLImport only exists on windows, it is implemented as a load from a
57  // DLLIMPORT stub.
58  if (GV->hasDLLImportLinkage())
59    return X86II::MO_DLLIMPORT;
60
61  // Determine whether this is a reference to a definition or a declaration.
62  // Materializable GVs (in JIT lazy compilation mode) do not require an extra
63  // load from stub.
64  bool isDecl = GV->hasAvailableExternallyLinkage();
65  if (GV->isDeclaration() && !GV->isMaterializable())
66    isDecl = true;
67
68  // X86-64 in PIC mode.
69  if (isPICStyleRIPRel()) {
70    // Large model never uses stubs.
71    if (TM.getCodeModel() == CodeModel::Large)
72      return X86II::MO_NO_FLAG;
73
74    if (isTargetDarwin()) {
75      // If symbol visibility is hidden, the extra load is not needed if
76      // target is x86-64 or the symbol is definitely defined in the current
77      // translation unit.
78      if (GV->hasDefaultVisibility() &&
79          (isDecl || GV->isWeakForLinker()))
80        return X86II::MO_GOTPCREL;
81    } else if (!isTargetWin64()) {
82      assert(isTargetELF() && "Unknown rip-relative target");
83
84      // Extra load is needed for all externally visible.
85      if (!GV->hasLocalLinkage() && GV->hasDefaultVisibility())
86        return X86II::MO_GOTPCREL;
87    }
88
89    return X86II::MO_NO_FLAG;
90  }
91
92  if (isPICStyleGOT()) {   // 32-bit ELF targets.
93    // Extra load is needed for all externally visible.
94    if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
95      return X86II::MO_GOTOFF;
96    return X86II::MO_GOT;
97  }
98
99  if (isPICStyleStubPIC()) {  // Darwin/32 in PIC mode.
100    // Determine whether we have a stub reference and/or whether the reference
101    // is relative to the PIC base or not.
102
103    // If this is a strong reference to a definition, it is definitely not
104    // through a stub.
105    if (!isDecl && !GV->isWeakForLinker())
106      return X86II::MO_PIC_BASE_OFFSET;
107
108    // Unless we have a symbol with hidden visibility, we have to go through a
109    // normal $non_lazy_ptr stub because this symbol might be resolved late.
110    if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
111      return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
112
113    // If symbol visibility is hidden, we have a stub for common symbol
114    // references and external declarations.
115    if (isDecl || GV->hasCommonLinkage()) {
116      // Hidden $non_lazy_ptr reference.
117      return X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE;
118    }
119
120    // Otherwise, no stub.
121    return X86II::MO_PIC_BASE_OFFSET;
122  }
123
124  if (isPICStyleStubNoDynamic()) {  // Darwin/32 in -mdynamic-no-pic mode.
125    // Determine whether we have a stub reference.
126
127    // If this is a strong reference to a definition, it is definitely not
128    // through a stub.
129    if (!isDecl && !GV->isWeakForLinker())
130      return X86II::MO_NO_FLAG;
131
132    // Unless we have a symbol with hidden visibility, we have to go through a
133    // normal $non_lazy_ptr stub because this symbol might be resolved late.
134    if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
135      return X86II::MO_DARWIN_NONLAZY;
136
137    // Otherwise, no stub.
138    return X86II::MO_NO_FLAG;
139  }
140
141  // Direct static reference to global.
142  return X86II::MO_NO_FLAG;
143}
144
145
146/// getBZeroEntry - This function returns the name of a function which has an
147/// interface like the non-standard bzero function, if such a function exists on
148/// the current subtarget and it is considered prefereable over memset with zero
149/// passed as the second argument. Otherwise it returns null.
150const char *X86Subtarget::getBZeroEntry() const {
151  // Darwin 10 has a __bzero entry point for this purpose.
152  if (getTargetTriple().isMacOSX() &&
153      !getTargetTriple().isMacOSXVersionLT(10, 6))
154    return "__bzero";
155
156  return 0;
157}
158
159bool X86Subtarget::hasSinCos() const {
160  return getTargetTriple().isMacOSX() &&
161    !getTargetTriple().isMacOSXVersionLT(10, 9) &&
162    is64Bit();
163}
164
165/// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
166/// to immediate address.
167bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
168  if (In64BitMode)
169    return false;
170  return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
171}
172
173void X86Subtarget::AutoDetectSubtargetFeatures() {
174  unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
175  unsigned MaxLevel;
176  union {
177    unsigned u[3];
178    char     c[12];
179  } text;
180
181  if (X86_MC::GetCpuIDAndInfo(0, &MaxLevel, text.u+0, text.u+2, text.u+1) ||
182      MaxLevel < 1)
183    return;
184
185  X86_MC::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
186
187  if ((EDX >> 15) & 1) { HasCMov = true;      ToggleFeature(X86::FeatureCMOV); }
188  if ((EDX >> 23) & 1) { X86SSELevel = MMX;   ToggleFeature(X86::FeatureMMX);  }
189  if ((EDX >> 25) & 1) { X86SSELevel = SSE1;  ToggleFeature(X86::FeatureSSE1); }
190  if ((EDX >> 26) & 1) { X86SSELevel = SSE2;  ToggleFeature(X86::FeatureSSE2); }
191  if (ECX & 0x1)       { X86SSELevel = SSE3;  ToggleFeature(X86::FeatureSSE3); }
192  if ((ECX >> 9)  & 1) { X86SSELevel = SSSE3; ToggleFeature(X86::FeatureSSSE3);}
193  if ((ECX >> 19) & 1) { X86SSELevel = SSE41; ToggleFeature(X86::FeatureSSE41);}
194  if ((ECX >> 20) & 1) { X86SSELevel = SSE42; ToggleFeature(X86::FeatureSSE42);}
195  if ((ECX >> 28) & 1) { X86SSELevel = AVX;   ToggleFeature(X86::FeatureAVX); }
196
197  bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
198  bool IsAMD   = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
199
200  if ((ECX >> 1) & 0x1) {
201    HasPCLMUL = true;
202    ToggleFeature(X86::FeaturePCLMUL);
203  }
204  if ((ECX >> 12) & 0x1) {
205    HasFMA = true;
206    ToggleFeature(X86::FeatureFMA);
207  }
208  if (IsIntel && ((ECX >> 22) & 0x1)) {
209    HasMOVBE = true;
210    ToggleFeature(X86::FeatureMOVBE);
211  }
212  if ((ECX >> 23) & 0x1) {
213    HasPOPCNT = true;
214    ToggleFeature(X86::FeaturePOPCNT);
215  }
216  if ((ECX >> 25) & 0x1) {
217    HasAES = true;
218    ToggleFeature(X86::FeatureAES);
219  }
220  if ((ECX >> 29) & 0x1) {
221    HasF16C = true;
222    ToggleFeature(X86::FeatureF16C);
223  }
224  if (IsIntel && ((ECX >> 30) & 0x1)) {
225    HasRDRAND = true;
226    ToggleFeature(X86::FeatureRDRAND);
227  }
228
229  if ((ECX >> 13) & 0x1) {
230    HasCmpxchg16b = true;
231    ToggleFeature(X86::FeatureCMPXCHG16B);
232  }
233
234  if (IsIntel || IsAMD) {
235    // Determine if bit test memory instructions are slow.
236    unsigned Family = 0;
237    unsigned Model  = 0;
238    X86_MC::DetectFamilyModel(EAX, Family, Model);
239    if (IsAMD || (Family == 6 && Model >= 13)) {
240      IsBTMemSlow = true;
241      ToggleFeature(X86::FeatureSlowBTMem);
242    }
243
244    // If it's an Intel chip since Nehalem and not an Atom chip, unaligned
245    // memory access is fast. We hard code model numbers here because they
246    // aren't strictly increasing for Intel chips it seems.
247    if (IsIntel &&
248        ((Family == 6 && Model == 0x1E) || // Nehalem: Clarksfield, Lynnfield,
249                                           //          Jasper Froest
250         (Family == 6 && Model == 0x1A) || // Nehalem: Bloomfield, Nehalem-EP
251         (Family == 6 && Model == 0x2E) || // Nehalem: Nehalem-EX
252         (Family == 6 && Model == 0x25) || // Westmere: Arrandale, Clarksdale
253         (Family == 6 && Model == 0x2C) || // Westmere: Gulftown, Westmere-EP
254         (Family == 6 && Model == 0x2F) || // Westmere: Westmere-EX
255         (Family == 6 && Model == 0x2A) || // SandyBridge
256         (Family == 6 && Model == 0x2D) || // SandyBridge: SandyBridge-E*
257         (Family == 6 && Model == 0x3A))) {// IvyBridge
258      IsUAMemFast = true;
259      ToggleFeature(X86::FeatureFastUAMem);
260    }
261
262    // Set processor type. Currently only Atom is detected.
263    if (Family == 6 &&
264        (Model == 28 || Model == 38 || Model == 39
265         || Model == 53 || Model == 54)) {
266      X86ProcFamily = IntelAtom;
267
268      UseLeaForSP = true;
269      ToggleFeature(X86::FeatureLeaForSP);
270    }
271
272    unsigned MaxExtLevel;
273    X86_MC::GetCpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
274
275    if (MaxExtLevel >= 0x80000001) {
276      X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
277      if ((EDX >> 29) & 0x1) {
278        HasX86_64 = true;
279        ToggleFeature(X86::Feature64Bit);
280      }
281      if ((ECX >> 5) & 0x1) {
282        HasLZCNT = true;
283        ToggleFeature(X86::FeatureLZCNT);
284      }
285      if (IsIntel && ((ECX >> 8) & 0x1)) {
286        HasPRFCHW = true;
287        ToggleFeature(X86::FeaturePRFCHW);
288      }
289      if (IsAMD) {
290        if ((ECX >> 6) & 0x1) {
291          HasSSE4A = true;
292          ToggleFeature(X86::FeatureSSE4A);
293        }
294        if ((ECX >> 11) & 0x1) {
295          HasXOP = true;
296          ToggleFeature(X86::FeatureXOP);
297        }
298        if ((ECX >> 16) & 0x1) {
299          HasFMA4 = true;
300          ToggleFeature(X86::FeatureFMA4);
301        }
302      }
303    }
304  }
305
306  if (MaxLevel >= 7) {
307    if (!X86_MC::GetCpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX)) {
308      if (IsIntel && (EBX & 0x1)) {
309        HasFSGSBase = true;
310        ToggleFeature(X86::FeatureFSGSBase);
311      }
312      if ((EBX >> 3) & 0x1) {
313        HasBMI = true;
314        ToggleFeature(X86::FeatureBMI);
315      }
316      if ((EBX >> 4) & 0x1) {
317        HasHLE = true;
318        ToggleFeature(X86::FeatureHLE);
319      }
320      if (IsIntel && ((EBX >> 5) & 0x1)) {
321        X86SSELevel = AVX2;
322        ToggleFeature(X86::FeatureAVX2);
323      }
324      if (IsIntel && ((EBX >> 8) & 0x1)) {
325        HasBMI2 = true;
326        ToggleFeature(X86::FeatureBMI2);
327      }
328      if (IsIntel && ((EBX >> 11) & 0x1)) {
329        HasRTM = true;
330        ToggleFeature(X86::FeatureRTM);
331      }
332      if (IsIntel && ((EBX >> 19) & 0x1)) {
333        HasADX = true;
334        ToggleFeature(X86::FeatureADX);
335      }
336      if (IsIntel && ((EBX >> 18) & 0x1)) {
337        HasRDSEED = true;
338        ToggleFeature(X86::FeatureRDSEED);
339      }
340    }
341  }
342}
343
344void X86Subtarget::resetSubtargetFeatures(const MachineFunction *MF) {
345  AttributeSet FnAttrs = MF->getFunction()->getAttributes();
346  Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
347                                           "target-cpu");
348  Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
349                                          "target-features");
350  std::string CPU =
351    !CPUAttr.hasAttribute(Attribute::None) ?CPUAttr.getValueAsString() : "";
352  std::string FS =
353    !FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
354  if (!FS.empty()) {
355    initializeEnvironment();
356    resetSubtargetFeatures(CPU, FS);
357  }
358}
359
360void X86Subtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
361  std::string CPUName = CPU;
362  if (!FS.empty() || !CPU.empty()) {
363    if (CPUName.empty()) {
364#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
365    || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
366      CPUName = sys::getHostCPUName();
367#else
368      CPUName = "generic";
369#endif
370    }
371
372    // Make sure 64-bit features are available in 64-bit mode. (But make sure
373    // SSE2 can be turned off explicitly.)
374    std::string FullFS = FS;
375    if (In64BitMode) {
376      if (!FullFS.empty())
377        FullFS = "+64bit,+sse2," + FullFS;
378      else
379        FullFS = "+64bit,+sse2";
380    }
381
382    // If feature string is not empty, parse features string.
383    ParseSubtargetFeatures(CPUName, FullFS);
384  } else {
385    if (CPUName.empty()) {
386#if defined (__x86_64__) || defined(__i386__)
387      CPUName = sys::getHostCPUName();
388#else
389      CPUName = "generic";
390#endif
391    }
392    // Otherwise, use CPUID to auto-detect feature set.
393    AutoDetectSubtargetFeatures();
394
395    // Make sure 64-bit features are available in 64-bit mode.
396    if (In64BitMode) {
397      HasX86_64 = true; ToggleFeature(X86::Feature64Bit);
398      HasCMov = true;   ToggleFeature(X86::FeatureCMOV);
399
400      if (X86SSELevel < SSE2) {
401        X86SSELevel = SSE2;
402        ToggleFeature(X86::FeatureSSE1);
403        ToggleFeature(X86::FeatureSSE2);
404      }
405    }
406  }
407
408  // CPUName may have been set by the CPU detection code. Make sure the
409  // new MCSchedModel is used.
410  InitMCProcessorInfo(CPUName, FS);
411
412  if (X86ProcFamily == IntelAtom)
413    PostRAScheduler = true;
414
415  InstrItins = getInstrItineraryForCPU(CPUName);
416
417  // It's important to keep the MCSubtargetInfo feature bits in sync with
418  // target data structure which is shared with MC code emitter, etc.
419  if (In64BitMode)
420    ToggleFeature(X86::Mode64Bit);
421
422  DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
423               << ", 3DNowLevel " << X863DNowLevel
424               << ", 64bit " << HasX86_64 << "\n");
425  assert((!In64BitMode || HasX86_64) &&
426         "64-bit code requested on a subtarget that doesn't support it!");
427
428  // Stack alignment is 16 bytes on Darwin, Linux and Solaris (both
429  // 32 and 64 bit) and for all 64-bit targets.
430  if (StackAlignOverride)
431    stackAlignment = StackAlignOverride;
432  else if (isTargetDarwin() || isTargetLinux() || isTargetSolaris() ||
433           In64BitMode)
434    stackAlignment = 16;
435}
436
437void X86Subtarget::initializeEnvironment() {
438  X86SSELevel = NoMMXSSE;
439  X863DNowLevel = NoThreeDNow;
440  HasCMov = false;
441  HasX86_64 = false;
442  HasPOPCNT = false;
443  HasSSE4A = false;
444  HasAES = false;
445  HasPCLMUL = false;
446  HasFMA = false;
447  HasFMA4 = false;
448  HasXOP = false;
449  HasMOVBE = false;
450  HasRDRAND = false;
451  HasF16C = false;
452  HasFSGSBase = false;
453  HasLZCNT = false;
454  HasBMI = false;
455  HasBMI2 = false;
456  HasRTM = false;
457  HasHLE = false;
458  HasADX = false;
459  HasPRFCHW = false;
460  HasRDSEED = false;
461  IsBTMemSlow = false;
462  IsUAMemFast = false;
463  HasVectorUAMem = false;
464  HasCmpxchg16b = false;
465  UseLeaForSP = false;
466  HasSlowDivide = false;
467  PostRAScheduler = false;
468  PadShortFunctions = false;
469  CallRegIndirect = false;
470  stackAlignment = 4;
471  // FIXME: this is a known good value for Yonah. How about others?
472  MaxInlineSizeThreshold = 128;
473}
474
475X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
476                           const std::string &FS,
477                           unsigned StackAlignOverride, bool is64Bit)
478  : X86GenSubtargetInfo(TT, CPU, FS)
479  , X86ProcFamily(Others)
480  , PICStyle(PICStyles::None)
481  , TargetTriple(TT)
482  , StackAlignOverride(StackAlignOverride)
483  , In64BitMode(is64Bit) {
484  initializeEnvironment();
485  resetSubtargetFeatures(CPU, FS);
486}
487
488bool X86Subtarget::enablePostRAScheduler(
489           CodeGenOpt::Level OptLevel,
490           TargetSubtargetInfo::AntiDepBreakMode& Mode,
491           RegClassVector& CriticalPathRCs) const {
492  Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
493  CriticalPathRCs.clear();
494  return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
495}
496