X86Subtarget.cpp revision 243830 
1//===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the X86 specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "subtarget"
15#include "X86Subtarget.h"
16#include "X86InstrInfo.h"
17#include "llvm/GlobalValue.h"
18#include "llvm/Support/Debug.h"
19#include "llvm/Support/ErrorHandling.h"
20#include "llvm/Support/raw_ostream.h"
21#include "llvm/Support/Host.h"
22#include "llvm/Target/TargetMachine.h"
23#include "llvm/Target/TargetOptions.h"
24
25#define GET_SUBTARGETINFO_TARGET_DESC
26#define GET_SUBTARGETINFO_CTOR
27#include "X86GenSubtargetInfo.inc"
28
29using namespace llvm;
30
31#if defined(_MSC_VER)
32#include <intrin.h>
33#endif
34
35/// ClassifyBlockAddressReference - Classify a blockaddress reference for the
36/// current subtarget according to how we should reference it in a non-pcrel
37/// context.
38unsigned char X86Subtarget::
39ClassifyBlockAddressReference() const {
40  if (isPICStyleGOT())    // 32-bit ELF targets.
41    return X86II::MO_GOTOFF;
42
43  if (isPICStyleStubPIC())   // Darwin/32 in PIC mode.
44    return X86II::MO_PIC_BASE_OFFSET;
45
46  // Direct static reference to label.
47  return X86II::MO_NO_FLAG;
48}
49
50/// ClassifyGlobalReference - Classify a global variable reference for the
51/// current subtarget according to how we should reference it in a non-pcrel
52/// context.
53unsigned char X86Subtarget::
54ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const {
55  // DLLImport only exists on windows, it is implemented as a load from a
56  // DLLIMPORT stub.
57  if (GV->hasDLLImportLinkage())
58    return X86II::MO_DLLIMPORT;
59
60  // Determine whether this is a reference to a definition or a declaration.
61  // Materializable GVs (in JIT lazy compilation mode) do not require an extra
62  // load from stub.
63  bool isDecl = GV->hasAvailableExternallyLinkage();
64  if (GV->isDeclaration() && !GV->isMaterializable())
65    isDecl = true;
66
67  // X86-64 in PIC mode.
68  if (isPICStyleRIPRel()) {
69    // Large model never uses stubs.
70    if (TM.getCodeModel() == CodeModel::Large)
71      return X86II::MO_NO_FLAG;
72
73    if (isTargetDarwin()) {
74      // If symbol visibility is hidden, the extra load is not needed if
75      // target is x86-64 or the symbol is definitely defined in the current
76      // translation unit.
77      if (GV->hasDefaultVisibility() &&
78          (isDecl || GV->isWeakForLinker()))
79        return X86II::MO_GOTPCREL;
80    } else if (!isTargetWin64()) {
81      assert(isTargetELF() && "Unknown rip-relative target");
82
83      // Extra load is needed for all externally visible.
84      if (!GV->hasLocalLinkage() && GV->hasDefaultVisibility())
85        return X86II::MO_GOTPCREL;
86    }
87
88    return X86II::MO_NO_FLAG;
89  }
90
91  if (isPICStyleGOT()) {   // 32-bit ELF targets.
92    // Extra load is needed for all externally visible.
93    if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
94      return X86II::MO_GOTOFF;
95    return X86II::MO_GOT;
96  }
97
98  if (isPICStyleStubPIC()) {  // Darwin/32 in PIC mode.
99    // Determine whether we have a stub reference and/or whether the reference
100    // is relative to the PIC base or not.
101
102    // If this is a strong reference to a definition, it is definitely not
103    // through a stub.
104    if (!isDecl && !GV->isWeakForLinker())
105      return X86II::MO_PIC_BASE_OFFSET;
106
107    // Unless we have a symbol with hidden visibility, we have to go through a
108    // normal $non_lazy_ptr stub because this symbol might be resolved late.
109    if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
110      return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
111
112    // If symbol visibility is hidden, we have a stub for common symbol
113    // references and external declarations.
114    if (isDecl || GV->hasCommonLinkage()) {
115      // Hidden $non_lazy_ptr reference.
116      return X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE;
117    }
118
119    // Otherwise, no stub.
120    return X86II::MO_PIC_BASE_OFFSET;
121  }
122
123  if (isPICStyleStubNoDynamic()) {  // Darwin/32 in -mdynamic-no-pic mode.
124    // Determine whether we have a stub reference.
125
126    // If this is a strong reference to a definition, it is definitely not
127    // through a stub.
128    if (!isDecl && !GV->isWeakForLinker())
129      return X86II::MO_NO_FLAG;
130
131    // Unless we have a symbol with hidden visibility, we have to go through a
132    // normal $non_lazy_ptr stub because this symbol might be resolved late.
133    if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
134      return X86II::MO_DARWIN_NONLAZY;
135
136    // Otherwise, no stub.
137    return X86II::MO_NO_FLAG;
138  }
139
140  // Direct static reference to global.
141  return X86II::MO_NO_FLAG;
142}
143
144
145/// getBZeroEntry - This function returns the name of a function which has an
146/// interface like the non-standard bzero function, if such a function exists on
147/// the current subtarget and it is considered prefereable over memset with zero
148/// passed as the second argument. Otherwise it returns null.
149const char *X86Subtarget::getBZeroEntry() const {
150  // Darwin 10 has a __bzero entry point for this purpose.
151  if (getTargetTriple().isMacOSX() &&
152      !getTargetTriple().isMacOSXVersionLT(10, 6))
153    return "__bzero";
154
155  return 0;
156}
157
158/// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
159/// to immediate address.
160bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
161  if (In64BitMode)
162    return false;
163  return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
164}
165
166void X86Subtarget::AutoDetectSubtargetFeatures() {
167  unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
168  unsigned MaxLevel;
169  union {
170    unsigned u[3];
171    char     c[12];
172  } text;
173
174  if (X86_MC::GetCpuIDAndInfo(0, &MaxLevel, text.u+0, text.u+2, text.u+1) ||
175      MaxLevel < 1)
176    return;
177
178  X86_MC::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
179
180  if ((EDX >> 15) & 1) { HasCMov = true;      ToggleFeature(X86::FeatureCMOV); }
181  if ((EDX >> 23) & 1) { X86SSELevel = MMX;   ToggleFeature(X86::FeatureMMX);  }
182  if ((EDX >> 25) & 1) { X86SSELevel = SSE1;  ToggleFeature(X86::FeatureSSE1); }
183  if ((EDX >> 26) & 1) { X86SSELevel = SSE2;  ToggleFeature(X86::FeatureSSE2); }
184  if (ECX & 0x1)       { X86SSELevel = SSE3;  ToggleFeature(X86::FeatureSSE3); }
185  if ((ECX >> 9)  & 1) { X86SSELevel = SSSE3; ToggleFeature(X86::FeatureSSSE3);}
186  if ((ECX >> 19) & 1) { X86SSELevel = SSE41; ToggleFeature(X86::FeatureSSE41);}
187  if ((ECX >> 20) & 1) { X86SSELevel = SSE42; ToggleFeature(X86::FeatureSSE42);}
188  if ((ECX >> 28) & 1) { X86SSELevel = AVX;   ToggleFeature(X86::FeatureAVX); }
189
190  bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
191  bool IsAMD   = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
192
193  if ((ECX >> 1) & 0x1) {
194    HasPCLMUL = true;
195    ToggleFeature(X86::FeaturePCLMUL);
196  }
197  if ((ECX >> 12) & 0x1) {
198    HasFMA = true;
199    ToggleFeature(X86::FeatureFMA);
200  }
201  if (IsIntel && ((ECX >> 22) & 0x1)) {
202    HasMOVBE = true;
203    ToggleFeature(X86::FeatureMOVBE);
204  }
205  if ((ECX >> 23) & 0x1) {
206    HasPOPCNT = true;
207    ToggleFeature(X86::FeaturePOPCNT);
208  }
209  if ((ECX >> 25) & 0x1) {
210    HasAES = true;
211    ToggleFeature(X86::FeatureAES);
212  }
213  if ((ECX >> 29) & 0x1) {
214    HasF16C = true;
215    ToggleFeature(X86::FeatureF16C);
216  }
217  if (IsIntel && ((ECX >> 30) & 0x1)) {
218    HasRDRAND = true;
219    ToggleFeature(X86::FeatureRDRAND);
220  }
221
222  if ((ECX >> 13) & 0x1) {
223    HasCmpxchg16b = true;
224    ToggleFeature(X86::FeatureCMPXCHG16B);
225  }
226
227  if (IsIntel || IsAMD) {
228    // Determine if bit test memory instructions are slow.
229    unsigned Family = 0;
230    unsigned Model  = 0;
231    X86_MC::DetectFamilyModel(EAX, Family, Model);
232    if (IsAMD || (Family == 6 && Model >= 13)) {
233      IsBTMemSlow = true;
234      ToggleFeature(X86::FeatureSlowBTMem);
235    }
236
237    // If it's Nehalem, unaligned memory access is fast.
238    // Include Westmere and Sandy Bridge as well.
239    // FIXME: add later processors.
240    if (IsIntel && ((Family == 6 && Model == 26) ||
241        (Family == 6 && Model == 44) ||
242        (Family == 6 && Model == 42))) {
243      IsUAMemFast = true;
244      ToggleFeature(X86::FeatureFastUAMem);
245    }
246
247    // Set processor type. Currently only Atom is detected.
248    if (Family == 6 &&
249        (Model == 28 || Model == 38 || Model == 39
250         || Model == 53 || Model == 54)) {
251      X86ProcFamily = IntelAtom;
252
253      UseLeaForSP = true;
254      ToggleFeature(X86::FeatureLeaForSP);
255    }
256
257    unsigned MaxExtLevel;
258    X86_MC::GetCpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
259
260    if (MaxExtLevel >= 0x80000001) {
261      X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
262      if ((EDX >> 29) & 0x1) {
263        HasX86_64 = true;
264        ToggleFeature(X86::Feature64Bit);
265      }
266      if ((ECX >> 5) & 0x1) {
267        HasLZCNT = true;
268        ToggleFeature(X86::FeatureLZCNT);
269      }
270      if (IsAMD) {
271        if ((ECX >> 6) & 0x1) {
272          HasSSE4A = true;
273          ToggleFeature(X86::FeatureSSE4A);
274        }
275        if ((ECX >> 11) & 0x1) {
276          HasXOP = true;
277          ToggleFeature(X86::FeatureXOP);
278        }
279        if ((ECX >> 16) & 0x1) {
280          HasFMA4 = true;
281          ToggleFeature(X86::FeatureFMA4);
282        }
283      }
284    }
285  }
286
287  if (MaxLevel >= 7) {
288    if (!X86_MC::GetCpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX)) {
289      if (IsIntel && (EBX & 0x1)) {
290        HasFSGSBase = true;
291        ToggleFeature(X86::FeatureFSGSBase);
292      }
293      if ((EBX >> 3) & 0x1) {
294        HasBMI = true;
295        ToggleFeature(X86::FeatureBMI);
296      }
297      if (IsIntel && ((EBX >> 5) & 0x1)) {
298        X86SSELevel = AVX2;
299        ToggleFeature(X86::FeatureAVX2);
300      }
301      if (IsIntel && ((EBX >> 8) & 0x1)) {
302        HasBMI2 = true;
303        ToggleFeature(X86::FeatureBMI2);
304      }
305      if (IsIntel && ((EBX >> 11) & 0x1)) {
306        HasRTM = true;
307        ToggleFeature(X86::FeatureRTM);
308      }
309    }
310  }
311}
312
313X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
314                           const std::string &FS,
315                           unsigned StackAlignOverride, bool is64Bit)
316  : X86GenSubtargetInfo(TT, CPU, FS)
317  , X86ProcFamily(Others)
318  , PICStyle(PICStyles::None)
319  , X86SSELevel(NoMMXSSE)
320  , X863DNowLevel(NoThreeDNow)
321  , HasCMov(false)
322  , HasX86_64(false)
323  , HasPOPCNT(false)
324  , HasSSE4A(false)
325  , HasAES(false)
326  , HasPCLMUL(false)
327  , HasFMA(false)
328  , HasFMA4(false)
329  , HasXOP(false)
330  , HasMOVBE(false)
331  , HasRDRAND(false)
332  , HasF16C(false)
333  , HasFSGSBase(false)
334  , HasLZCNT(false)
335  , HasBMI(false)
336  , HasBMI2(false)
337  , HasRTM(false)
338  , IsBTMemSlow(false)
339  , IsUAMemFast(false)
340  , HasVectorUAMem(false)
341  , HasCmpxchg16b(false)
342  , UseLeaForSP(false)
343  , HasSlowDivide(false)
344  , PostRAScheduler(false)
345  , stackAlignment(4)
346  // FIXME: this is a known good value for Yonah. How about others?
347  , MaxInlineSizeThreshold(128)
348  , TargetTriple(TT)
349  , In64BitMode(is64Bit) {
350  // Determine default and user specified characteristics
351  std::string CPUName = CPU;
352  if (!FS.empty() || !CPU.empty()) {
353    if (CPUName.empty()) {
354#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
355    || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
356      CPUName = sys::getHostCPUName();
357#else
358      CPUName = "generic";
359#endif
360    }
361
362    // Make sure 64-bit features are available in 64-bit mode. (But make sure
363    // SSE2 can be turned off explicitly.)
364    std::string FullFS = FS;
365    if (In64BitMode) {
366      if (!FullFS.empty())
367        FullFS = "+64bit,+sse2," + FullFS;
368      else
369        FullFS = "+64bit,+sse2";
370    }
371
372    // If feature string is not empty, parse features string.
373    ParseSubtargetFeatures(CPUName, FullFS);
374  } else {
375    if (CPUName.empty()) {
376#if defined (__x86_64__) || defined(__i386__)
377      CPUName = sys::getHostCPUName();
378#else
379      CPUName = "generic";
380#endif
381    }
382    // Otherwise, use CPUID to auto-detect feature set.
383    AutoDetectSubtargetFeatures();
384
385    // Make sure 64-bit features are available in 64-bit mode.
386    if (In64BitMode) {
387      HasX86_64 = true; ToggleFeature(X86::Feature64Bit);
388      HasCMov = true;   ToggleFeature(X86::FeatureCMOV);
389
390      if (X86SSELevel < SSE2) {
391        X86SSELevel = SSE2;
392        ToggleFeature(X86::FeatureSSE1);
393        ToggleFeature(X86::FeatureSSE2);
394      }
395    }
396  }
397
398  // CPUName may have been set by the CPU detection code. Make sure the
399  // new MCSchedModel is used.
400  InitMCProcessorInfo(CPUName, FS);
401
402  if (X86ProcFamily == IntelAtom)
403    PostRAScheduler = true;
404
405  InstrItins = getInstrItineraryForCPU(CPUName);
406
407  // It's important to keep the MCSubtargetInfo feature bits in sync with
408  // target data structure which is shared with MC code emitter, etc.
409  if (In64BitMode)
410    ToggleFeature(X86::Mode64Bit);
411
412  DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
413               << ", 3DNowLevel " << X863DNowLevel
414               << ", 64bit " << HasX86_64 << "\n");
415  assert((!In64BitMode || HasX86_64) &&
416         "64-bit code requested on a subtarget that doesn't support it!");
417
418  // Stack alignment is 16 bytes on Darwin, Linux and Solaris (both
419  // 32 and 64 bit) and for all 64-bit targets.
420  if (StackAlignOverride)
421    stackAlignment = StackAlignOverride;
422  else if (isTargetDarwin() || isTargetLinux() || isTargetSolaris() ||
423           In64BitMode)
424    stackAlignment = 16;
425}
426
427bool X86Subtarget::enablePostRAScheduler(
428           CodeGenOpt::Level OptLevel,
429           TargetSubtargetInfo::AntiDepBreakMode& Mode,
430           RegClassVector& CriticalPathRCs) const {
431  Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
432  CriticalPathRCs.clear();
433  return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
434}
435