X86Subtarget.cpp revision 221345 
1//===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the X86 specific subclass of TargetSubtarget.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "subtarget"
15#include "X86Subtarget.h"
16#include "X86InstrInfo.h"
17#include "X86GenSubtarget.inc"
18#include "llvm/GlobalValue.h"
19#include "llvm/Support/Debug.h"
20#include "llvm/Support/raw_ostream.h"
21#include "llvm/Support/Host.h"
22#include "llvm/Target/TargetMachine.h"
23#include "llvm/Target/TargetOptions.h"
24#include "llvm/ADT/SmallVector.h"
25using namespace llvm;
26
27#if defined(_MSC_VER)
28#include <intrin.h>
29#endif
30
31/// ClassifyBlockAddressReference - Classify a blockaddress reference for the
32/// current subtarget according to how we should reference it in a non-pcrel
33/// context.
34unsigned char X86Subtarget::
35ClassifyBlockAddressReference() const {
36  if (isPICStyleGOT())    // 32-bit ELF targets.
37    return X86II::MO_GOTOFF;
38
39  if (isPICStyleStubPIC())   // Darwin/32 in PIC mode.
40    return X86II::MO_PIC_BASE_OFFSET;
41
42  // Direct static reference to label.
43  return X86II::MO_NO_FLAG;
44}
45
46/// ClassifyGlobalReference - Classify a global variable reference for the
47/// current subtarget according to how we should reference it in a non-pcrel
48/// context.
49unsigned char X86Subtarget::
50ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const {
51  // DLLImport only exists on windows, it is implemented as a load from a
52  // DLLIMPORT stub.
53  if (GV->hasDLLImportLinkage())
54    return X86II::MO_DLLIMPORT;
55
56  // Determine whether this is a reference to a definition or a declaration.
57  // Materializable GVs (in JIT lazy compilation mode) do not require an extra
58  // load from stub.
59  bool isDecl = GV->hasAvailableExternallyLinkage();
60  if (GV->isDeclaration() && !GV->isMaterializable())
61    isDecl = true;
62
63  // X86-64 in PIC mode.
64  if (isPICStyleRIPRel()) {
65    // Large model never uses stubs.
66    if (TM.getCodeModel() == CodeModel::Large)
67      return X86II::MO_NO_FLAG;
68
69    if (isTargetDarwin()) {
70      // If symbol visibility is hidden, the extra load is not needed if
71      // target is x86-64 or the symbol is definitely defined in the current
72      // translation unit.
73      if (GV->hasDefaultVisibility() &&
74          (isDecl || GV->isWeakForLinker()))
75        return X86II::MO_GOTPCREL;
76    } else if (!isTargetWin64()) {
77      assert(isTargetELF() && "Unknown rip-relative target");
78
79      // Extra load is needed for all externally visible.
80      if (!GV->hasLocalLinkage() && GV->hasDefaultVisibility())
81        return X86II::MO_GOTPCREL;
82    }
83
84    return X86II::MO_NO_FLAG;
85  }
86
87  if (isPICStyleGOT()) {   // 32-bit ELF targets.
88    // Extra load is needed for all externally visible.
89    if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
90      return X86II::MO_GOTOFF;
91    return X86II::MO_GOT;
92  }
93
94  if (isPICStyleStubPIC()) {  // Darwin/32 in PIC mode.
95    // Determine whether we have a stub reference and/or whether the reference
96    // is relative to the PIC base or not.
97
98    // If this is a strong reference to a definition, it is definitely not
99    // through a stub.
100    if (!isDecl && !GV->isWeakForLinker())
101      return X86II::MO_PIC_BASE_OFFSET;
102
103    // Unless we have a symbol with hidden visibility, we have to go through a
104    // normal $non_lazy_ptr stub because this symbol might be resolved late.
105    if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
106      return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
107
108    // If symbol visibility is hidden, we have a stub for common symbol
109    // references and external declarations.
110    if (isDecl || GV->hasCommonLinkage()) {
111      // Hidden $non_lazy_ptr reference.
112      return X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE;
113    }
114
115    // Otherwise, no stub.
116    return X86II::MO_PIC_BASE_OFFSET;
117  }
118
119  if (isPICStyleStubNoDynamic()) {  // Darwin/32 in -mdynamic-no-pic mode.
120    // Determine whether we have a stub reference.
121
122    // If this is a strong reference to a definition, it is definitely not
123    // through a stub.
124    if (!isDecl && !GV->isWeakForLinker())
125      return X86II::MO_NO_FLAG;
126
127    // Unless we have a symbol with hidden visibility, we have to go through a
128    // normal $non_lazy_ptr stub because this symbol might be resolved late.
129    if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
130      return X86II::MO_DARWIN_NONLAZY;
131
132    // Otherwise, no stub.
133    return X86II::MO_NO_FLAG;
134  }
135
136  // Direct static reference to global.
137  return X86II::MO_NO_FLAG;
138}
139
140
141/// getBZeroEntry - This function returns the name of a function which has an
142/// interface like the non-standard bzero function, if such a function exists on
143/// the current subtarget and it is considered prefereable over memset with zero
144/// passed as the second argument. Otherwise it returns null.
145const char *X86Subtarget::getBZeroEntry() const {
146  // Darwin 10 has a __bzero entry point for this purpose.
147  if (getTargetTriple().isMacOSX() &&
148      !getTargetTriple().isMacOSXVersionLT(10, 6))
149    return "__bzero";
150
151  return 0;
152}
153
154/// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
155/// to immediate address.
156bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
157  if (Is64Bit)
158    return false;
159  return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
160}
161
162/// getSpecialAddressLatency - For targets where it is beneficial to
163/// backschedule instructions that compute addresses, return a value
164/// indicating the number of scheduling cycles of backscheduling that
165/// should be attempted.
166unsigned X86Subtarget::getSpecialAddressLatency() const {
167  // For x86 out-of-order targets, back-schedule address computations so
168  // that loads and stores aren't blocked.
169  // This value was chosen arbitrarily.
170  return 200;
171}
172
173/// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
174/// specified arguments.  If we can't run cpuid on the host, return true.
175static bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
176                            unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
177#if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
178  #if defined(__GNUC__)
179    // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
180    asm ("movq\t%%rbx, %%rsi\n\t"
181         "cpuid\n\t"
182         "xchgq\t%%rbx, %%rsi\n\t"
183         : "=a" (*rEAX),
184           "=S" (*rEBX),
185           "=c" (*rECX),
186           "=d" (*rEDX)
187         :  "a" (value));
188    return false;
189  #elif defined(_MSC_VER)
190    int registers[4];
191    __cpuid(registers, value);
192    *rEAX = registers[0];
193    *rEBX = registers[1];
194    *rECX = registers[2];
195    *rEDX = registers[3];
196    return false;
197  #endif
198#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
199  #if defined(__GNUC__)
200    asm ("movl\t%%ebx, %%esi\n\t"
201         "cpuid\n\t"
202         "xchgl\t%%ebx, %%esi\n\t"
203         : "=a" (*rEAX),
204           "=S" (*rEBX),
205           "=c" (*rECX),
206           "=d" (*rEDX)
207         :  "a" (value));
208    return false;
209  #elif defined(_MSC_VER)
210    __asm {
211      mov   eax,value
212      cpuid
213      mov   esi,rEAX
214      mov   dword ptr [esi],eax
215      mov   esi,rEBX
216      mov   dword ptr [esi],ebx
217      mov   esi,rECX
218      mov   dword ptr [esi],ecx
219      mov   esi,rEDX
220      mov   dword ptr [esi],edx
221    }
222    return false;
223  #endif
224#endif
225  return true;
226}
227
228static void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model) {
229  Family = (EAX >> 8) & 0xf; // Bits 8 - 11
230  Model  = (EAX >> 4) & 0xf; // Bits 4 - 7
231  if (Family == 6 || Family == 0xf) {
232    if (Family == 0xf)
233      // Examine extended family ID if family ID is F.
234      Family += (EAX >> 20) & 0xff;    // Bits 20 - 27
235    // Examine extended model ID if family ID is 6 or F.
236    Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
237  }
238}
239
240void X86Subtarget::AutoDetectSubtargetFeatures() {
241  unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
242  union {
243    unsigned u[3];
244    char     c[12];
245  } text;
246
247  if (GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1))
248    return;
249
250  GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
251
252  if ((EDX >> 15) & 1) HasCMov = true;
253  if ((EDX >> 23) & 1) X86SSELevel = MMX;
254  if ((EDX >> 25) & 1) X86SSELevel = SSE1;
255  if ((EDX >> 26) & 1) X86SSELevel = SSE2;
256  if (ECX & 0x1)       X86SSELevel = SSE3;
257  if ((ECX >> 9)  & 1) X86SSELevel = SSSE3;
258  if ((ECX >> 19) & 1) X86SSELevel = SSE41;
259  if ((ECX >> 20) & 1) X86SSELevel = SSE42;
260  // FIXME: AVX codegen support is not ready.
261  //if ((ECX >> 28) & 1) { HasAVX = true; X86SSELevel = NoMMXSSE; }
262
263  bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
264  bool IsAMD   = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
265
266  HasCLMUL = IsIntel && ((ECX >> 1) & 0x1);
267  HasFMA3  = IsIntel && ((ECX >> 12) & 0x1);
268  HasAES   = IsIntel && ((ECX >> 25) & 0x1);
269
270  if (IsIntel || IsAMD) {
271    // Determine if bit test memory instructions are slow.
272    unsigned Family = 0;
273    unsigned Model  = 0;
274    DetectFamilyModel(EAX, Family, Model);
275    IsBTMemSlow = IsAMD || (Family == 6 && Model >= 13);
276    // If it's Nehalem, unaligned memory access is fast.
277    if (Family == 15 && Model == 26)
278      IsUAMemFast = true;
279
280    GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
281    HasX86_64 = (EDX >> 29) & 0x1;
282    HasSSE4A = IsAMD && ((ECX >> 6) & 0x1);
283    HasFMA4 = IsAMD && ((ECX >> 16) & 0x1);
284  }
285}
286
287X86Subtarget::X86Subtarget(const std::string &TT, const std::string &FS,
288                           bool is64Bit)
289  : PICStyle(PICStyles::None)
290  , X86SSELevel(NoMMXSSE)
291  , X863DNowLevel(NoThreeDNow)
292  , HasCMov(false)
293  , HasX86_64(false)
294  , HasPOPCNT(false)
295  , HasSSE4A(false)
296  , HasAVX(false)
297  , HasAES(false)
298  , HasCLMUL(false)
299  , HasFMA3(false)
300  , HasFMA4(false)
301  , IsBTMemSlow(false)
302  , IsUAMemFast(false)
303  , HasVectorUAMem(false)
304  , stackAlignment(8)
305  // FIXME: this is a known good value for Yonah. How about others?
306  , MaxInlineSizeThreshold(128)
307  , TargetTriple(TT)
308  , Is64Bit(is64Bit) {
309
310  // default to hard float ABI
311  if (FloatABIType == FloatABI::Default)
312    FloatABIType = FloatABI::Hard;
313
314  // Determine default and user specified characteristics
315  if (!FS.empty()) {
316    // If feature string is not empty, parse features string.
317    std::string CPU = sys::getHostCPUName();
318    ParseSubtargetFeatures(FS, CPU);
319    // All X86-64 CPUs also have SSE2, however user might request no SSE via
320    // -mattr, so don't force SSELevel here.
321    if (HasAVX)
322      X86SSELevel = NoMMXSSE;
323  } else {
324    // Otherwise, use CPUID to auto-detect feature set.
325    AutoDetectSubtargetFeatures();
326    // Make sure SSE2 is enabled; it is available on all X86-64 CPUs.
327    if (Is64Bit && !HasAVX && X86SSELevel < SSE2)
328      X86SSELevel = SSE2;
329  }
330
331  // If requesting codegen for X86-64, make sure that 64-bit features
332  // are enabled.
333  if (Is64Bit) {
334    HasX86_64 = true;
335
336    // All 64-bit cpus have cmov support.
337    HasCMov = true;
338  }
339
340  DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
341               << ", 3DNowLevel " << X863DNowLevel
342               << ", 64bit " << HasX86_64 << "\n");
343  assert((!Is64Bit || HasX86_64) &&
344         "64-bit code requested on a subtarget that doesn't support it!");
345
346  // Stack alignment is 16 bytes on Darwin, FreeBSD, Linux and Solaris (both
347  // 32 and 64 bit) and for all 64-bit targets.
348  if (isTargetDarwin() || isTargetFreeBSD() || isTargetLinux() ||
349      isTargetSolaris() || Is64Bit)
350    stackAlignment = 16;
351
352  if (StackAlignment)
353    stackAlignment = StackAlignment;
354}
355
356/// IsCalleePop - Determines whether the callee is required to pop its
357/// own arguments. Callee pop is necessary to support tail calls.
358bool X86Subtarget::IsCalleePop(bool IsVarArg,
359                               CallingConv::ID CallingConv) const {
360  if (IsVarArg)
361    return false;
362
363  switch (CallingConv) {
364  default:
365    return false;
366  case CallingConv::X86_StdCall:
367    return !is64Bit();
368  case CallingConv::X86_FastCall:
369    return !is64Bit();
370  case CallingConv::X86_ThisCall:
371    return !is64Bit();
372  case CallingConv::Fast:
373    return GuaranteedTailCallOpt;
374  case CallingConv::GHC:
375    return GuaranteedTailCallOpt;
376  }
377}
378