X86InstrCompiler.td revision 247205
1//===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the various pseudo instructions used by the compiler, 11// as well as Pat patterns used during instruction selection. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// Pattern Matching Support 17 18def GetLo32XForm : SDNodeXForm<imm, [{ 19 // Transformation function: get the low 32 bits. 20 return getI32Imm((unsigned)N->getZExtValue()); 21}]>; 22 23def GetLo8XForm : SDNodeXForm<imm, [{ 24 // Transformation function: get the low 8 bits. 25 return getI8Imm((uint8_t)N->getZExtValue()); 26}]>; 27 28 29//===----------------------------------------------------------------------===// 30// Random Pseudo Instructions. 31 32// PIC base construction. This expands to code that looks like this: 33// call $next_inst 34// popl %destreg" 35let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in 36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label), 37 "", []>; 38 39 40// ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into 41// a stack adjustment and the codegen must know that they may modify the stack 42// pointer before prolog-epilog rewriting occurs. 43// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 44// sub / add which can clobber EFLAGS. 45let Defs = [ESP, EFLAGS], Uses = [ESP] in { 46def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt), 47 "#ADJCALLSTACKDOWN", 48 [(X86callseq_start timm:$amt)]>, 49 Requires<[In32BitMode]>; 50def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 51 "#ADJCALLSTACKUP", 52 [(X86callseq_end timm:$amt1, timm:$amt2)]>, 53 Requires<[In32BitMode]>; 54} 55 56// ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into 57// a stack adjustment and the codegen must know that they may modify the stack 58// pointer before prolog-epilog rewriting occurs. 59// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 60// sub / add which can clobber EFLAGS. 61let Defs = [RSP, EFLAGS], Uses = [RSP] in { 62def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt), 63 "#ADJCALLSTACKDOWN", 64 [(X86callseq_start timm:$amt)]>, 65 Requires<[In64BitMode]>; 66def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 67 "#ADJCALLSTACKUP", 68 [(X86callseq_end timm:$amt1, timm:$amt2)]>, 69 Requires<[In64BitMode]>; 70} 71 72 73 74// x86-64 va_start lowering magic. 75let usesCustomInserter = 1 in { 76def VASTART_SAVE_XMM_REGS : I<0, Pseudo, 77 (outs), 78 (ins GR8:$al, 79 i64imm:$regsavefi, i64imm:$offset, 80 variable_ops), 81 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset", 82 [(X86vastart_save_xmm_regs GR8:$al, 83 imm:$regsavefi, 84 imm:$offset)]>; 85 86// The VAARG_64 pseudo-instruction takes the address of the va_list, 87// and places the address of the next argument into a register. 88let Defs = [EFLAGS] in 89def VAARG_64 : I<0, Pseudo, 90 (outs GR64:$dst), 91 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align), 92 "#VAARG_64 $dst, $ap, $size, $mode, $align", 93 [(set GR64:$dst, 94 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)), 95 (implicit EFLAGS)]>; 96 97// Dynamic stack allocation yields a _chkstk or _alloca call for all Windows 98// targets. These calls are needed to probe the stack when allocating more than 99// 4k bytes in one go. Touching the stack at 4K increments is necessary to 100// ensure that the guard pages used by the OS virtual memory manager are 101// allocated in correct sequence. 102// The main point of having separate instruction are extra unmodelled effects 103// (compared to ordinary calls) like stack pointer change. 104 105let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 106 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins), 107 "# dynamic stack allocation", 108 [(X86WinAlloca)]>; 109 110// When using segmented stacks these are lowered into instructions which first 111// check if the current stacklet has enough free memory. If it does, memory is 112// allocated by bumping the stack pointer. Otherwise memory is allocated from 113// the heap. 114 115let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 116def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size), 117 "# variable sized alloca for segmented stacks", 118 [(set GR32:$dst, 119 (X86SegAlloca GR32:$size))]>, 120 Requires<[In32BitMode]>; 121 122let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in 123def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size), 124 "# variable sized alloca for segmented stacks", 125 [(set GR64:$dst, 126 (X86SegAlloca GR64:$size))]>, 127 Requires<[In64BitMode]>; 128} 129 130// The MSVC runtime contains an _ftol2 routine for converting floating-point 131// to integer values. It has a strange calling convention: the input is 132// popped from the x87 stack, and the return value is given in EDX:EAX. No 133// other registers (aside from flags) are touched. 134// Microsoft toolchains do not support 80-bit precision, so a WIN_FTOL_80 135// variant is unnecessary. 136 137let Defs = [EAX, EDX, EFLAGS], FPForm = SpecialFP in { 138 def WIN_FTOL_32 : I<0, Pseudo, (outs), (ins RFP32:$src), 139 "# win32 fptoui", 140 [(X86WinFTOL RFP32:$src)]>, 141 Requires<[In32BitMode]>; 142 143 def WIN_FTOL_64 : I<0, Pseudo, (outs), (ins RFP64:$src), 144 "# win32 fptoui", 145 [(X86WinFTOL RFP64:$src)]>, 146 Requires<[In32BitMode]>; 147} 148 149//===----------------------------------------------------------------------===// 150// EH Pseudo Instructions 151// 152let isTerminator = 1, isReturn = 1, isBarrier = 1, 153 hasCtrlDep = 1, isCodeGenOnly = 1 in { 154def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr), 155 "ret\t#eh_return, addr: $addr", 156 [(X86ehret GR32:$addr)], IIC_RET>; 157 158} 159 160let isTerminator = 1, isReturn = 1, isBarrier = 1, 161 hasCtrlDep = 1, isCodeGenOnly = 1 in { 162def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr), 163 "ret\t#eh_return, addr: $addr", 164 [(X86ehret GR64:$addr)], IIC_RET>; 165 166} 167 168let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 169 usesCustomInserter = 1 in { 170 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf), 171 "#EH_SJLJ_SETJMP32", 172 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>, 173 Requires<[In32BitMode]>; 174 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf), 175 "#EH_SJLJ_SETJMP64", 176 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>, 177 Requires<[In64BitMode]>; 178 let isTerminator = 1 in { 179 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf), 180 "#EH_SJLJ_LONGJMP32", 181 [(X86eh_sjlj_longjmp addr:$buf)]>, 182 Requires<[In32BitMode]>; 183 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf), 184 "#EH_SJLJ_LONGJMP64", 185 [(X86eh_sjlj_longjmp addr:$buf)]>, 186 Requires<[In64BitMode]>; 187 } 188} 189 190let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in { 191 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst), 192 "#EH_SjLj_Setup\t$dst", []>; 193} 194 195//===----------------------------------------------------------------------===// 196// Pseudo instructions used by segmented stacks. 197// 198 199// This is lowered into a RET instruction by MCInstLower. We need 200// this so that we don't have to have a MachineBasicBlock which ends 201// with a RET and also has successors. 202let isPseudo = 1 in { 203def MORESTACK_RET: I<0, Pseudo, (outs), (ins), 204 "", []>; 205 206// This instruction is lowered to a RET followed by a MOV. The two 207// instructions are not generated on a higher level since then the 208// verifier sees a MachineBasicBlock ending with a non-terminator. 209def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins), 210 "", []>; 211} 212 213//===----------------------------------------------------------------------===// 214// Alias Instructions 215//===----------------------------------------------------------------------===// 216 217// Alias instructions that map movr0 to xor. 218// FIXME: remove when we can teach regalloc that xor reg, reg is ok. 219// FIXME: Set encoding to pseudo. 220let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1, 221 isCodeGenOnly = 1 in { 222def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "", 223 [(set GR8:$dst, 0)], IIC_ALU_NONMEM>; 224 225// We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller 226// encoding and avoids a partial-register update sometimes, but doing so 227// at isel time interferes with rematerialization in the current register 228// allocator. For now, this is rewritten when the instruction is lowered 229// to an MCInst. 230def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins), 231 "", 232 [(set GR16:$dst, 0)], IIC_ALU_NONMEM>, OpSize; 233 234// FIXME: Set encoding to pseudo. 235def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "", 236 [(set GR32:$dst, 0)], IIC_ALU_NONMEM>; 237} 238 239// We want to rewrite MOV64r0 in terms of MOV32r0, because it's sometimes a 240// smaller encoding, but doing so at isel time interferes with rematerialization 241// in the current register allocator. For now, this is rewritten when the 242// instruction is lowered to an MCInst. 243// FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove 244// when we have a better way to specify isel priority. 245let Defs = [EFLAGS], isCodeGenOnly=1, 246 AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in 247def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins), "", 248 [(set GR64:$dst, 0)], IIC_ALU_NONMEM>; 249 250// Materialize i64 constant where top 32-bits are zero. This could theoretically 251// use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however 252// that would make it more difficult to rematerialize. 253let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1, 254 isCodeGenOnly = 1 in 255def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src), 256 "", [(set GR64:$dst, i64immZExt32:$src)], 257 IIC_ALU_NONMEM>; 258 259// Use sbb to materialize carry bit. 260let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1 in { 261// FIXME: These are pseudo ops that should be replaced with Pat<> patterns. 262// However, Pat<> can't replicate the destination reg into the inputs of the 263// result. 264def SETB_C8r : I<0, Pseudo, (outs GR8:$dst), (ins), "", 265 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 266def SETB_C16r : I<0, Pseudo, (outs GR16:$dst), (ins), "", 267 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 268def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "", 269 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 270def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "", 271 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 272} // isCodeGenOnly 273 274 275def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 276 (SETB_C16r)>; 277def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 278 (SETB_C32r)>; 279def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 280 (SETB_C64r)>; 281 282def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 283 (SETB_C16r)>; 284def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 285 (SETB_C32r)>; 286def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 287 (SETB_C64r)>; 288 289// We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and 290// will be eliminated and that the sbb can be extended up to a wider type. When 291// this happens, it is great. However, if we are left with an 8-bit sbb and an 292// and, we might as well just match it as a setb. 293def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), 294 (SETBr)>; 295 296// (add OP, SETB) -> (adc OP, 0) 297def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op), 298 (ADC8ri GR8:$op, 0)>; 299def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op), 300 (ADC32ri8 GR32:$op, 0)>; 301def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op), 302 (ADC64ri8 GR64:$op, 0)>; 303 304// (sub OP, SETB) -> (sbb OP, 0) 305def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)), 306 (SBB8ri GR8:$op, 0)>; 307def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)), 308 (SBB32ri8 GR32:$op, 0)>; 309def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)), 310 (SBB64ri8 GR64:$op, 0)>; 311 312// (sub OP, SETCC_CARRY) -> (adc OP, 0) 313def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))), 314 (ADC8ri GR8:$op, 0)>; 315def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))), 316 (ADC32ri8 GR32:$op, 0)>; 317def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))), 318 (ADC64ri8 GR64:$op, 0)>; 319 320//===----------------------------------------------------------------------===// 321// String Pseudo Instructions 322// 323let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in { 324def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}", 325 [(X86rep_movs i8)], IIC_REP_MOVS>, REP, 326 Requires<[In32BitMode]>; 327def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}", 328 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize, 329 Requires<[In32BitMode]>; 330def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}", 331 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, 332 Requires<[In32BitMode]>; 333} 334 335let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in { 336def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}", 337 [(X86rep_movs i8)], IIC_REP_MOVS>, REP, 338 Requires<[In64BitMode]>; 339def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}", 340 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize, 341 Requires<[In64BitMode]>; 342def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}", 343 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, 344 Requires<[In64BitMode]>; 345def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}", 346 [(X86rep_movs i64)], IIC_REP_MOVS>, REP, 347 Requires<[In64BitMode]>; 348} 349 350// FIXME: Should use "(X86rep_stos AL)" as the pattern. 351let Defs = [ECX,EDI], isCodeGenOnly = 1 in { 352 let Uses = [AL,ECX,EDI] in 353 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}", 354 [(X86rep_stos i8)], IIC_REP_STOS>, REP, 355 Requires<[In32BitMode]>; 356 let Uses = [AX,ECX,EDI] in 357 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}", 358 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize, 359 Requires<[In32BitMode]>; 360 let Uses = [EAX,ECX,EDI] in 361 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}", 362 [(X86rep_stos i32)], IIC_REP_STOS>, REP, 363 Requires<[In32BitMode]>; 364} 365 366let Defs = [RCX,RDI], isCodeGenOnly = 1 in { 367 let Uses = [AL,RCX,RDI] in 368 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}", 369 [(X86rep_stos i8)], IIC_REP_STOS>, REP, 370 Requires<[In64BitMode]>; 371 let Uses = [AX,RCX,RDI] in 372 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}", 373 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize, 374 Requires<[In64BitMode]>; 375 let Uses = [RAX,RCX,RDI] in 376 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}", 377 [(X86rep_stos i32)], IIC_REP_STOS>, REP, 378 Requires<[In64BitMode]>; 379 380 let Uses = [RAX,RCX,RDI] in 381 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}", 382 [(X86rep_stos i64)], IIC_REP_STOS>, REP, 383 Requires<[In64BitMode]>; 384} 385 386//===----------------------------------------------------------------------===// 387// Thread Local Storage Instructions 388// 389 390// ELF TLS Support 391// All calls clobber the non-callee saved registers. ESP is marked as 392// a use to prevent stack-pointer assignments that appear immediately 393// before calls from potentially appearing dead. 394let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, 395 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 396 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 397 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], 398 Uses = [ESP] in { 399def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 400 "# TLS_addr32", 401 [(X86tlsaddr tls32addr:$sym)]>, 402 Requires<[In32BitMode]>; 403def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 404 "# TLS_base_addr32", 405 [(X86tlsbaseaddr tls32baseaddr:$sym)]>, 406 Requires<[In32BitMode]>; 407} 408 409// All calls clobber the non-callee saved registers. RSP is marked as 410// a use to prevent stack-pointer assignments that appear immediately 411// before calls from potentially appearing dead. 412let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, 413 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1, 414 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 415 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 416 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], 417 Uses = [RSP] in { 418def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 419 "# TLS_addr64", 420 [(X86tlsaddr tls64addr:$sym)]>, 421 Requires<[In64BitMode]>; 422def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 423 "# TLS_base_addr64", 424 [(X86tlsbaseaddr tls64baseaddr:$sym)]>, 425 Requires<[In64BitMode]>; 426} 427 428// Darwin TLS Support 429// For i386, the address of the thunk is passed on the stack, on return the 430// address of the variable is in %eax. %ecx is trashed during the function 431// call. All other registers are preserved. 432let Defs = [EAX, ECX, EFLAGS], 433 Uses = [ESP], 434 usesCustomInserter = 1 in 435def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 436 "# TLSCall_32", 437 [(X86TLSCall addr:$sym)]>, 438 Requires<[In32BitMode]>; 439 440// For x86_64, the address of the thunk is passed in %rdi, on return 441// the address of the variable is in %rax. All other registers are preserved. 442let Defs = [RAX, EFLAGS], 443 Uses = [RSP, RDI], 444 usesCustomInserter = 1 in 445def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 446 "# TLSCall_64", 447 [(X86TLSCall addr:$sym)]>, 448 Requires<[In64BitMode]>; 449 450 451//===----------------------------------------------------------------------===// 452// Conditional Move Pseudo Instructions 453 454// X86 doesn't have 8-bit conditional moves. Use a customInserter to 455// emit control flow. An alternative to this is to mark i8 SELECT as Promote, 456// however that requires promoting the operands, and can induce additional 457// i8 register pressure. 458let usesCustomInserter = 1, Uses = [EFLAGS] in { 459def CMOV_GR8 : I<0, Pseudo, 460 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond), 461 "#CMOV_GR8 PSEUDO!", 462 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2, 463 imm:$cond, EFLAGS))]>; 464 465let Predicates = [NoCMov] in { 466def CMOV_GR32 : I<0, Pseudo, 467 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond), 468 "#CMOV_GR32* PSEUDO!", 469 [(set GR32:$dst, 470 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>; 471def CMOV_GR16 : I<0, Pseudo, 472 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond), 473 "#CMOV_GR16* PSEUDO!", 474 [(set GR16:$dst, 475 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>; 476} // Predicates = [NoCMov] 477 478// fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no 479// SSE1. 480let Predicates = [FPStackf32] in 481def CMOV_RFP32 : I<0, Pseudo, 482 (outs RFP32:$dst), 483 (ins RFP32:$src1, RFP32:$src2, i8imm:$cond), 484 "#CMOV_RFP32 PSEUDO!", 485 [(set RFP32:$dst, 486 (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond, 487 EFLAGS))]>; 488// fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no 489// SSE2. 490let Predicates = [FPStackf64] in 491def CMOV_RFP64 : I<0, Pseudo, 492 (outs RFP64:$dst), 493 (ins RFP64:$src1, RFP64:$src2, i8imm:$cond), 494 "#CMOV_RFP64 PSEUDO!", 495 [(set RFP64:$dst, 496 (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond, 497 EFLAGS))]>; 498def CMOV_RFP80 : I<0, Pseudo, 499 (outs RFP80:$dst), 500 (ins RFP80:$src1, RFP80:$src2, i8imm:$cond), 501 "#CMOV_RFP80 PSEUDO!", 502 [(set RFP80:$dst, 503 (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond, 504 EFLAGS))]>; 505} // UsesCustomInserter = 1, Uses = [EFLAGS] 506 507 508//===----------------------------------------------------------------------===// 509// Atomic Instruction Pseudo Instructions 510//===----------------------------------------------------------------------===// 511 512// Pseudo atomic instructions 513 514multiclass PSEUDO_ATOMIC_LOAD_BINOP<string mnemonic> { 515 let usesCustomInserter = 1, mayLoad = 1, mayStore = 1 in { 516 def #NAME#8 : I<0, Pseudo, (outs GR8:$dst), 517 (ins i8mem:$ptr, GR8:$val), 518 !strconcat(mnemonic, "8 PSEUDO!"), []>; 519 def #NAME#16 : I<0, Pseudo,(outs GR16:$dst), 520 (ins i16mem:$ptr, GR16:$val), 521 !strconcat(mnemonic, "16 PSEUDO!"), []>; 522 def #NAME#32 : I<0, Pseudo, (outs GR32:$dst), 523 (ins i32mem:$ptr, GR32:$val), 524 !strconcat(mnemonic, "32 PSEUDO!"), []>; 525 def #NAME#64 : I<0, Pseudo, (outs GR64:$dst), 526 (ins i64mem:$ptr, GR64:$val), 527 !strconcat(mnemonic, "64 PSEUDO!"), []>; 528 } 529} 530 531multiclass PSEUDO_ATOMIC_LOAD_BINOP_PATS<string name, string frag> { 532 def : Pat<(!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val), 533 (!cast<Instruction>(name # "8") addr:$ptr, GR8:$val)>; 534 def : Pat<(!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val), 535 (!cast<Instruction>(name # "16") addr:$ptr, GR16:$val)>; 536 def : Pat<(!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val), 537 (!cast<Instruction>(name # "32") addr:$ptr, GR32:$val)>; 538 def : Pat<(!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val), 539 (!cast<Instruction>(name # "64") addr:$ptr, GR64:$val)>; 540} 541 542// Atomic exchange, and, or, xor 543defm ATOMAND : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMAND">; 544defm ATOMOR : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMOR">; 545defm ATOMXOR : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMXOR">; 546defm ATOMNAND : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMNAND">; 547defm ATOMMAX : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMMAX">; 548defm ATOMMIN : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMMIN">; 549defm ATOMUMAX : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMUMAX">; 550defm ATOMUMIN : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMUMIN">; 551 552defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMAND", "atomic_load_and">; 553defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMOR", "atomic_load_or">; 554defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMXOR", "atomic_load_xor">; 555defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMNAND", "atomic_load_nand">; 556defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMMAX", "atomic_load_max">; 557defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMMIN", "atomic_load_min">; 558defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMUMAX", "atomic_load_umax">; 559defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMUMIN", "atomic_load_umin">; 560 561multiclass PSEUDO_ATOMIC_LOAD_BINOP6432<string mnemonic> { 562 let usesCustomInserter = 1, mayLoad = 1, mayStore = 1 in 563 def #NAME#6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), 564 (ins i64mem:$ptr, GR32:$val1, GR32:$val2), 565 !strconcat(mnemonic, "6432 PSEUDO!"), []>; 566} 567 568defm ATOMAND : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMAND">; 569defm ATOMOR : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMOR">; 570defm ATOMXOR : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMXOR">; 571defm ATOMNAND : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMNAND">; 572defm ATOMADD : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMADD">; 573defm ATOMSUB : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMSUB">; 574defm ATOMMAX : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMMAX">; 575defm ATOMMIN : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMMIN">; 576defm ATOMUMAX : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMUMAX">; 577defm ATOMUMIN : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMUMIN">; 578defm ATOMSWAP : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMSWAP">; 579 580//===----------------------------------------------------------------------===// 581// Normal-Instructions-With-Lock-Prefix Pseudo Instructions 582//===----------------------------------------------------------------------===// 583 584// FIXME: Use normal instructions and add lock prefix dynamically. 585 586// Memory barriers 587 588// TODO: Get this to fold the constant into the instruction. 589let isCodeGenOnly = 1, Defs = [EFLAGS] in 590def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero), 591 "or{l}\t{$zero, $dst|$dst, $zero}", 592 [], IIC_ALU_MEM>, Requires<[In32BitMode]>, LOCK; 593 594let hasSideEffects = 1 in 595def Int_MemBarrier : I<0, Pseudo, (outs), (ins), 596 "#MEMBARRIER", 597 [(X86MemBarrier)]>; 598 599// RegOpc corresponds to the mr version of the instruction 600// ImmOpc corresponds to the mi version of the instruction 601// ImmOpc8 corresponds to the mi8 version of the instruction 602// ImmMod corresponds to the instruction format of the mi and mi8 versions 603multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8, 604 Format ImmMod, string mnemonic> { 605let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1 in { 606 607def #NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 608 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 }, 609 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), 610 !strconcat(mnemonic, "{b}\t", 611 "{$src2, $dst|$dst, $src2}"), 612 [], IIC_ALU_NONMEM>, LOCK; 613def #NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 614 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 615 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), 616 !strconcat(mnemonic, "{w}\t", 617 "{$src2, $dst|$dst, $src2}"), 618 [], IIC_ALU_NONMEM>, OpSize, LOCK; 619def #NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 620 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 621 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), 622 !strconcat(mnemonic, "{l}\t", 623 "{$src2, $dst|$dst, $src2}"), 624 [], IIC_ALU_NONMEM>, LOCK; 625def #NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 626 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 627 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), 628 !strconcat(mnemonic, "{q}\t", 629 "{$src2, $dst|$dst, $src2}"), 630 [], IIC_ALU_NONMEM>, LOCK; 631 632def #NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 633 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 }, 634 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2), 635 !strconcat(mnemonic, "{b}\t", 636 "{$src2, $dst|$dst, $src2}"), 637 [], IIC_ALU_MEM>, LOCK; 638 639def #NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 640 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 641 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2), 642 !strconcat(mnemonic, "{w}\t", 643 "{$src2, $dst|$dst, $src2}"), 644 [], IIC_ALU_MEM>, OpSize, LOCK; 645 646def #NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 647 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 648 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2), 649 !strconcat(mnemonic, "{l}\t", 650 "{$src2, $dst|$dst, $src2}"), 651 [], IIC_ALU_MEM>, LOCK; 652 653def #NAME#64mi32 : RIi32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 654 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 655 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2), 656 !strconcat(mnemonic, "{q}\t", 657 "{$src2, $dst|$dst, $src2}"), 658 [], IIC_ALU_MEM>, LOCK; 659 660def #NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 661 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 662 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2), 663 !strconcat(mnemonic, "{w}\t", 664 "{$src2, $dst|$dst, $src2}"), 665 [], IIC_ALU_MEM>, OpSize, LOCK; 666def #NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 667 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 668 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2), 669 !strconcat(mnemonic, "{l}\t", 670 "{$src2, $dst|$dst, $src2}"), 671 [], IIC_ALU_MEM>, LOCK; 672def #NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 673 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 674 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2), 675 !strconcat(mnemonic, "{q}\t", 676 "{$src2, $dst|$dst, $src2}"), 677 [], IIC_ALU_MEM>, LOCK; 678 679} 680 681} 682 683defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">; 684defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">; 685defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, "or">; 686defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">; 687defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">; 688 689// Optimized codegen when the non-memory output is not used. 690multiclass LOCK_ArithUnOp<bits<8> Opc8, bits<8> Opc, Format Form, 691 string mnemonic> { 692let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1 in { 693 694def #NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst), 695 !strconcat(mnemonic, "{b}\t$dst"), 696 [], IIC_UNARY_MEM>, LOCK; 697def #NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst), 698 !strconcat(mnemonic, "{w}\t$dst"), 699 [], IIC_UNARY_MEM>, OpSize, LOCK; 700def #NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst), 701 !strconcat(mnemonic, "{l}\t$dst"), 702 [], IIC_UNARY_MEM>, LOCK; 703def #NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst), 704 !strconcat(mnemonic, "{q}\t$dst"), 705 [], IIC_UNARY_MEM>, LOCK; 706} 707} 708 709defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, "inc">; 710defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "dec">; 711 712// Atomic compare and swap. 713multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic, 714 SDPatternOperator frag, X86MemOperand x86memop, 715 InstrItinClass itin> { 716let isCodeGenOnly = 1 in { 717 def #NAME# : I<Opc, Form, (outs), (ins x86memop:$ptr), 718 !strconcat(mnemonic, "\t$ptr"), 719 [(frag addr:$ptr)], itin>, TB, LOCK; 720} 721} 722 723multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form, 724 string mnemonic, SDPatternOperator frag, 725 InstrItinClass itin8, InstrItinClass itin> { 726let isCodeGenOnly = 1 in { 727 let Defs = [AL, EFLAGS], Uses = [AL] in 728 def #NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap), 729 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"), 730 [(frag addr:$ptr, GR8:$swap, 1)], itin8>, TB, LOCK; 731 let Defs = [AX, EFLAGS], Uses = [AX] in 732 def #NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap), 733 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"), 734 [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize, LOCK; 735 let Defs = [EAX, EFLAGS], Uses = [EAX] in 736 def #NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap), 737 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"), 738 [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, LOCK; 739 let Defs = [RAX, EFLAGS], Uses = [RAX] in 740 def #NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap), 741 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"), 742 [(frag addr:$ptr, GR64:$swap, 8)], itin>, TB, LOCK; 743} 744} 745 746let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in { 747defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b", 748 X86cas8, i64mem, 749 IIC_CMPX_LOCK_8B>; 750} 751 752let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX], 753 Predicates = [HasCmpxchg16b] in { 754defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b", 755 X86cas16, i128mem, 756 IIC_CMPX_LOCK_16B>, REX_W; 757} 758 759defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg", 760 X86cas, IIC_CMPX_LOCK_8, IIC_CMPX_LOCK>; 761 762// Atomic exchange and add 763multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic, 764 string frag, 765 InstrItinClass itin8, InstrItinClass itin> { 766 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1 in { 767 def #NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst), 768 (ins GR8:$val, i8mem:$ptr), 769 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"), 770 [(set GR8:$dst, 771 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))], 772 itin8>; 773 def #NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst), 774 (ins GR16:$val, i16mem:$ptr), 775 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"), 776 [(set 777 GR16:$dst, 778 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))], 779 itin>, OpSize; 780 def #NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst), 781 (ins GR32:$val, i32mem:$ptr), 782 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"), 783 [(set 784 GR32:$dst, 785 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))], 786 itin>; 787 def #NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst), 788 (ins GR64:$val, i64mem:$ptr), 789 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"), 790 [(set 791 GR64:$dst, 792 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))], 793 itin>; 794 } 795} 796 797defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add", 798 IIC_XADD_LOCK_MEM8, IIC_XADD_LOCK_MEM>, 799 TB, LOCK; 800 801def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src), 802 "#ACQUIRE_MOV PSEUDO!", 803 [(set GR8:$dst, (atomic_load_8 addr:$src))]>; 804def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src), 805 "#ACQUIRE_MOV PSEUDO!", 806 [(set GR16:$dst, (atomic_load_16 addr:$src))]>; 807def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src), 808 "#ACQUIRE_MOV PSEUDO!", 809 [(set GR32:$dst, (atomic_load_32 addr:$src))]>; 810def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src), 811 "#ACQUIRE_MOV PSEUDO!", 812 [(set GR64:$dst, (atomic_load_64 addr:$src))]>; 813 814def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src), 815 "#RELEASE_MOV PSEUDO!", 816 [(atomic_store_8 addr:$dst, GR8 :$src)]>; 817def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src), 818 "#RELEASE_MOV PSEUDO!", 819 [(atomic_store_16 addr:$dst, GR16:$src)]>; 820def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src), 821 "#RELEASE_MOV PSEUDO!", 822 [(atomic_store_32 addr:$dst, GR32:$src)]>; 823def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src), 824 "#RELEASE_MOV PSEUDO!", 825 [(atomic_store_64 addr:$dst, GR64:$src)]>; 826 827//===----------------------------------------------------------------------===// 828// Conditional Move Pseudo Instructions. 829//===----------------------------------------------------------------------===// 830 831 832// CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after 833// instruction selection into a branch sequence. 834let Uses = [EFLAGS], usesCustomInserter = 1 in { 835 def CMOV_FR32 : I<0, Pseudo, 836 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond), 837 "#CMOV_FR32 PSEUDO!", 838 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond, 839 EFLAGS))]>; 840 def CMOV_FR64 : I<0, Pseudo, 841 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond), 842 "#CMOV_FR64 PSEUDO!", 843 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond, 844 EFLAGS))]>; 845 def CMOV_V4F32 : I<0, Pseudo, 846 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond), 847 "#CMOV_V4F32 PSEUDO!", 848 [(set VR128:$dst, 849 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond, 850 EFLAGS)))]>; 851 def CMOV_V2F64 : I<0, Pseudo, 852 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond), 853 "#CMOV_V2F64 PSEUDO!", 854 [(set VR128:$dst, 855 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond, 856 EFLAGS)))]>; 857 def CMOV_V2I64 : I<0, Pseudo, 858 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond), 859 "#CMOV_V2I64 PSEUDO!", 860 [(set VR128:$dst, 861 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond, 862 EFLAGS)))]>; 863 def CMOV_V8F32 : I<0, Pseudo, 864 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond), 865 "#CMOV_V8F32 PSEUDO!", 866 [(set VR256:$dst, 867 (v8f32 (X86cmov VR256:$t, VR256:$f, imm:$cond, 868 EFLAGS)))]>; 869 def CMOV_V4F64 : I<0, Pseudo, 870 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond), 871 "#CMOV_V4F64 PSEUDO!", 872 [(set VR256:$dst, 873 (v4f64 (X86cmov VR256:$t, VR256:$f, imm:$cond, 874 EFLAGS)))]>; 875 def CMOV_V4I64 : I<0, Pseudo, 876 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond), 877 "#CMOV_V4I64 PSEUDO!", 878 [(set VR256:$dst, 879 (v4i64 (X86cmov VR256:$t, VR256:$f, imm:$cond, 880 EFLAGS)))]>; 881} 882 883 884//===----------------------------------------------------------------------===// 885// DAG Pattern Matching Rules 886//===----------------------------------------------------------------------===// 887 888// ConstantPool GlobalAddress, ExternalSymbol, and JumpTable 889def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>; 890def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>; 891def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>; 892def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>; 893def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>; 894def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>; 895 896def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)), 897 (ADD32ri GR32:$src1, tconstpool:$src2)>; 898def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)), 899 (ADD32ri GR32:$src1, tjumptable:$src2)>; 900def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)), 901 (ADD32ri GR32:$src1, tglobaladdr:$src2)>; 902def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)), 903 (ADD32ri GR32:$src1, texternalsym:$src2)>; 904def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)), 905 (ADD32ri GR32:$src1, tblockaddress:$src2)>; 906 907def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst), 908 (MOV32mi addr:$dst, tglobaladdr:$src)>; 909def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst), 910 (MOV32mi addr:$dst, texternalsym:$src)>; 911def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst), 912 (MOV32mi addr:$dst, tblockaddress:$src)>; 913 914 915 916// ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small 917// code model mode, should use 'movabs'. FIXME: This is really a hack, the 918// 'movabs' predicate should handle this sort of thing. 919def : Pat<(i64 (X86Wrapper tconstpool :$dst)), 920 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>; 921def : Pat<(i64 (X86Wrapper tjumptable :$dst)), 922 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>; 923def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), 924 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>; 925def : Pat<(i64 (X86Wrapper texternalsym:$dst)), 926 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>; 927def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), 928 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>; 929 930// In static codegen with small code model, we can get the address of a label 931// into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of 932// the MOV64ri64i32 should accept these. 933def : Pat<(i64 (X86Wrapper tconstpool :$dst)), 934 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>; 935def : Pat<(i64 (X86Wrapper tjumptable :$dst)), 936 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>; 937def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), 938 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>; 939def : Pat<(i64 (X86Wrapper texternalsym:$dst)), 940 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>; 941def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), 942 (MOV64ri64i32 tblockaddress:$dst)>, Requires<[SmallCode]>; 943 944// In kernel code model, we can get the address of a label 945// into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of 946// the MOV64ri32 should accept these. 947def : Pat<(i64 (X86Wrapper tconstpool :$dst)), 948 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>; 949def : Pat<(i64 (X86Wrapper tjumptable :$dst)), 950 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>; 951def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), 952 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>; 953def : Pat<(i64 (X86Wrapper texternalsym:$dst)), 954 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>; 955def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), 956 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>; 957 958// If we have small model and -static mode, it is safe to store global addresses 959// directly as immediates. FIXME: This is really a hack, the 'imm' predicate 960// for MOV64mi32 should handle this sort of thing. 961def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst), 962 (MOV64mi32 addr:$dst, tconstpool:$src)>, 963 Requires<[NearData, IsStatic]>; 964def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst), 965 (MOV64mi32 addr:$dst, tjumptable:$src)>, 966 Requires<[NearData, IsStatic]>; 967def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst), 968 (MOV64mi32 addr:$dst, tglobaladdr:$src)>, 969 Requires<[NearData, IsStatic]>; 970def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst), 971 (MOV64mi32 addr:$dst, texternalsym:$src)>, 972 Requires<[NearData, IsStatic]>; 973def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst), 974 (MOV64mi32 addr:$dst, tblockaddress:$src)>, 975 Requires<[NearData, IsStatic]>; 976 977 978 979// Calls 980 981// tls has some funny stuff here... 982// This corresponds to movabs $foo@tpoff, %rax 983def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)), 984 (MOV64ri tglobaltlsaddr :$dst)>; 985// This corresponds to add $foo@tpoff, %rax 986def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)), 987 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>; 988// This corresponds to mov foo@tpoff(%rbx), %eax 989def : Pat<(load (i64 (X86Wrapper tglobaltlsaddr :$dst))), 990 (MOV64rm tglobaltlsaddr :$dst)>; 991 992 993// Direct PC relative function call for small code model. 32-bit displacement 994// sign extended to 64-bit. 995def : Pat<(X86call (i64 tglobaladdr:$dst)), 996 (CALL64pcrel32 tglobaladdr:$dst)>; 997def : Pat<(X86call (i64 texternalsym:$dst)), 998 (CALL64pcrel32 texternalsym:$dst)>; 999 1000// Tailcall stuff. The TCRETURN instructions execute after the epilog, so they 1001// can never use callee-saved registers. That is the purpose of the GR64_TC 1002// register classes. 1003// 1004// The only volatile register that is never used by the calling convention is 1005// %r11. This happens when calling a vararg function with 6 arguments. 1006// 1007// Match an X86tcret that uses less than 7 volatile registers. 1008def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off), 1009 (X86tcret node:$ptr, node:$off), [{ 1010 // X86tcret args: (*chain, ptr, imm, regs..., glue) 1011 unsigned NumRegs = 0; 1012 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i) 1013 if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6) 1014 return false; 1015 return true; 1016}]>; 1017 1018def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), 1019 (TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>, 1020 Requires<[In32BitMode]>; 1021 1022// FIXME: This is disabled for 32-bit PIC mode because the global base 1023// register which is part of the address mode may be assigned a 1024// callee-saved register. 1025def : Pat<(X86tcret (load addr:$dst), imm:$off), 1026 (TCRETURNmi addr:$dst, imm:$off)>, 1027 Requires<[In32BitMode, IsNotPIC]>; 1028 1029def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off), 1030 (TCRETURNdi texternalsym:$dst, imm:$off)>, 1031 Requires<[In32BitMode]>; 1032 1033def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off), 1034 (TCRETURNdi texternalsym:$dst, imm:$off)>, 1035 Requires<[In32BitMode]>; 1036 1037def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), 1038 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>, 1039 Requires<[In64BitMode]>; 1040 1041// Don't fold loads into X86tcret requiring more than 6 regs. 1042// There wouldn't be enough scratch registers for base+index. 1043def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off), 1044 (TCRETURNmi64 addr:$dst, imm:$off)>, 1045 Requires<[In64BitMode]>; 1046 1047def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off), 1048 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>, 1049 Requires<[In64BitMode]>; 1050 1051def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off), 1052 (TCRETURNdi64 texternalsym:$dst, imm:$off)>, 1053 Requires<[In64BitMode]>; 1054 1055// Normal calls, with various flavors of addresses. 1056def : Pat<(X86call (i32 tglobaladdr:$dst)), 1057 (CALLpcrel32 tglobaladdr:$dst)>; 1058def : Pat<(X86call (i32 texternalsym:$dst)), 1059 (CALLpcrel32 texternalsym:$dst)>; 1060def : Pat<(X86call (i32 imm:$dst)), 1061 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>; 1062 1063// Comparisons. 1064 1065// TEST R,R is smaller than CMP R,0 1066def : Pat<(X86cmp GR8:$src1, 0), 1067 (TEST8rr GR8:$src1, GR8:$src1)>; 1068def : Pat<(X86cmp GR16:$src1, 0), 1069 (TEST16rr GR16:$src1, GR16:$src1)>; 1070def : Pat<(X86cmp GR32:$src1, 0), 1071 (TEST32rr GR32:$src1, GR32:$src1)>; 1072def : Pat<(X86cmp GR64:$src1, 0), 1073 (TEST64rr GR64:$src1, GR64:$src1)>; 1074 1075// Conditional moves with folded loads with operands swapped and conditions 1076// inverted. 1077multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32, 1078 Instruction Inst64> { 1079 let Predicates = [HasCMov] in { 1080 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS), 1081 (Inst16 GR16:$src2, addr:$src1)>; 1082 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS), 1083 (Inst32 GR32:$src2, addr:$src1)>; 1084 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS), 1085 (Inst64 GR64:$src2, addr:$src1)>; 1086 } 1087} 1088 1089defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>; 1090defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>; 1091defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>; 1092defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>; 1093defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>; 1094defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>; 1095defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>; 1096defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>; 1097defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>; 1098defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>; 1099defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>; 1100defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>; 1101defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>; 1102defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>; 1103defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>; 1104defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>; 1105 1106// zextload bool -> zextload byte 1107def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>; 1108def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; 1109def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; 1110def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>; 1111 1112// extload bool -> extload byte 1113// When extloading from 16-bit and smaller memory locations into 64-bit 1114// registers, use zero-extending loads so that the entire 64-bit register is 1115// defined, avoiding partial-register updates. 1116 1117def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>; 1118def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; 1119def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; 1120def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>; 1121def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>; 1122def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>; 1123 1124def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>; 1125def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>; 1126def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>; 1127// For other extloads, use subregs, since the high contents of the register are 1128// defined after an extload. 1129def : Pat<(extloadi64i32 addr:$src), 1130 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), 1131 sub_32bit)>; 1132 1133// anyext. Define these to do an explicit zero-extend to 1134// avoid partial-register updates. 1135def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG 1136 (MOVZX32rr8 GR8 :$src), sub_16bit)>; 1137def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>; 1138 1139// Except for i16 -> i32 since isel expect i16 ops to be promoted to i32. 1140def : Pat<(i32 (anyext GR16:$src)), 1141 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>; 1142 1143def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>; 1144def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>; 1145def : Pat<(i64 (anyext GR32:$src)), 1146 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; 1147 1148 1149// Any instruction that defines a 32-bit result leaves the high half of the 1150// register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may 1151// be copying from a truncate. And x86's cmov doesn't do anything if the 1152// condition is false. But any other 32-bit operation will zero-extend 1153// up to 64 bits. 1154def def32 : PatLeaf<(i32 GR32:$src), [{ 1155 return N->getOpcode() != ISD::TRUNCATE && 1156 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG && 1157 N->getOpcode() != ISD::CopyFromReg && 1158 N->getOpcode() != X86ISD::CMOV; 1159}]>; 1160 1161// In the case of a 32-bit def that is known to implicitly zero-extend, 1162// we can use a SUBREG_TO_REG. 1163def : Pat<(i64 (zext def32:$src)), 1164 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; 1165 1166//===----------------------------------------------------------------------===// 1167// Pattern match OR as ADD 1168//===----------------------------------------------------------------------===// 1169 1170// If safe, we prefer to pattern match OR as ADD at isel time. ADD can be 1171// 3-addressified into an LEA instruction to avoid copies. However, we also 1172// want to finally emit these instructions as an or at the end of the code 1173// generator to make the generated code easier to read. To do this, we select 1174// into "disjoint bits" pseudo ops. 1175 1176// Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero. 1177def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{ 1178 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1179 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue()); 1180 1181 APInt KnownZero0, KnownOne0; 1182 CurDAG->ComputeMaskedBits(N->getOperand(0), KnownZero0, KnownOne0, 0); 1183 APInt KnownZero1, KnownOne1; 1184 CurDAG->ComputeMaskedBits(N->getOperand(1), KnownZero1, KnownOne1, 0); 1185 return (~KnownZero0 & ~KnownZero1) == 0; 1186}]>; 1187 1188 1189// (or x1, x2) -> (add x1, x2) if two operands are known not to share bits. 1190let AddedComplexity = 5 in { // Try this before the selecting to OR 1191 1192let isConvertibleToThreeAddress = 1, 1193 Constraints = "$src1 = $dst", Defs = [EFLAGS] in { 1194let isCommutable = 1 in { 1195def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 1196 "", // orw/addw REG, REG 1197 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>; 1198def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 1199 "", // orl/addl REG, REG 1200 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>; 1201def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 1202 "", // orq/addq REG, REG 1203 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>; 1204} // isCommutable 1205 1206// NOTE: These are order specific, we want the ri8 forms to be listed 1207// first so that they are slightly preferred to the ri forms. 1208 1209def ADD16ri8_DB : I<0, Pseudo, 1210 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), 1211 "", // orw/addw REG, imm8 1212 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>; 1213def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), 1214 "", // orw/addw REG, imm 1215 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>; 1216 1217def ADD32ri8_DB : I<0, Pseudo, 1218 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), 1219 "", // orl/addl REG, imm8 1220 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>; 1221def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 1222 "", // orl/addl REG, imm 1223 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>; 1224 1225 1226def ADD64ri8_DB : I<0, Pseudo, 1227 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), 1228 "", // orq/addq REG, imm8 1229 [(set GR64:$dst, (or_is_add GR64:$src1, 1230 i64immSExt8:$src2))]>; 1231def ADD64ri32_DB : I<0, Pseudo, 1232 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), 1233 "", // orq/addq REG, imm 1234 [(set GR64:$dst, (or_is_add GR64:$src1, 1235 i64immSExt32:$src2))]>; 1236} 1237} // AddedComplexity 1238 1239 1240//===----------------------------------------------------------------------===// 1241// Some peepholes 1242//===----------------------------------------------------------------------===// 1243 1244// Odd encoding trick: -128 fits into an 8-bit immediate field while 1245// +128 doesn't, so in this special case use a sub instead of an add. 1246def : Pat<(add GR16:$src1, 128), 1247 (SUB16ri8 GR16:$src1, -128)>; 1248def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst), 1249 (SUB16mi8 addr:$dst, -128)>; 1250 1251def : Pat<(add GR32:$src1, 128), 1252 (SUB32ri8 GR32:$src1, -128)>; 1253def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst), 1254 (SUB32mi8 addr:$dst, -128)>; 1255 1256def : Pat<(add GR64:$src1, 128), 1257 (SUB64ri8 GR64:$src1, -128)>; 1258def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst), 1259 (SUB64mi8 addr:$dst, -128)>; 1260 1261// The same trick applies for 32-bit immediate fields in 64-bit 1262// instructions. 1263def : Pat<(add GR64:$src1, 0x0000000080000000), 1264 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>; 1265def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst), 1266 (SUB64mi32 addr:$dst, 0xffffffff80000000)>; 1267 1268// To avoid needing to materialize an immediate in a register, use a 32-bit and 1269// with implicit zero-extension instead of a 64-bit and if the immediate has at 1270// least 32 bits of leading zeros. If in addition the last 32 bits can be 1271// represented with a sign extension of a 8 bit constant, use that. 1272 1273def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm), 1274 (SUBREG_TO_REG 1275 (i64 0), 1276 (AND32ri8 1277 (EXTRACT_SUBREG GR64:$src, sub_32bit), 1278 (i32 (GetLo8XForm imm:$imm))), 1279 sub_32bit)>; 1280 1281def : Pat<(and GR64:$src, i64immZExt32:$imm), 1282 (SUBREG_TO_REG 1283 (i64 0), 1284 (AND32ri 1285 (EXTRACT_SUBREG GR64:$src, sub_32bit), 1286 (i32 (GetLo32XForm imm:$imm))), 1287 sub_32bit)>; 1288 1289 1290// r & (2^16-1) ==> movz 1291def : Pat<(and GR32:$src1, 0xffff), 1292 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>; 1293// r & (2^8-1) ==> movz 1294def : Pat<(and GR32:$src1, 0xff), 1295 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1, 1296 GR32_ABCD)), 1297 sub_8bit))>, 1298 Requires<[In32BitMode]>; 1299// r & (2^8-1) ==> movz 1300def : Pat<(and GR16:$src1, 0xff), 1301 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG 1302 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)), 1303 sub_16bit)>, 1304 Requires<[In32BitMode]>; 1305 1306// r & (2^32-1) ==> movz 1307def : Pat<(and GR64:$src, 0x00000000FFFFFFFF), 1308 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>; 1309// r & (2^16-1) ==> movz 1310def : Pat<(and GR64:$src, 0xffff), 1311 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit)))>; 1312// r & (2^8-1) ==> movz 1313def : Pat<(and GR64:$src, 0xff), 1314 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit)))>; 1315// r & (2^8-1) ==> movz 1316def : Pat<(and GR32:$src1, 0xff), 1317 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>, 1318 Requires<[In64BitMode]>; 1319// r & (2^8-1) ==> movz 1320def : Pat<(and GR16:$src1, 0xff), 1321 (EXTRACT_SUBREG (MOVZX32rr8 (i8 1322 (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>, 1323 Requires<[In64BitMode]>; 1324 1325 1326// sext_inreg patterns 1327def : Pat<(sext_inreg GR32:$src, i16), 1328 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>; 1329def : Pat<(sext_inreg GR32:$src, i8), 1330 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1331 GR32_ABCD)), 1332 sub_8bit))>, 1333 Requires<[In32BitMode]>; 1334 1335def : Pat<(sext_inreg GR16:$src, i8), 1336 (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG 1337 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))), 1338 sub_16bit)>, 1339 Requires<[In32BitMode]>; 1340 1341def : Pat<(sext_inreg GR64:$src, i32), 1342 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>; 1343def : Pat<(sext_inreg GR64:$src, i16), 1344 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>; 1345def : Pat<(sext_inreg GR64:$src, i8), 1346 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>; 1347def : Pat<(sext_inreg GR32:$src, i8), 1348 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>, 1349 Requires<[In64BitMode]>; 1350def : Pat<(sext_inreg GR16:$src, i8), 1351 (EXTRACT_SUBREG (MOVSX32rr8 1352 (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>, 1353 Requires<[In64BitMode]>; 1354 1355// sext, sext_load, zext, zext_load 1356def: Pat<(i16 (sext GR8:$src)), 1357 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>; 1358def: Pat<(sextloadi16i8 addr:$src), 1359 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>; 1360def: Pat<(i16 (zext GR8:$src)), 1361 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>; 1362def: Pat<(zextloadi16i8 addr:$src), 1363 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1364 1365// trunc patterns 1366def : Pat<(i16 (trunc GR32:$src)), 1367 (EXTRACT_SUBREG GR32:$src, sub_16bit)>; 1368def : Pat<(i8 (trunc GR32:$src)), 1369 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1370 sub_8bit)>, 1371 Requires<[In32BitMode]>; 1372def : Pat<(i8 (trunc GR16:$src)), 1373 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1374 sub_8bit)>, 1375 Requires<[In32BitMode]>; 1376def : Pat<(i32 (trunc GR64:$src)), 1377 (EXTRACT_SUBREG GR64:$src, sub_32bit)>; 1378def : Pat<(i16 (trunc GR64:$src)), 1379 (EXTRACT_SUBREG GR64:$src, sub_16bit)>; 1380def : Pat<(i8 (trunc GR64:$src)), 1381 (EXTRACT_SUBREG GR64:$src, sub_8bit)>; 1382def : Pat<(i8 (trunc GR32:$src)), 1383 (EXTRACT_SUBREG GR32:$src, sub_8bit)>, 1384 Requires<[In64BitMode]>; 1385def : Pat<(i8 (trunc GR16:$src)), 1386 (EXTRACT_SUBREG GR16:$src, sub_8bit)>, 1387 Requires<[In64BitMode]>; 1388 1389// h-register tricks 1390def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))), 1391 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1392 sub_8bit_hi)>, 1393 Requires<[In32BitMode]>; 1394def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))), 1395 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1396 sub_8bit_hi)>, 1397 Requires<[In32BitMode]>; 1398def : Pat<(srl GR16:$src, (i8 8)), 1399 (EXTRACT_SUBREG 1400 (MOVZX32rr8 1401 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1402 sub_8bit_hi)), 1403 sub_16bit)>, 1404 Requires<[In32BitMode]>; 1405def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), 1406 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, 1407 GR16_ABCD)), 1408 sub_8bit_hi))>, 1409 Requires<[In32BitMode]>; 1410def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), 1411 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, 1412 GR16_ABCD)), 1413 sub_8bit_hi))>, 1414 Requires<[In32BitMode]>; 1415def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), 1416 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1417 GR32_ABCD)), 1418 sub_8bit_hi))>, 1419 Requires<[In32BitMode]>; 1420def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)), 1421 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1422 GR32_ABCD)), 1423 sub_8bit_hi))>, 1424 Requires<[In32BitMode]>; 1425 1426// h-register tricks. 1427// For now, be conservative on x86-64 and use an h-register extract only if the 1428// value is immediately zero-extended or stored, which are somewhat common 1429// cases. This uses a bunch of code to prevent a register requiring a REX prefix 1430// from being allocated in the same instruction as the h register, as there's 1431// currently no way to describe this requirement to the register allocator. 1432 1433// h-register extract and zero-extend. 1434def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)), 1435 (SUBREG_TO_REG 1436 (i64 0), 1437 (MOVZX32_NOREXrr8 1438 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)), 1439 sub_8bit_hi)), 1440 sub_32bit)>; 1441def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), 1442 (MOVZX32_NOREXrr8 1443 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1444 sub_8bit_hi))>, 1445 Requires<[In64BitMode]>; 1446def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)), 1447 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1448 GR32_ABCD)), 1449 sub_8bit_hi))>, 1450 Requires<[In64BitMode]>; 1451def : Pat<(srl GR16:$src, (i8 8)), 1452 (EXTRACT_SUBREG 1453 (MOVZX32_NOREXrr8 1454 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1455 sub_8bit_hi)), 1456 sub_16bit)>, 1457 Requires<[In64BitMode]>; 1458def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), 1459 (MOVZX32_NOREXrr8 1460 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1461 sub_8bit_hi))>, 1462 Requires<[In64BitMode]>; 1463def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), 1464 (MOVZX32_NOREXrr8 1465 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1466 sub_8bit_hi))>, 1467 Requires<[In64BitMode]>; 1468def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))), 1469 (SUBREG_TO_REG 1470 (i64 0), 1471 (MOVZX32_NOREXrr8 1472 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1473 sub_8bit_hi)), 1474 sub_32bit)>; 1475def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))), 1476 (SUBREG_TO_REG 1477 (i64 0), 1478 (MOVZX32_NOREXrr8 1479 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1480 sub_8bit_hi)), 1481 sub_32bit)>; 1482 1483// h-register extract and store. 1484def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst), 1485 (MOV8mr_NOREX 1486 addr:$dst, 1487 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)), 1488 sub_8bit_hi))>; 1489def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst), 1490 (MOV8mr_NOREX 1491 addr:$dst, 1492 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1493 sub_8bit_hi))>, 1494 Requires<[In64BitMode]>; 1495def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst), 1496 (MOV8mr_NOREX 1497 addr:$dst, 1498 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1499 sub_8bit_hi))>, 1500 Requires<[In64BitMode]>; 1501 1502 1503// (shl x, 1) ==> (add x, x) 1504// Note that if x is undef (immediate or otherwise), we could theoretically 1505// end up with the two uses of x getting different values, producing a result 1506// where the least significant bit is not 0. However, the probability of this 1507// happening is considered low enough that this is officially not a 1508// "real problem". 1509def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>; 1510def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>; 1511def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>; 1512def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>; 1513 1514// Helper imms that check if a mask doesn't change significant shift bits. 1515def immShift32 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 5; }]>; 1516def immShift64 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 6; }]>; 1517 1518// (shl x (and y, 31)) ==> (shl x, y) 1519def : Pat<(shl GR8:$src1, (and CL, immShift32)), 1520 (SHL8rCL GR8:$src1)>; 1521def : Pat<(shl GR16:$src1, (and CL, immShift32)), 1522 (SHL16rCL GR16:$src1)>; 1523def : Pat<(shl GR32:$src1, (and CL, immShift32)), 1524 (SHL32rCL GR32:$src1)>; 1525def : Pat<(store (shl (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst), 1526 (SHL8mCL addr:$dst)>; 1527def : Pat<(store (shl (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst), 1528 (SHL16mCL addr:$dst)>; 1529def : Pat<(store (shl (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst), 1530 (SHL32mCL addr:$dst)>; 1531 1532def : Pat<(srl GR8:$src1, (and CL, immShift32)), 1533 (SHR8rCL GR8:$src1)>; 1534def : Pat<(srl GR16:$src1, (and CL, immShift32)), 1535 (SHR16rCL GR16:$src1)>; 1536def : Pat<(srl GR32:$src1, (and CL, immShift32)), 1537 (SHR32rCL GR32:$src1)>; 1538def : Pat<(store (srl (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst), 1539 (SHR8mCL addr:$dst)>; 1540def : Pat<(store (srl (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst), 1541 (SHR16mCL addr:$dst)>; 1542def : Pat<(store (srl (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst), 1543 (SHR32mCL addr:$dst)>; 1544 1545def : Pat<(sra GR8:$src1, (and CL, immShift32)), 1546 (SAR8rCL GR8:$src1)>; 1547def : Pat<(sra GR16:$src1, (and CL, immShift32)), 1548 (SAR16rCL GR16:$src1)>; 1549def : Pat<(sra GR32:$src1, (and CL, immShift32)), 1550 (SAR32rCL GR32:$src1)>; 1551def : Pat<(store (sra (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst), 1552 (SAR8mCL addr:$dst)>; 1553def : Pat<(store (sra (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst), 1554 (SAR16mCL addr:$dst)>; 1555def : Pat<(store (sra (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst), 1556 (SAR32mCL addr:$dst)>; 1557 1558// (shl x (and y, 63)) ==> (shl x, y) 1559def : Pat<(shl GR64:$src1, (and CL, immShift64)), 1560 (SHL64rCL GR64:$src1)>; 1561def : Pat<(store (shl (loadi64 addr:$dst), (and CL, 63)), addr:$dst), 1562 (SHL64mCL addr:$dst)>; 1563 1564def : Pat<(srl GR64:$src1, (and CL, immShift64)), 1565 (SHR64rCL GR64:$src1)>; 1566def : Pat<(store (srl (loadi64 addr:$dst), (and CL, 63)), addr:$dst), 1567 (SHR64mCL addr:$dst)>; 1568 1569def : Pat<(sra GR64:$src1, (and CL, immShift64)), 1570 (SAR64rCL GR64:$src1)>; 1571def : Pat<(store (sra (loadi64 addr:$dst), (and CL, 63)), addr:$dst), 1572 (SAR64mCL addr:$dst)>; 1573 1574 1575// (anyext (setcc_carry)) -> (setcc_carry) 1576def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 1577 (SETB_C16r)>; 1578def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 1579 (SETB_C32r)>; 1580def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))), 1581 (SETB_C32r)>; 1582 1583 1584 1585 1586//===----------------------------------------------------------------------===// 1587// EFLAGS-defining Patterns 1588//===----------------------------------------------------------------------===// 1589 1590// add reg, reg 1591def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>; 1592def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>; 1593def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>; 1594 1595// add reg, mem 1596def : Pat<(add GR8:$src1, (loadi8 addr:$src2)), 1597 (ADD8rm GR8:$src1, addr:$src2)>; 1598def : Pat<(add GR16:$src1, (loadi16 addr:$src2)), 1599 (ADD16rm GR16:$src1, addr:$src2)>; 1600def : Pat<(add GR32:$src1, (loadi32 addr:$src2)), 1601 (ADD32rm GR32:$src1, addr:$src2)>; 1602 1603// add reg, imm 1604def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>; 1605def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>; 1606def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>; 1607def : Pat<(add GR16:$src1, i16immSExt8:$src2), 1608 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>; 1609def : Pat<(add GR32:$src1, i32immSExt8:$src2), 1610 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>; 1611 1612// sub reg, reg 1613def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>; 1614def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>; 1615def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>; 1616 1617// sub reg, mem 1618def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)), 1619 (SUB8rm GR8:$src1, addr:$src2)>; 1620def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)), 1621 (SUB16rm GR16:$src1, addr:$src2)>; 1622def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)), 1623 (SUB32rm GR32:$src1, addr:$src2)>; 1624 1625// sub reg, imm 1626def : Pat<(sub GR8:$src1, imm:$src2), 1627 (SUB8ri GR8:$src1, imm:$src2)>; 1628def : Pat<(sub GR16:$src1, imm:$src2), 1629 (SUB16ri GR16:$src1, imm:$src2)>; 1630def : Pat<(sub GR32:$src1, imm:$src2), 1631 (SUB32ri GR32:$src1, imm:$src2)>; 1632def : Pat<(sub GR16:$src1, i16immSExt8:$src2), 1633 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>; 1634def : Pat<(sub GR32:$src1, i32immSExt8:$src2), 1635 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>; 1636 1637// sub 0, reg 1638def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>; 1639def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>; 1640def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>; 1641def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>; 1642 1643// mul reg, reg 1644def : Pat<(mul GR16:$src1, GR16:$src2), 1645 (IMUL16rr GR16:$src1, GR16:$src2)>; 1646def : Pat<(mul GR32:$src1, GR32:$src2), 1647 (IMUL32rr GR32:$src1, GR32:$src2)>; 1648 1649// mul reg, mem 1650def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)), 1651 (IMUL16rm GR16:$src1, addr:$src2)>; 1652def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)), 1653 (IMUL32rm GR32:$src1, addr:$src2)>; 1654 1655// mul reg, imm 1656def : Pat<(mul GR16:$src1, imm:$src2), 1657 (IMUL16rri GR16:$src1, imm:$src2)>; 1658def : Pat<(mul GR32:$src1, imm:$src2), 1659 (IMUL32rri GR32:$src1, imm:$src2)>; 1660def : Pat<(mul GR16:$src1, i16immSExt8:$src2), 1661 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>; 1662def : Pat<(mul GR32:$src1, i32immSExt8:$src2), 1663 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>; 1664 1665// reg = mul mem, imm 1666def : Pat<(mul (loadi16 addr:$src1), imm:$src2), 1667 (IMUL16rmi addr:$src1, imm:$src2)>; 1668def : Pat<(mul (loadi32 addr:$src1), imm:$src2), 1669 (IMUL32rmi addr:$src1, imm:$src2)>; 1670def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2), 1671 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>; 1672def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2), 1673 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>; 1674 1675// Patterns for nodes that do not produce flags, for instructions that do. 1676 1677// addition 1678def : Pat<(add GR64:$src1, GR64:$src2), 1679 (ADD64rr GR64:$src1, GR64:$src2)>; 1680def : Pat<(add GR64:$src1, i64immSExt8:$src2), 1681 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>; 1682def : Pat<(add GR64:$src1, i64immSExt32:$src2), 1683 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>; 1684def : Pat<(add GR64:$src1, (loadi64 addr:$src2)), 1685 (ADD64rm GR64:$src1, addr:$src2)>; 1686 1687// subtraction 1688def : Pat<(sub GR64:$src1, GR64:$src2), 1689 (SUB64rr GR64:$src1, GR64:$src2)>; 1690def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)), 1691 (SUB64rm GR64:$src1, addr:$src2)>; 1692def : Pat<(sub GR64:$src1, i64immSExt8:$src2), 1693 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>; 1694def : Pat<(sub GR64:$src1, i64immSExt32:$src2), 1695 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>; 1696 1697// Multiply 1698def : Pat<(mul GR64:$src1, GR64:$src2), 1699 (IMUL64rr GR64:$src1, GR64:$src2)>; 1700def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)), 1701 (IMUL64rm GR64:$src1, addr:$src2)>; 1702def : Pat<(mul GR64:$src1, i64immSExt8:$src2), 1703 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>; 1704def : Pat<(mul GR64:$src1, i64immSExt32:$src2), 1705 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>; 1706def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2), 1707 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>; 1708def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2), 1709 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>; 1710 1711// Increment reg. 1712def : Pat<(add GR8 :$src, 1), (INC8r GR8 :$src)>; 1713def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>, Requires<[In32BitMode]>; 1714def : Pat<(add GR16:$src, 1), (INC64_16r GR16:$src)>, Requires<[In64BitMode]>; 1715def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>, Requires<[In32BitMode]>; 1716def : Pat<(add GR32:$src, 1), (INC64_32r GR32:$src)>, Requires<[In64BitMode]>; 1717def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>; 1718 1719// Decrement reg. 1720def : Pat<(add GR8 :$src, -1), (DEC8r GR8 :$src)>; 1721def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>, Requires<[In32BitMode]>; 1722def : Pat<(add GR16:$src, -1), (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>; 1723def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>, Requires<[In32BitMode]>; 1724def : Pat<(add GR32:$src, -1), (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>; 1725def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>; 1726 1727// or reg/reg. 1728def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>; 1729def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>; 1730def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>; 1731def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>; 1732 1733// or reg/mem 1734def : Pat<(or GR8:$src1, (loadi8 addr:$src2)), 1735 (OR8rm GR8:$src1, addr:$src2)>; 1736def : Pat<(or GR16:$src1, (loadi16 addr:$src2)), 1737 (OR16rm GR16:$src1, addr:$src2)>; 1738def : Pat<(or GR32:$src1, (loadi32 addr:$src2)), 1739 (OR32rm GR32:$src1, addr:$src2)>; 1740def : Pat<(or GR64:$src1, (loadi64 addr:$src2)), 1741 (OR64rm GR64:$src1, addr:$src2)>; 1742 1743// or reg/imm 1744def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>; 1745def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>; 1746def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>; 1747def : Pat<(or GR16:$src1, i16immSExt8:$src2), 1748 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>; 1749def : Pat<(or GR32:$src1, i32immSExt8:$src2), 1750 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>; 1751def : Pat<(or GR64:$src1, i64immSExt8:$src2), 1752 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>; 1753def : Pat<(or GR64:$src1, i64immSExt32:$src2), 1754 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>; 1755 1756// xor reg/reg 1757def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>; 1758def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>; 1759def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>; 1760def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>; 1761 1762// xor reg/mem 1763def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)), 1764 (XOR8rm GR8:$src1, addr:$src2)>; 1765def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)), 1766 (XOR16rm GR16:$src1, addr:$src2)>; 1767def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)), 1768 (XOR32rm GR32:$src1, addr:$src2)>; 1769def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)), 1770 (XOR64rm GR64:$src1, addr:$src2)>; 1771 1772// xor reg/imm 1773def : Pat<(xor GR8:$src1, imm:$src2), 1774 (XOR8ri GR8:$src1, imm:$src2)>; 1775def : Pat<(xor GR16:$src1, imm:$src2), 1776 (XOR16ri GR16:$src1, imm:$src2)>; 1777def : Pat<(xor GR32:$src1, imm:$src2), 1778 (XOR32ri GR32:$src1, imm:$src2)>; 1779def : Pat<(xor GR16:$src1, i16immSExt8:$src2), 1780 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>; 1781def : Pat<(xor GR32:$src1, i32immSExt8:$src2), 1782 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>; 1783def : Pat<(xor GR64:$src1, i64immSExt8:$src2), 1784 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>; 1785def : Pat<(xor GR64:$src1, i64immSExt32:$src2), 1786 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>; 1787 1788// and reg/reg 1789def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>; 1790def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>; 1791def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>; 1792def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>; 1793 1794// and reg/mem 1795def : Pat<(and GR8:$src1, (loadi8 addr:$src2)), 1796 (AND8rm GR8:$src1, addr:$src2)>; 1797def : Pat<(and GR16:$src1, (loadi16 addr:$src2)), 1798 (AND16rm GR16:$src1, addr:$src2)>; 1799def : Pat<(and GR32:$src1, (loadi32 addr:$src2)), 1800 (AND32rm GR32:$src1, addr:$src2)>; 1801def : Pat<(and GR64:$src1, (loadi64 addr:$src2)), 1802 (AND64rm GR64:$src1, addr:$src2)>; 1803 1804// and reg/imm 1805def : Pat<(and GR8:$src1, imm:$src2), 1806 (AND8ri GR8:$src1, imm:$src2)>; 1807def : Pat<(and GR16:$src1, imm:$src2), 1808 (AND16ri GR16:$src1, imm:$src2)>; 1809def : Pat<(and GR32:$src1, imm:$src2), 1810 (AND32ri GR32:$src1, imm:$src2)>; 1811def : Pat<(and GR16:$src1, i16immSExt8:$src2), 1812 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>; 1813def : Pat<(and GR32:$src1, i32immSExt8:$src2), 1814 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>; 1815def : Pat<(and GR64:$src1, i64immSExt8:$src2), 1816 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>; 1817def : Pat<(and GR64:$src1, i64immSExt32:$src2), 1818 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>; 1819 1820// Bit scan instruction patterns to match explicit zero-undef behavior. 1821def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>; 1822def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>; 1823def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>; 1824def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>; 1825def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>; 1826def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>; 1827