X86InstrCompiler.td revision 230393
1//===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the various pseudo instructions used by the compiler, 11// as well as Pat patterns used during instruction selection. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// Pattern Matching Support 17 18def GetLo32XForm : SDNodeXForm<imm, [{ 19 // Transformation function: get the low 32 bits. 20 return getI32Imm((unsigned)N->getZExtValue()); 21}]>; 22 23def GetLo8XForm : SDNodeXForm<imm, [{ 24 // Transformation function: get the low 8 bits. 25 return getI8Imm((uint8_t)N->getZExtValue()); 26}]>; 27 28 29//===----------------------------------------------------------------------===// 30// Random Pseudo Instructions. 31 32// PIC base construction. This expands to code that looks like this: 33// call $next_inst 34// popl %destreg" 35let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in 36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label), 37 "", []>; 38 39 40// ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into 41// a stack adjustment and the codegen must know that they may modify the stack 42// pointer before prolog-epilog rewriting occurs. 43// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 44// sub / add which can clobber EFLAGS. 45let Defs = [ESP, EFLAGS], Uses = [ESP] in { 46def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt), 47 "#ADJCALLSTACKDOWN", 48 [(X86callseq_start timm:$amt)]>, 49 Requires<[In32BitMode]>; 50def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 51 "#ADJCALLSTACKUP", 52 [(X86callseq_end timm:$amt1, timm:$amt2)]>, 53 Requires<[In32BitMode]>; 54} 55 56// ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into 57// a stack adjustment and the codegen must know that they may modify the stack 58// pointer before prolog-epilog rewriting occurs. 59// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 60// sub / add which can clobber EFLAGS. 61let Defs = [RSP, EFLAGS], Uses = [RSP] in { 62def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt), 63 "#ADJCALLSTACKDOWN", 64 [(X86callseq_start timm:$amt)]>, 65 Requires<[In64BitMode]>; 66def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 67 "#ADJCALLSTACKUP", 68 [(X86callseq_end timm:$amt1, timm:$amt2)]>, 69 Requires<[In64BitMode]>; 70} 71 72 73 74// x86-64 va_start lowering magic. 75let usesCustomInserter = 1 in { 76def VASTART_SAVE_XMM_REGS : I<0, Pseudo, 77 (outs), 78 (ins GR8:$al, 79 i64imm:$regsavefi, i64imm:$offset, 80 variable_ops), 81 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset", 82 [(X86vastart_save_xmm_regs GR8:$al, 83 imm:$regsavefi, 84 imm:$offset)]>; 85 86// The VAARG_64 pseudo-instruction takes the address of the va_list, 87// and places the address of the next argument into a register. 88let Defs = [EFLAGS] in 89def VAARG_64 : I<0, Pseudo, 90 (outs GR64:$dst), 91 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align), 92 "#VAARG_64 $dst, $ap, $size, $mode, $align", 93 [(set GR64:$dst, 94 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)), 95 (implicit EFLAGS)]>; 96 97// Dynamic stack allocation yields a _chkstk or _alloca call for all Windows 98// targets. These calls are needed to probe the stack when allocating more than 99// 4k bytes in one go. Touching the stack at 4K increments is necessary to 100// ensure that the guard pages used by the OS virtual memory manager are 101// allocated in correct sequence. 102// The main point of having separate instruction are extra unmodelled effects 103// (compared to ordinary calls) like stack pointer change. 104 105let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 106 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins), 107 "# dynamic stack allocation", 108 [(X86WinAlloca)]>; 109 110// When using segmented stacks these are lowered into instructions which first 111// check if the current stacklet has enough free memory. If it does, memory is 112// allocated by bumping the stack pointer. Otherwise memory is allocated from 113// the heap. 114 115let Defs = [EAX, ESP, EFLAGS], Uses = [ESP, EAX] in 116def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size), 117 "# variable sized alloca for segmented stacks", 118 [(set GR32:$dst, 119 (X86SegAlloca GR32:$size))]>, 120 Requires<[In32BitMode]>; 121 122let Defs = [RAX, RSP, EFLAGS], Uses = [RSP, RAX] in 123def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size), 124 "# variable sized alloca for segmented stacks", 125 [(set GR64:$dst, 126 (X86SegAlloca GR64:$size))]>, 127 Requires<[In64BitMode]>; 128 129} 130 131 132 133//===----------------------------------------------------------------------===// 134// EH Pseudo Instructions 135// 136let isTerminator = 1, isReturn = 1, isBarrier = 1, 137 hasCtrlDep = 1, isCodeGenOnly = 1 in { 138def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr), 139 "ret\t#eh_return, addr: $addr", 140 [(X86ehret GR32:$addr)]>; 141 142} 143 144let isTerminator = 1, isReturn = 1, isBarrier = 1, 145 hasCtrlDep = 1, isCodeGenOnly = 1 in { 146def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr), 147 "ret\t#eh_return, addr: $addr", 148 [(X86ehret GR64:$addr)]>; 149 150} 151 152//===----------------------------------------------------------------------===// 153// Alias Instructions 154//===----------------------------------------------------------------------===// 155 156// Alias instructions that map movr0 to xor. 157// FIXME: remove when we can teach regalloc that xor reg, reg is ok. 158// FIXME: Set encoding to pseudo. 159let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1, 160 isCodeGenOnly = 1 in { 161def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "", 162 [(set GR8:$dst, 0)]>; 163 164// We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller 165// encoding and avoids a partial-register update sometimes, but doing so 166// at isel time interferes with rematerialization in the current register 167// allocator. For now, this is rewritten when the instruction is lowered 168// to an MCInst. 169def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins), 170 "", 171 [(set GR16:$dst, 0)]>, OpSize; 172 173// FIXME: Set encoding to pseudo. 174def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "", 175 [(set GR32:$dst, 0)]>; 176} 177 178// We want to rewrite MOV64r0 in terms of MOV32r0, because it's sometimes a 179// smaller encoding, but doing so at isel time interferes with rematerialization 180// in the current register allocator. For now, this is rewritten when the 181// instruction is lowered to an MCInst. 182// FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove 183// when we have a better way to specify isel priority. 184let Defs = [EFLAGS], isCodeGenOnly=1, 185 AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in 186def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins), "", 187 [(set GR64:$dst, 0)]>; 188 189// Materialize i64 constant where top 32-bits are zero. This could theoretically 190// use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however 191// that would make it more difficult to rematerialize. 192let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1, 193 isCodeGenOnly = 1 in 194def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src), 195 "", [(set GR64:$dst, i64immZExt32:$src)]>; 196 197// Use sbb to materialize carry bit. 198let Uses = [EFLAGS], Defs = [EFLAGS], isCodeGenOnly = 1 in { 199// FIXME: These are pseudo ops that should be replaced with Pat<> patterns. 200// However, Pat<> can't replicate the destination reg into the inputs of the 201// result. 202// FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces 203// X86CodeEmitter. 204def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "", 205 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 206def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "", 207 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>, 208 OpSize; 209def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "", 210 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 211def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins), "", 212 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 213} // isCodeGenOnly 214 215 216def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 217 (SETB_C16r)>; 218def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 219 (SETB_C32r)>; 220def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 221 (SETB_C64r)>; 222 223def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 224 (SETB_C16r)>; 225def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 226 (SETB_C32r)>; 227def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 228 (SETB_C64r)>; 229 230// We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and 231// will be eliminated and that the sbb can be extended up to a wider type. When 232// this happens, it is great. However, if we are left with an 8-bit sbb and an 233// and, we might as well just match it as a setb. 234def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), 235 (SETBr)>; 236 237// (add OP, SETB) -> (adc OP, 0) 238def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op), 239 (ADC8ri GR8:$op, 0)>; 240def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op), 241 (ADC32ri8 GR32:$op, 0)>; 242def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op), 243 (ADC64ri8 GR64:$op, 0)>; 244 245// (sub OP, SETB) -> (sbb OP, 0) 246def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)), 247 (SBB8ri GR8:$op, 0)>; 248def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)), 249 (SBB32ri8 GR32:$op, 0)>; 250def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)), 251 (SBB64ri8 GR64:$op, 0)>; 252 253// (sub OP, SETCC_CARRY) -> (adc OP, 0) 254def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))), 255 (ADC8ri GR8:$op, 0)>; 256def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))), 257 (ADC32ri8 GR32:$op, 0)>; 258def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))), 259 (ADC64ri8 GR64:$op, 0)>; 260 261//===----------------------------------------------------------------------===// 262// String Pseudo Instructions 263// 264let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in { 265def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}", 266 [(X86rep_movs i8)]>, REP; 267def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}", 268 [(X86rep_movs i16)]>, REP, OpSize; 269def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}", 270 [(X86rep_movs i32)]>, REP; 271} 272 273let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in 274def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}", 275 [(X86rep_movs i64)]>, REP; 276 277 278// FIXME: Should use "(X86rep_stos AL)" as the pattern. 279let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in 280def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}", 281 [(X86rep_stos i8)]>, REP; 282let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in 283def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}", 284 [(X86rep_stos i16)]>, REP, OpSize; 285let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in 286def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}", 287 [(X86rep_stos i32)]>, REP; 288 289let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI], isCodeGenOnly = 1 in 290def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}", 291 [(X86rep_stos i64)]>, REP; 292 293 294//===----------------------------------------------------------------------===// 295// Thread Local Storage Instructions 296// 297 298// ELF TLS Support 299// All calls clobber the non-callee saved registers. ESP is marked as 300// a use to prevent stack-pointer assignments that appear immediately 301// before calls from potentially appearing dead. 302let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, 303 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 304 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 305 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], 306 Uses = [ESP] in 307def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 308 "# TLS_addr32", 309 [(X86tlsaddr tls32addr:$sym)]>, 310 Requires<[In32BitMode]>; 311 312// All calls clobber the non-callee saved registers. RSP is marked as 313// a use to prevent stack-pointer assignments that appear immediately 314// before calls from potentially appearing dead. 315let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, 316 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1, 317 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 318 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 319 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], 320 Uses = [RSP] in 321def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 322 "# TLS_addr64", 323 [(X86tlsaddr tls64addr:$sym)]>, 324 Requires<[In64BitMode]>; 325 326// Darwin TLS Support 327// For i386, the address of the thunk is passed on the stack, on return the 328// address of the variable is in %eax. %ecx is trashed during the function 329// call. All other registers are preserved. 330let Defs = [EAX, ECX, EFLAGS], 331 Uses = [ESP], 332 usesCustomInserter = 1 in 333def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 334 "# TLSCall_32", 335 [(X86TLSCall addr:$sym)]>, 336 Requires<[In32BitMode]>; 337 338// For x86_64, the address of the thunk is passed in %rdi, on return 339// the address of the variable is in %rax. All other registers are preserved. 340let Defs = [RAX, EFLAGS], 341 Uses = [RSP, RDI], 342 usesCustomInserter = 1 in 343def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 344 "# TLSCall_64", 345 [(X86TLSCall addr:$sym)]>, 346 Requires<[In64BitMode]>; 347 348 349//===----------------------------------------------------------------------===// 350// Conditional Move Pseudo Instructions 351 352// X86 doesn't have 8-bit conditional moves. Use a customInserter to 353// emit control flow. An alternative to this is to mark i8 SELECT as Promote, 354// however that requires promoting the operands, and can induce additional 355// i8 register pressure. 356let usesCustomInserter = 1, Uses = [EFLAGS] in { 357def CMOV_GR8 : I<0, Pseudo, 358 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond), 359 "#CMOV_GR8 PSEUDO!", 360 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2, 361 imm:$cond, EFLAGS))]>; 362 363let Predicates = [NoCMov] in { 364def CMOV_GR32 : I<0, Pseudo, 365 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond), 366 "#CMOV_GR32* PSEUDO!", 367 [(set GR32:$dst, 368 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>; 369def CMOV_GR16 : I<0, Pseudo, 370 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond), 371 "#CMOV_GR16* PSEUDO!", 372 [(set GR16:$dst, 373 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>; 374def CMOV_RFP32 : I<0, Pseudo, 375 (outs RFP32:$dst), 376 (ins RFP32:$src1, RFP32:$src2, i8imm:$cond), 377 "#CMOV_RFP32 PSEUDO!", 378 [(set RFP32:$dst, 379 (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond, 380 EFLAGS))]>; 381def CMOV_RFP64 : I<0, Pseudo, 382 (outs RFP64:$dst), 383 (ins RFP64:$src1, RFP64:$src2, i8imm:$cond), 384 "#CMOV_RFP64 PSEUDO!", 385 [(set RFP64:$dst, 386 (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond, 387 EFLAGS))]>; 388def CMOV_RFP80 : I<0, Pseudo, 389 (outs RFP80:$dst), 390 (ins RFP80:$src1, RFP80:$src2, i8imm:$cond), 391 "#CMOV_RFP80 PSEUDO!", 392 [(set RFP80:$dst, 393 (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond, 394 EFLAGS))]>; 395} // Predicates = [NoCMov] 396} // UsesCustomInserter = 1, Uses = [EFLAGS] 397 398 399//===----------------------------------------------------------------------===// 400// Atomic Instruction Pseudo Instructions 401//===----------------------------------------------------------------------===// 402 403// Atomic exchange, and, or, xor 404let Constraints = "$val = $dst", Defs = [EFLAGS], 405 usesCustomInserter = 1 in { 406 407def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val), 408 "#ATOMAND8 PSEUDO!", 409 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>; 410def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val), 411 "#ATOMOR8 PSEUDO!", 412 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>; 413def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val), 414 "#ATOMXOR8 PSEUDO!", 415 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>; 416def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val), 417 "#ATOMNAND8 PSEUDO!", 418 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>; 419 420def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), 421 "#ATOMAND16 PSEUDO!", 422 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>; 423def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), 424 "#ATOMOR16 PSEUDO!", 425 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>; 426def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), 427 "#ATOMXOR16 PSEUDO!", 428 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>; 429def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), 430 "#ATOMNAND16 PSEUDO!", 431 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>; 432def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val), 433 "#ATOMMIN16 PSEUDO!", 434 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>; 435def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), 436 "#ATOMMAX16 PSEUDO!", 437 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>; 438def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), 439 "#ATOMUMIN16 PSEUDO!", 440 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>; 441def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), 442 "#ATOMUMAX16 PSEUDO!", 443 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>; 444 445 446def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), 447 "#ATOMAND32 PSEUDO!", 448 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>; 449def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), 450 "#ATOMOR32 PSEUDO!", 451 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>; 452def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), 453 "#ATOMXOR32 PSEUDO!", 454 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>; 455def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), 456 "#ATOMNAND32 PSEUDO!", 457 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>; 458def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val), 459 "#ATOMMIN32 PSEUDO!", 460 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>; 461def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), 462 "#ATOMMAX32 PSEUDO!", 463 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>; 464def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), 465 "#ATOMUMIN32 PSEUDO!", 466 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>; 467def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), 468 "#ATOMUMAX32 PSEUDO!", 469 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>; 470 471 472 473def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val), 474 "#ATOMAND64 PSEUDO!", 475 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>; 476def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val), 477 "#ATOMOR64 PSEUDO!", 478 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>; 479def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val), 480 "#ATOMXOR64 PSEUDO!", 481 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>; 482def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val), 483 "#ATOMNAND64 PSEUDO!", 484 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>; 485def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val), 486 "#ATOMMIN64 PSEUDO!", 487 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>; 488def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val), 489 "#ATOMMAX64 PSEUDO!", 490 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>; 491def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val), 492 "#ATOMUMIN64 PSEUDO!", 493 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>; 494def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val), 495 "#ATOMUMAX64 PSEUDO!", 496 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>; 497} 498 499let Constraints = "$val1 = $dst1, $val2 = $dst2", 500 Defs = [EFLAGS, EAX, EBX, ECX, EDX], 501 Uses = [EAX, EBX, ECX, EDX], 502 mayLoad = 1, mayStore = 1, 503 usesCustomInserter = 1 in { 504def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), 505 (ins i64mem:$ptr, GR32:$val1, GR32:$val2), 506 "#ATOMAND6432 PSEUDO!", []>; 507def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), 508 (ins i64mem:$ptr, GR32:$val1, GR32:$val2), 509 "#ATOMOR6432 PSEUDO!", []>; 510def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), 511 (ins i64mem:$ptr, GR32:$val1, GR32:$val2), 512 "#ATOMXOR6432 PSEUDO!", []>; 513def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), 514 (ins i64mem:$ptr, GR32:$val1, GR32:$val2), 515 "#ATOMNAND6432 PSEUDO!", []>; 516def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), 517 (ins i64mem:$ptr, GR32:$val1, GR32:$val2), 518 "#ATOMADD6432 PSEUDO!", []>; 519def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), 520 (ins i64mem:$ptr, GR32:$val1, GR32:$val2), 521 "#ATOMSUB6432 PSEUDO!", []>; 522def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), 523 (ins i64mem:$ptr, GR32:$val1, GR32:$val2), 524 "#ATOMSWAP6432 PSEUDO!", []>; 525} 526 527//===----------------------------------------------------------------------===// 528// Normal-Instructions-With-Lock-Prefix Pseudo Instructions 529//===----------------------------------------------------------------------===// 530 531// FIXME: Use normal instructions and add lock prefix dynamically. 532 533// Memory barriers 534 535// TODO: Get this to fold the constant into the instruction. 536let isCodeGenOnly = 1, Defs = [EFLAGS] in 537def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero), 538 "lock\n\t" 539 "or{l}\t{$zero, $dst|$dst, $zero}", 540 []>, Requires<[In32BitMode]>, LOCK; 541 542let hasSideEffects = 1 in 543def Int_MemBarrier : I<0, Pseudo, (outs), (ins), 544 "#MEMBARRIER", 545 [(X86MemBarrier)]>; 546 547// TODO: Get this to fold the constant into the instruction. 548let hasSideEffects = 1, Defs = [ESP], isCodeGenOnly = 1 in 549def Int_MemBarrierNoSSE64 : RI<0x09, MRM1r, (outs), (ins GR64:$zero), 550 "lock\n\t" 551 "or{q}\t{$zero, (%rsp)|(%rsp), $zero}", 552 [(X86MemBarrierNoSSE GR64:$zero)]>, 553 Requires<[In64BitMode]>, LOCK; 554 555 556// RegOpc corresponds to the mr version of the instruction 557// ImmOpc corresponds to the mi version of the instruction 558// ImmOpc8 corresponds to the mi8 version of the instruction 559// ImmMod corresponds to the instruction format of the mi and mi8 versions 560multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8, 561 Format ImmMod, string mnemonic> { 562let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1 in { 563 564def #NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 565 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 }, 566 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), 567 !strconcat("lock\n\t", mnemonic, "{b}\t", 568 "{$src2, $dst|$dst, $src2}"), 569 []>, LOCK; 570def #NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 571 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 572 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), 573 !strconcat("lock\n\t", mnemonic, "{w}\t", 574 "{$src2, $dst|$dst, $src2}"), 575 []>, OpSize, LOCK; 576def #NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 577 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 578 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), 579 !strconcat("lock\n\t", mnemonic, "{l}\t", 580 "{$src2, $dst|$dst, $src2}"), 581 []>, LOCK; 582def #NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 583 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 584 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), 585 !strconcat("lock\n\t", mnemonic, "{q}\t", 586 "{$src2, $dst|$dst, $src2}"), 587 []>, LOCK; 588 589def #NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 590 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 }, 591 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2), 592 !strconcat("lock\n\t", mnemonic, "{b}\t", 593 "{$src2, $dst|$dst, $src2}"), 594 []>, LOCK; 595 596def #NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 597 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 598 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2), 599 !strconcat("lock\n\t", mnemonic, "{w}\t", 600 "{$src2, $dst|$dst, $src2}"), 601 []>, LOCK; 602 603def #NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 604 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 605 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2), 606 !strconcat("lock\n\t", mnemonic, "{l}\t", 607 "{$src2, $dst|$dst, $src2}"), 608 []>, LOCK; 609 610def #NAME#64mi32 : RIi32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 611 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 612 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2), 613 !strconcat("lock\n\t", mnemonic, "{q}\t", 614 "{$src2, $dst|$dst, $src2}"), 615 []>, LOCK; 616 617def #NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 618 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 619 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2), 620 !strconcat("lock\n\t", mnemonic, "{w}\t", 621 "{$src2, $dst|$dst, $src2}"), 622 []>, LOCK; 623def #NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 624 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 625 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2), 626 !strconcat("lock\n\t", mnemonic, "{l}\t", 627 "{$src2, $dst|$dst, $src2}"), 628 []>, LOCK; 629def #NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 630 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 631 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2), 632 !strconcat("lock\n\t", mnemonic, "{q}\t", 633 "{$src2, $dst|$dst, $src2}"), 634 []>, LOCK; 635 636} 637 638} 639 640defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">; 641defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">; 642defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, "or">; 643defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">; 644defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">; 645 646// Optimized codegen when the non-memory output is not used. 647let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1 in { 648 649def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), 650 "lock\n\t" 651 "inc{b}\t$dst", []>, LOCK; 652def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), 653 "lock\n\t" 654 "inc{w}\t$dst", []>, OpSize, LOCK; 655def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), 656 "lock\n\t" 657 "inc{l}\t$dst", []>, LOCK; 658def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), 659 "lock\n\t" 660 "inc{q}\t$dst", []>, LOCK; 661 662def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), 663 "lock\n\t" 664 "dec{b}\t$dst", []>, LOCK; 665def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), 666 "lock\n\t" 667 "dec{w}\t$dst", []>, OpSize, LOCK; 668def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), 669 "lock\n\t" 670 "dec{l}\t$dst", []>, LOCK; 671def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), 672 "lock\n\t" 673 "dec{q}\t$dst", []>, LOCK; 674} 675 676// Atomic compare and swap. 677let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX], 678 isCodeGenOnly = 1 in 679def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr), 680 "lock\n\t" 681 "cmpxchg8b\t$ptr", 682 [(X86cas8 addr:$ptr)]>, TB, LOCK; 683 684let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX], 685 isCodeGenOnly = 1 in 686def LCMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$ptr), 687 "lock\n\t" 688 "cmpxchg16b\t$ptr", 689 [(X86cas16 addr:$ptr)]>, TB, LOCK, 690 Requires<[HasCmpxchg16b]>; 691 692let Defs = [AL, EFLAGS], Uses = [AL], isCodeGenOnly = 1 in { 693def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap), 694 "lock\n\t" 695 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}", 696 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK; 697} 698 699let Defs = [AX, EFLAGS], Uses = [AX], isCodeGenOnly = 1 in { 700def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap), 701 "lock\n\t" 702 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}", 703 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK; 704} 705 706let Defs = [EAX, EFLAGS], Uses = [EAX], isCodeGenOnly = 1 in { 707def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap), 708 "lock\n\t" 709 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}", 710 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK; 711} 712 713let Defs = [RAX, EFLAGS], Uses = [RAX], isCodeGenOnly = 1 in { 714def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap), 715 "lock\n\t" 716 "cmpxchg{q}\t{$swap, $ptr|$ptr, $swap}", 717 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK; 718} 719 720// Atomic exchange and add 721let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1 in { 722def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr), 723 "lock\n\t" 724 "xadd{b}\t{$val, $ptr|$ptr, $val}", 725 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>, 726 TB, LOCK; 727def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr), 728 "lock\n\t" 729 "xadd{w}\t{$val, $ptr|$ptr, $val}", 730 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>, 731 TB, OpSize, LOCK; 732def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr), 733 "lock\n\t" 734 "xadd{l}\t{$val, $ptr|$ptr, $val}", 735 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>, 736 TB, LOCK; 737def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins GR64:$val,i64mem:$ptr), 738 "lock\n\t" 739 "xadd{q}\t{$val, $ptr|$ptr, $val}", 740 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>, 741 TB, LOCK; 742} 743 744def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src), 745 "#ACQUIRE_MOV PSEUDO!", 746 [(set GR8:$dst, (atomic_load_8 addr:$src))]>; 747def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src), 748 "#ACQUIRE_MOV PSEUDO!", 749 [(set GR16:$dst, (atomic_load_16 addr:$src))]>; 750def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src), 751 "#ACQUIRE_MOV PSEUDO!", 752 [(set GR32:$dst, (atomic_load_32 addr:$src))]>; 753def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src), 754 "#ACQUIRE_MOV PSEUDO!", 755 [(set GR64:$dst, (atomic_load_64 addr:$src))]>; 756 757def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src), 758 "#RELEASE_MOV PSEUDO!", 759 [(atomic_store_8 addr:$dst, GR8 :$src)]>; 760def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src), 761 "#RELEASE_MOV PSEUDO!", 762 [(atomic_store_16 addr:$dst, GR16:$src)]>; 763def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src), 764 "#RELEASE_MOV PSEUDO!", 765 [(atomic_store_32 addr:$dst, GR32:$src)]>; 766def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src), 767 "#RELEASE_MOV PSEUDO!", 768 [(atomic_store_64 addr:$dst, GR64:$src)]>; 769 770//===----------------------------------------------------------------------===// 771// Conditional Move Pseudo Instructions. 772//===----------------------------------------------------------------------===// 773 774 775// CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after 776// instruction selection into a branch sequence. 777let Uses = [EFLAGS], usesCustomInserter = 1 in { 778 def CMOV_FR32 : I<0, Pseudo, 779 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond), 780 "#CMOV_FR32 PSEUDO!", 781 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond, 782 EFLAGS))]>; 783 def CMOV_FR64 : I<0, Pseudo, 784 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond), 785 "#CMOV_FR64 PSEUDO!", 786 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond, 787 EFLAGS))]>; 788 def CMOV_V4F32 : I<0, Pseudo, 789 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond), 790 "#CMOV_V4F32 PSEUDO!", 791 [(set VR128:$dst, 792 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond, 793 EFLAGS)))]>; 794 def CMOV_V2F64 : I<0, Pseudo, 795 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond), 796 "#CMOV_V2F64 PSEUDO!", 797 [(set VR128:$dst, 798 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond, 799 EFLAGS)))]>; 800 def CMOV_V2I64 : I<0, Pseudo, 801 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond), 802 "#CMOV_V2I64 PSEUDO!", 803 [(set VR128:$dst, 804 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond, 805 EFLAGS)))]>; 806 def CMOV_V8F32 : I<0, Pseudo, 807 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond), 808 "#CMOV_V8F32 PSEUDO!", 809 [(set VR256:$dst, 810 (v8f32 (X86cmov VR256:$t, VR256:$f, imm:$cond, 811 EFLAGS)))]>; 812 def CMOV_V4F64 : I<0, Pseudo, 813 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond), 814 "#CMOV_V4F64 PSEUDO!", 815 [(set VR256:$dst, 816 (v4f64 (X86cmov VR256:$t, VR256:$f, imm:$cond, 817 EFLAGS)))]>; 818 def CMOV_V4I64 : I<0, Pseudo, 819 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond), 820 "#CMOV_V4I64 PSEUDO!", 821 [(set VR256:$dst, 822 (v4i64 (X86cmov VR256:$t, VR256:$f, imm:$cond, 823 EFLAGS)))]>; 824} 825 826 827//===----------------------------------------------------------------------===// 828// DAG Pattern Matching Rules 829//===----------------------------------------------------------------------===// 830 831// ConstantPool GlobalAddress, ExternalSymbol, and JumpTable 832def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>; 833def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>; 834def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>; 835def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>; 836def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>; 837def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>; 838 839def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)), 840 (ADD32ri GR32:$src1, tconstpool:$src2)>; 841def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)), 842 (ADD32ri GR32:$src1, tjumptable:$src2)>; 843def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)), 844 (ADD32ri GR32:$src1, tglobaladdr:$src2)>; 845def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)), 846 (ADD32ri GR32:$src1, texternalsym:$src2)>; 847def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)), 848 (ADD32ri GR32:$src1, tblockaddress:$src2)>; 849 850def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst), 851 (MOV32mi addr:$dst, tglobaladdr:$src)>; 852def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst), 853 (MOV32mi addr:$dst, texternalsym:$src)>; 854def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst), 855 (MOV32mi addr:$dst, tblockaddress:$src)>; 856 857 858 859// ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small 860// code model mode, should use 'movabs'. FIXME: This is really a hack, the 861// 'movabs' predicate should handle this sort of thing. 862def : Pat<(i64 (X86Wrapper tconstpool :$dst)), 863 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>; 864def : Pat<(i64 (X86Wrapper tjumptable :$dst)), 865 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>; 866def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), 867 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>; 868def : Pat<(i64 (X86Wrapper texternalsym:$dst)), 869 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>; 870def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), 871 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>; 872 873// In static codegen with small code model, we can get the address of a label 874// into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of 875// the MOV64ri64i32 should accept these. 876def : Pat<(i64 (X86Wrapper tconstpool :$dst)), 877 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>; 878def : Pat<(i64 (X86Wrapper tjumptable :$dst)), 879 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>; 880def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), 881 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>; 882def : Pat<(i64 (X86Wrapper texternalsym:$dst)), 883 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>; 884def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), 885 (MOV64ri64i32 tblockaddress:$dst)>, Requires<[SmallCode]>; 886 887// In kernel code model, we can get the address of a label 888// into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of 889// the MOV64ri32 should accept these. 890def : Pat<(i64 (X86Wrapper tconstpool :$dst)), 891 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>; 892def : Pat<(i64 (X86Wrapper tjumptable :$dst)), 893 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>; 894def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), 895 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>; 896def : Pat<(i64 (X86Wrapper texternalsym:$dst)), 897 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>; 898def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), 899 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>; 900 901// If we have small model and -static mode, it is safe to store global addresses 902// directly as immediates. FIXME: This is really a hack, the 'imm' predicate 903// for MOV64mi32 should handle this sort of thing. 904def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst), 905 (MOV64mi32 addr:$dst, tconstpool:$src)>, 906 Requires<[NearData, IsStatic]>; 907def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst), 908 (MOV64mi32 addr:$dst, tjumptable:$src)>, 909 Requires<[NearData, IsStatic]>; 910def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst), 911 (MOV64mi32 addr:$dst, tglobaladdr:$src)>, 912 Requires<[NearData, IsStatic]>; 913def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst), 914 (MOV64mi32 addr:$dst, texternalsym:$src)>, 915 Requires<[NearData, IsStatic]>; 916def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst), 917 (MOV64mi32 addr:$dst, tblockaddress:$src)>, 918 Requires<[NearData, IsStatic]>; 919 920 921 922// Calls 923 924// tls has some funny stuff here... 925// This corresponds to movabs $foo@tpoff, %rax 926def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)), 927 (MOV64ri tglobaltlsaddr :$dst)>; 928// This corresponds to add $foo@tpoff, %rax 929def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)), 930 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>; 931// This corresponds to mov foo@tpoff(%rbx), %eax 932def : Pat<(load (i64 (X86Wrapper tglobaltlsaddr :$dst))), 933 (MOV64rm tglobaltlsaddr :$dst)>; 934 935 936// Direct PC relative function call for small code model. 32-bit displacement 937// sign extended to 64-bit. 938def : Pat<(X86call (i64 tglobaladdr:$dst)), 939 (CALL64pcrel32 tglobaladdr:$dst)>, Requires<[NotWin64]>; 940def : Pat<(X86call (i64 texternalsym:$dst)), 941 (CALL64pcrel32 texternalsym:$dst)>, Requires<[NotWin64]>; 942 943def : Pat<(X86call (i64 tglobaladdr:$dst)), 944 (WINCALL64pcrel32 tglobaladdr:$dst)>, Requires<[IsWin64]>; 945def : Pat<(X86call (i64 texternalsym:$dst)), 946 (WINCALL64pcrel32 texternalsym:$dst)>, Requires<[IsWin64]>; 947 948// tailcall stuff 949def : Pat<(X86tcret GR32_TC:$dst, imm:$off), 950 (TCRETURNri GR32_TC:$dst, imm:$off)>, 951 Requires<[In32BitMode]>; 952 953// FIXME: This is disabled for 32-bit PIC mode because the global base 954// register which is part of the address mode may be assigned a 955// callee-saved register. 956def : Pat<(X86tcret (load addr:$dst), imm:$off), 957 (TCRETURNmi addr:$dst, imm:$off)>, 958 Requires<[In32BitMode, IsNotPIC]>; 959 960def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off), 961 (TCRETURNdi texternalsym:$dst, imm:$off)>, 962 Requires<[In32BitMode]>; 963 964def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off), 965 (TCRETURNdi texternalsym:$dst, imm:$off)>, 966 Requires<[In32BitMode]>; 967 968def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), 969 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>, 970 Requires<[In64BitMode]>; 971 972def : Pat<(X86tcret (load addr:$dst), imm:$off), 973 (TCRETURNmi64 addr:$dst, imm:$off)>, 974 Requires<[In64BitMode]>; 975 976def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off), 977 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>, 978 Requires<[In64BitMode]>; 979 980def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off), 981 (TCRETURNdi64 texternalsym:$dst, imm:$off)>, 982 Requires<[In64BitMode]>; 983 984// Normal calls, with various flavors of addresses. 985def : Pat<(X86call (i32 tglobaladdr:$dst)), 986 (CALLpcrel32 tglobaladdr:$dst)>; 987def : Pat<(X86call (i32 texternalsym:$dst)), 988 (CALLpcrel32 texternalsym:$dst)>; 989def : Pat<(X86call (i32 imm:$dst)), 990 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>; 991 992// Comparisons. 993 994// TEST R,R is smaller than CMP R,0 995def : Pat<(X86cmp GR8:$src1, 0), 996 (TEST8rr GR8:$src1, GR8:$src1)>; 997def : Pat<(X86cmp GR16:$src1, 0), 998 (TEST16rr GR16:$src1, GR16:$src1)>; 999def : Pat<(X86cmp GR32:$src1, 0), 1000 (TEST32rr GR32:$src1, GR32:$src1)>; 1001def : Pat<(X86cmp GR64:$src1, 0), 1002 (TEST64rr GR64:$src1, GR64:$src1)>; 1003 1004// Conditional moves with folded loads with operands swapped and conditions 1005// inverted. 1006multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32, 1007 Instruction Inst64> { 1008 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS), 1009 (Inst16 GR16:$src2, addr:$src1)>; 1010 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS), 1011 (Inst32 GR32:$src2, addr:$src1)>; 1012 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS), 1013 (Inst64 GR64:$src2, addr:$src1)>; 1014} 1015 1016defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>; 1017defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>; 1018defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>; 1019defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>; 1020defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>; 1021defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>; 1022defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>; 1023defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>; 1024defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>; 1025defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>; 1026defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>; 1027defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>; 1028defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>; 1029defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>; 1030defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>; 1031defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>; 1032 1033// zextload bool -> zextload byte 1034def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>; 1035def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; 1036def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; 1037def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>; 1038 1039// extload bool -> extload byte 1040// When extloading from 16-bit and smaller memory locations into 64-bit 1041// registers, use zero-extending loads so that the entire 64-bit register is 1042// defined, avoiding partial-register updates. 1043 1044def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>; 1045def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; 1046def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; 1047def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>; 1048def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>; 1049def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>; 1050 1051def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>; 1052def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>; 1053def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>; 1054// For other extloads, use subregs, since the high contents of the register are 1055// defined after an extload. 1056def : Pat<(extloadi64i32 addr:$src), 1057 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), 1058 sub_32bit)>; 1059 1060// anyext. Define these to do an explicit zero-extend to 1061// avoid partial-register updates. 1062def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG 1063 (MOVZX32rr8 GR8 :$src), sub_16bit)>; 1064def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>; 1065 1066// Except for i16 -> i32 since isel expect i16 ops to be promoted to i32. 1067def : Pat<(i32 (anyext GR16:$src)), 1068 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>; 1069 1070def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>; 1071def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>; 1072def : Pat<(i64 (anyext GR32:$src)), 1073 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; 1074 1075 1076// Any instruction that defines a 32-bit result leaves the high half of the 1077// register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may 1078// be copying from a truncate. And x86's cmov doesn't do anything if the 1079// condition is false. But any other 32-bit operation will zero-extend 1080// up to 64 bits. 1081def def32 : PatLeaf<(i32 GR32:$src), [{ 1082 return N->getOpcode() != ISD::TRUNCATE && 1083 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG && 1084 N->getOpcode() != ISD::CopyFromReg && 1085 N->getOpcode() != X86ISD::CMOV; 1086}]>; 1087 1088// In the case of a 32-bit def that is known to implicitly zero-extend, 1089// we can use a SUBREG_TO_REG. 1090def : Pat<(i64 (zext def32:$src)), 1091 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; 1092 1093//===----------------------------------------------------------------------===// 1094// Pattern match OR as ADD 1095//===----------------------------------------------------------------------===// 1096 1097// If safe, we prefer to pattern match OR as ADD at isel time. ADD can be 1098// 3-addressified into an LEA instruction to avoid copies. However, we also 1099// want to finally emit these instructions as an or at the end of the code 1100// generator to make the generated code easier to read. To do this, we select 1101// into "disjoint bits" pseudo ops. 1102 1103// Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero. 1104def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{ 1105 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1106 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue()); 1107 1108 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits(); 1109 APInt Mask = APInt::getAllOnesValue(BitWidth); 1110 APInt KnownZero0, KnownOne0; 1111 CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0); 1112 APInt KnownZero1, KnownOne1; 1113 CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0); 1114 return (~KnownZero0 & ~KnownZero1) == 0; 1115}]>; 1116 1117 1118// (or x1, x2) -> (add x1, x2) if two operands are known not to share bits. 1119let AddedComplexity = 5 in { // Try this before the selecting to OR 1120 1121let isConvertibleToThreeAddress = 1, 1122 Constraints = "$src1 = $dst", Defs = [EFLAGS] in { 1123let isCommutable = 1 in { 1124def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 1125 "", // orw/addw REG, REG 1126 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>; 1127def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 1128 "", // orl/addl REG, REG 1129 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>; 1130def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 1131 "", // orq/addq REG, REG 1132 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>; 1133} // isCommutable 1134 1135// NOTE: These are order specific, we want the ri8 forms to be listed 1136// first so that they are slightly preferred to the ri forms. 1137 1138def ADD16ri8_DB : I<0, Pseudo, 1139 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), 1140 "", // orw/addw REG, imm8 1141 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>; 1142def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), 1143 "", // orw/addw REG, imm 1144 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>; 1145 1146def ADD32ri8_DB : I<0, Pseudo, 1147 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), 1148 "", // orl/addl REG, imm8 1149 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>; 1150def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 1151 "", // orl/addl REG, imm 1152 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>; 1153 1154 1155def ADD64ri8_DB : I<0, Pseudo, 1156 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), 1157 "", // orq/addq REG, imm8 1158 [(set GR64:$dst, (or_is_add GR64:$src1, 1159 i64immSExt8:$src2))]>; 1160def ADD64ri32_DB : I<0, Pseudo, 1161 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), 1162 "", // orq/addq REG, imm 1163 [(set GR64:$dst, (or_is_add GR64:$src1, 1164 i64immSExt32:$src2))]>; 1165} 1166} // AddedComplexity 1167 1168 1169//===----------------------------------------------------------------------===// 1170// Some peepholes 1171//===----------------------------------------------------------------------===// 1172 1173// Odd encoding trick: -128 fits into an 8-bit immediate field while 1174// +128 doesn't, so in this special case use a sub instead of an add. 1175def : Pat<(add GR16:$src1, 128), 1176 (SUB16ri8 GR16:$src1, -128)>; 1177def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst), 1178 (SUB16mi8 addr:$dst, -128)>; 1179 1180def : Pat<(add GR32:$src1, 128), 1181 (SUB32ri8 GR32:$src1, -128)>; 1182def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst), 1183 (SUB32mi8 addr:$dst, -128)>; 1184 1185def : Pat<(add GR64:$src1, 128), 1186 (SUB64ri8 GR64:$src1, -128)>; 1187def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst), 1188 (SUB64mi8 addr:$dst, -128)>; 1189 1190// The same trick applies for 32-bit immediate fields in 64-bit 1191// instructions. 1192def : Pat<(add GR64:$src1, 0x0000000080000000), 1193 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>; 1194def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst), 1195 (SUB64mi32 addr:$dst, 0xffffffff80000000)>; 1196 1197// To avoid needing to materialize an immediate in a register, use a 32-bit and 1198// with implicit zero-extension instead of a 64-bit and if the immediate has at 1199// least 32 bits of leading zeros. If in addition the last 32 bits can be 1200// represented with a sign extension of a 8 bit constant, use that. 1201 1202def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm), 1203 (SUBREG_TO_REG 1204 (i64 0), 1205 (AND32ri8 1206 (EXTRACT_SUBREG GR64:$src, sub_32bit), 1207 (i32 (GetLo8XForm imm:$imm))), 1208 sub_32bit)>; 1209 1210def : Pat<(and GR64:$src, i64immZExt32:$imm), 1211 (SUBREG_TO_REG 1212 (i64 0), 1213 (AND32ri 1214 (EXTRACT_SUBREG GR64:$src, sub_32bit), 1215 (i32 (GetLo32XForm imm:$imm))), 1216 sub_32bit)>; 1217 1218 1219// r & (2^16-1) ==> movz 1220def : Pat<(and GR32:$src1, 0xffff), 1221 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>; 1222// r & (2^8-1) ==> movz 1223def : Pat<(and GR32:$src1, 0xff), 1224 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1, 1225 GR32_ABCD)), 1226 sub_8bit))>, 1227 Requires<[In32BitMode]>; 1228// r & (2^8-1) ==> movz 1229def : Pat<(and GR16:$src1, 0xff), 1230 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG 1231 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)), 1232 sub_16bit)>, 1233 Requires<[In32BitMode]>; 1234 1235// r & (2^32-1) ==> movz 1236def : Pat<(and GR64:$src, 0x00000000FFFFFFFF), 1237 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>; 1238// r & (2^16-1) ==> movz 1239def : Pat<(and GR64:$src, 0xffff), 1240 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit)))>; 1241// r & (2^8-1) ==> movz 1242def : Pat<(and GR64:$src, 0xff), 1243 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit)))>; 1244// r & (2^8-1) ==> movz 1245def : Pat<(and GR32:$src1, 0xff), 1246 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>, 1247 Requires<[In64BitMode]>; 1248// r & (2^8-1) ==> movz 1249def : Pat<(and GR16:$src1, 0xff), 1250 (EXTRACT_SUBREG (MOVZX32rr8 (i8 1251 (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>, 1252 Requires<[In64BitMode]>; 1253 1254 1255// sext_inreg patterns 1256def : Pat<(sext_inreg GR32:$src, i16), 1257 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>; 1258def : Pat<(sext_inreg GR32:$src, i8), 1259 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1260 GR32_ABCD)), 1261 sub_8bit))>, 1262 Requires<[In32BitMode]>; 1263 1264def : Pat<(sext_inreg GR16:$src, i8), 1265 (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG 1266 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))), 1267 sub_16bit)>, 1268 Requires<[In32BitMode]>; 1269 1270def : Pat<(sext_inreg GR64:$src, i32), 1271 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>; 1272def : Pat<(sext_inreg GR64:$src, i16), 1273 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>; 1274def : Pat<(sext_inreg GR64:$src, i8), 1275 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>; 1276def : Pat<(sext_inreg GR32:$src, i8), 1277 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>, 1278 Requires<[In64BitMode]>; 1279def : Pat<(sext_inreg GR16:$src, i8), 1280 (EXTRACT_SUBREG (MOVSX32rr8 1281 (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>, 1282 Requires<[In64BitMode]>; 1283 1284// sext, sext_load, zext, zext_load 1285def: Pat<(i16 (sext GR8:$src)), 1286 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>; 1287def: Pat<(sextloadi16i8 addr:$src), 1288 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>; 1289def: Pat<(i16 (zext GR8:$src)), 1290 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>; 1291def: Pat<(zextloadi16i8 addr:$src), 1292 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1293 1294// trunc patterns 1295def : Pat<(i16 (trunc GR32:$src)), 1296 (EXTRACT_SUBREG GR32:$src, sub_16bit)>; 1297def : Pat<(i8 (trunc GR32:$src)), 1298 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1299 sub_8bit)>, 1300 Requires<[In32BitMode]>; 1301def : Pat<(i8 (trunc GR16:$src)), 1302 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1303 sub_8bit)>, 1304 Requires<[In32BitMode]>; 1305def : Pat<(i32 (trunc GR64:$src)), 1306 (EXTRACT_SUBREG GR64:$src, sub_32bit)>; 1307def : Pat<(i16 (trunc GR64:$src)), 1308 (EXTRACT_SUBREG GR64:$src, sub_16bit)>; 1309def : Pat<(i8 (trunc GR64:$src)), 1310 (EXTRACT_SUBREG GR64:$src, sub_8bit)>; 1311def : Pat<(i8 (trunc GR32:$src)), 1312 (EXTRACT_SUBREG GR32:$src, sub_8bit)>, 1313 Requires<[In64BitMode]>; 1314def : Pat<(i8 (trunc GR16:$src)), 1315 (EXTRACT_SUBREG GR16:$src, sub_8bit)>, 1316 Requires<[In64BitMode]>; 1317 1318// h-register tricks 1319def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))), 1320 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1321 sub_8bit_hi)>, 1322 Requires<[In32BitMode]>; 1323def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))), 1324 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1325 sub_8bit_hi)>, 1326 Requires<[In32BitMode]>; 1327def : Pat<(srl GR16:$src, (i8 8)), 1328 (EXTRACT_SUBREG 1329 (MOVZX32rr8 1330 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1331 sub_8bit_hi)), 1332 sub_16bit)>, 1333 Requires<[In32BitMode]>; 1334def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), 1335 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, 1336 GR16_ABCD)), 1337 sub_8bit_hi))>, 1338 Requires<[In32BitMode]>; 1339def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), 1340 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, 1341 GR16_ABCD)), 1342 sub_8bit_hi))>, 1343 Requires<[In32BitMode]>; 1344def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), 1345 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1346 GR32_ABCD)), 1347 sub_8bit_hi))>, 1348 Requires<[In32BitMode]>; 1349def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)), 1350 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1351 GR32_ABCD)), 1352 sub_8bit_hi))>, 1353 Requires<[In32BitMode]>; 1354 1355// h-register tricks. 1356// For now, be conservative on x86-64 and use an h-register extract only if the 1357// value is immediately zero-extended or stored, which are somewhat common 1358// cases. This uses a bunch of code to prevent a register requiring a REX prefix 1359// from being allocated in the same instruction as the h register, as there's 1360// currently no way to describe this requirement to the register allocator. 1361 1362// h-register extract and zero-extend. 1363def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)), 1364 (SUBREG_TO_REG 1365 (i64 0), 1366 (MOVZX32_NOREXrr8 1367 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)), 1368 sub_8bit_hi)), 1369 sub_32bit)>; 1370def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), 1371 (MOVZX32_NOREXrr8 1372 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1373 sub_8bit_hi))>, 1374 Requires<[In64BitMode]>; 1375def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)), 1376 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1377 GR32_ABCD)), 1378 sub_8bit_hi))>, 1379 Requires<[In64BitMode]>; 1380def : Pat<(srl GR16:$src, (i8 8)), 1381 (EXTRACT_SUBREG 1382 (MOVZX32_NOREXrr8 1383 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1384 sub_8bit_hi)), 1385 sub_16bit)>, 1386 Requires<[In64BitMode]>; 1387def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), 1388 (MOVZX32_NOREXrr8 1389 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1390 sub_8bit_hi))>, 1391 Requires<[In64BitMode]>; 1392def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), 1393 (MOVZX32_NOREXrr8 1394 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1395 sub_8bit_hi))>, 1396 Requires<[In64BitMode]>; 1397def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))), 1398 (SUBREG_TO_REG 1399 (i64 0), 1400 (MOVZX32_NOREXrr8 1401 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1402 sub_8bit_hi)), 1403 sub_32bit)>; 1404def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))), 1405 (SUBREG_TO_REG 1406 (i64 0), 1407 (MOVZX32_NOREXrr8 1408 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1409 sub_8bit_hi)), 1410 sub_32bit)>; 1411 1412// h-register extract and store. 1413def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst), 1414 (MOV8mr_NOREX 1415 addr:$dst, 1416 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)), 1417 sub_8bit_hi))>; 1418def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst), 1419 (MOV8mr_NOREX 1420 addr:$dst, 1421 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1422 sub_8bit_hi))>, 1423 Requires<[In64BitMode]>; 1424def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst), 1425 (MOV8mr_NOREX 1426 addr:$dst, 1427 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1428 sub_8bit_hi))>, 1429 Requires<[In64BitMode]>; 1430 1431 1432// (shl x, 1) ==> (add x, x) 1433// Note that if x is undef (immediate or otherwise), we could theoretically 1434// end up with the two uses of x getting different values, producing a result 1435// where the least significant bit is not 0. However, the probability of this 1436// happening is considered low enough that this is officially not a 1437// "real problem". 1438def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>; 1439def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>; 1440def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>; 1441def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>; 1442 1443// (shl x (and y, 31)) ==> (shl x, y) 1444def : Pat<(shl GR8:$src1, (and CL, 31)), 1445 (SHL8rCL GR8:$src1)>; 1446def : Pat<(shl GR16:$src1, (and CL, 31)), 1447 (SHL16rCL GR16:$src1)>; 1448def : Pat<(shl GR32:$src1, (and CL, 31)), 1449 (SHL32rCL GR32:$src1)>; 1450def : Pat<(store (shl (loadi8 addr:$dst), (and CL, 31)), addr:$dst), 1451 (SHL8mCL addr:$dst)>; 1452def : Pat<(store (shl (loadi16 addr:$dst), (and CL, 31)), addr:$dst), 1453 (SHL16mCL addr:$dst)>; 1454def : Pat<(store (shl (loadi32 addr:$dst), (and CL, 31)), addr:$dst), 1455 (SHL32mCL addr:$dst)>; 1456 1457def : Pat<(srl GR8:$src1, (and CL, 31)), 1458 (SHR8rCL GR8:$src1)>; 1459def : Pat<(srl GR16:$src1, (and CL, 31)), 1460 (SHR16rCL GR16:$src1)>; 1461def : Pat<(srl GR32:$src1, (and CL, 31)), 1462 (SHR32rCL GR32:$src1)>; 1463def : Pat<(store (srl (loadi8 addr:$dst), (and CL, 31)), addr:$dst), 1464 (SHR8mCL addr:$dst)>; 1465def : Pat<(store (srl (loadi16 addr:$dst), (and CL, 31)), addr:$dst), 1466 (SHR16mCL addr:$dst)>; 1467def : Pat<(store (srl (loadi32 addr:$dst), (and CL, 31)), addr:$dst), 1468 (SHR32mCL addr:$dst)>; 1469 1470def : Pat<(sra GR8:$src1, (and CL, 31)), 1471 (SAR8rCL GR8:$src1)>; 1472def : Pat<(sra GR16:$src1, (and CL, 31)), 1473 (SAR16rCL GR16:$src1)>; 1474def : Pat<(sra GR32:$src1, (and CL, 31)), 1475 (SAR32rCL GR32:$src1)>; 1476def : Pat<(store (sra (loadi8 addr:$dst), (and CL, 31)), addr:$dst), 1477 (SAR8mCL addr:$dst)>; 1478def : Pat<(store (sra (loadi16 addr:$dst), (and CL, 31)), addr:$dst), 1479 (SAR16mCL addr:$dst)>; 1480def : Pat<(store (sra (loadi32 addr:$dst), (and CL, 31)), addr:$dst), 1481 (SAR32mCL addr:$dst)>; 1482 1483// (shl x (and y, 63)) ==> (shl x, y) 1484def : Pat<(shl GR64:$src1, (and CL, 63)), 1485 (SHL64rCL GR64:$src1)>; 1486def : Pat<(store (shl (loadi64 addr:$dst), (and CL, 63)), addr:$dst), 1487 (SHL64mCL addr:$dst)>; 1488 1489def : Pat<(srl GR64:$src1, (and CL, 63)), 1490 (SHR64rCL GR64:$src1)>; 1491def : Pat<(store (srl (loadi64 addr:$dst), (and CL, 63)), addr:$dst), 1492 (SHR64mCL addr:$dst)>; 1493 1494def : Pat<(sra GR64:$src1, (and CL, 63)), 1495 (SAR64rCL GR64:$src1)>; 1496def : Pat<(store (sra (loadi64 addr:$dst), (and CL, 63)), addr:$dst), 1497 (SAR64mCL addr:$dst)>; 1498 1499 1500// (anyext (setcc_carry)) -> (setcc_carry) 1501def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 1502 (SETB_C16r)>; 1503def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 1504 (SETB_C32r)>; 1505def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))), 1506 (SETB_C32r)>; 1507 1508 1509 1510 1511//===----------------------------------------------------------------------===// 1512// EFLAGS-defining Patterns 1513//===----------------------------------------------------------------------===// 1514 1515// add reg, reg 1516def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>; 1517def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>; 1518def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>; 1519 1520// add reg, mem 1521def : Pat<(add GR8:$src1, (loadi8 addr:$src2)), 1522 (ADD8rm GR8:$src1, addr:$src2)>; 1523def : Pat<(add GR16:$src1, (loadi16 addr:$src2)), 1524 (ADD16rm GR16:$src1, addr:$src2)>; 1525def : Pat<(add GR32:$src1, (loadi32 addr:$src2)), 1526 (ADD32rm GR32:$src1, addr:$src2)>; 1527 1528// add reg, imm 1529def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>; 1530def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>; 1531def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>; 1532def : Pat<(add GR16:$src1, i16immSExt8:$src2), 1533 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>; 1534def : Pat<(add GR32:$src1, i32immSExt8:$src2), 1535 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>; 1536 1537// sub reg, reg 1538def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>; 1539def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>; 1540def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>; 1541 1542// sub reg, mem 1543def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)), 1544 (SUB8rm GR8:$src1, addr:$src2)>; 1545def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)), 1546 (SUB16rm GR16:$src1, addr:$src2)>; 1547def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)), 1548 (SUB32rm GR32:$src1, addr:$src2)>; 1549 1550// sub reg, imm 1551def : Pat<(sub GR8:$src1, imm:$src2), 1552 (SUB8ri GR8:$src1, imm:$src2)>; 1553def : Pat<(sub GR16:$src1, imm:$src2), 1554 (SUB16ri GR16:$src1, imm:$src2)>; 1555def : Pat<(sub GR32:$src1, imm:$src2), 1556 (SUB32ri GR32:$src1, imm:$src2)>; 1557def : Pat<(sub GR16:$src1, i16immSExt8:$src2), 1558 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>; 1559def : Pat<(sub GR32:$src1, i32immSExt8:$src2), 1560 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>; 1561 1562// mul reg, reg 1563def : Pat<(mul GR16:$src1, GR16:$src2), 1564 (IMUL16rr GR16:$src1, GR16:$src2)>; 1565def : Pat<(mul GR32:$src1, GR32:$src2), 1566 (IMUL32rr GR32:$src1, GR32:$src2)>; 1567 1568// mul reg, mem 1569def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)), 1570 (IMUL16rm GR16:$src1, addr:$src2)>; 1571def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)), 1572 (IMUL32rm GR32:$src1, addr:$src2)>; 1573 1574// mul reg, imm 1575def : Pat<(mul GR16:$src1, imm:$src2), 1576 (IMUL16rri GR16:$src1, imm:$src2)>; 1577def : Pat<(mul GR32:$src1, imm:$src2), 1578 (IMUL32rri GR32:$src1, imm:$src2)>; 1579def : Pat<(mul GR16:$src1, i16immSExt8:$src2), 1580 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>; 1581def : Pat<(mul GR32:$src1, i32immSExt8:$src2), 1582 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>; 1583 1584// reg = mul mem, imm 1585def : Pat<(mul (loadi16 addr:$src1), imm:$src2), 1586 (IMUL16rmi addr:$src1, imm:$src2)>; 1587def : Pat<(mul (loadi32 addr:$src1), imm:$src2), 1588 (IMUL32rmi addr:$src1, imm:$src2)>; 1589def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2), 1590 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>; 1591def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2), 1592 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>; 1593 1594// Patterns for nodes that do not produce flags, for instructions that do. 1595 1596// addition 1597def : Pat<(add GR64:$src1, GR64:$src2), 1598 (ADD64rr GR64:$src1, GR64:$src2)>; 1599def : Pat<(add GR64:$src1, i64immSExt8:$src2), 1600 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>; 1601def : Pat<(add GR64:$src1, i64immSExt32:$src2), 1602 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>; 1603def : Pat<(add GR64:$src1, (loadi64 addr:$src2)), 1604 (ADD64rm GR64:$src1, addr:$src2)>; 1605 1606// subtraction 1607def : Pat<(sub GR64:$src1, GR64:$src2), 1608 (SUB64rr GR64:$src1, GR64:$src2)>; 1609def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)), 1610 (SUB64rm GR64:$src1, addr:$src2)>; 1611def : Pat<(sub GR64:$src1, i64immSExt8:$src2), 1612 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>; 1613def : Pat<(sub GR64:$src1, i64immSExt32:$src2), 1614 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>; 1615 1616// Multiply 1617def : Pat<(mul GR64:$src1, GR64:$src2), 1618 (IMUL64rr GR64:$src1, GR64:$src2)>; 1619def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)), 1620 (IMUL64rm GR64:$src1, addr:$src2)>; 1621def : Pat<(mul GR64:$src1, i64immSExt8:$src2), 1622 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>; 1623def : Pat<(mul GR64:$src1, i64immSExt32:$src2), 1624 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>; 1625def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2), 1626 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>; 1627def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2), 1628 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>; 1629 1630// Increment reg. 1631def : Pat<(add GR8 :$src, 1), (INC8r GR8 :$src)>; 1632def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>, Requires<[In32BitMode]>; 1633def : Pat<(add GR16:$src, 1), (INC64_16r GR16:$src)>, Requires<[In64BitMode]>; 1634def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>, Requires<[In32BitMode]>; 1635def : Pat<(add GR32:$src, 1), (INC64_32r GR32:$src)>, Requires<[In64BitMode]>; 1636def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>; 1637 1638// Decrement reg. 1639def : Pat<(add GR8 :$src, -1), (DEC8r GR8 :$src)>; 1640def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>, Requires<[In32BitMode]>; 1641def : Pat<(add GR16:$src, -1), (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>; 1642def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>, Requires<[In32BitMode]>; 1643def : Pat<(add GR32:$src, -1), (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>; 1644def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>; 1645 1646// or reg/reg. 1647def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>; 1648def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>; 1649def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>; 1650def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>; 1651 1652// or reg/mem 1653def : Pat<(or GR8:$src1, (loadi8 addr:$src2)), 1654 (OR8rm GR8:$src1, addr:$src2)>; 1655def : Pat<(or GR16:$src1, (loadi16 addr:$src2)), 1656 (OR16rm GR16:$src1, addr:$src2)>; 1657def : Pat<(or GR32:$src1, (loadi32 addr:$src2)), 1658 (OR32rm GR32:$src1, addr:$src2)>; 1659def : Pat<(or GR64:$src1, (loadi64 addr:$src2)), 1660 (OR64rm GR64:$src1, addr:$src2)>; 1661 1662// or reg/imm 1663def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>; 1664def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>; 1665def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>; 1666def : Pat<(or GR16:$src1, i16immSExt8:$src2), 1667 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>; 1668def : Pat<(or GR32:$src1, i32immSExt8:$src2), 1669 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>; 1670def : Pat<(or GR64:$src1, i64immSExt8:$src2), 1671 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>; 1672def : Pat<(or GR64:$src1, i64immSExt32:$src2), 1673 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>; 1674 1675// xor reg/reg 1676def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>; 1677def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>; 1678def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>; 1679def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>; 1680 1681// xor reg/mem 1682def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)), 1683 (XOR8rm GR8:$src1, addr:$src2)>; 1684def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)), 1685 (XOR16rm GR16:$src1, addr:$src2)>; 1686def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)), 1687 (XOR32rm GR32:$src1, addr:$src2)>; 1688def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)), 1689 (XOR64rm GR64:$src1, addr:$src2)>; 1690 1691// xor reg/imm 1692def : Pat<(xor GR8:$src1, imm:$src2), 1693 (XOR8ri GR8:$src1, imm:$src2)>; 1694def : Pat<(xor GR16:$src1, imm:$src2), 1695 (XOR16ri GR16:$src1, imm:$src2)>; 1696def : Pat<(xor GR32:$src1, imm:$src2), 1697 (XOR32ri GR32:$src1, imm:$src2)>; 1698def : Pat<(xor GR16:$src1, i16immSExt8:$src2), 1699 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>; 1700def : Pat<(xor GR32:$src1, i32immSExt8:$src2), 1701 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>; 1702def : Pat<(xor GR64:$src1, i64immSExt8:$src2), 1703 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>; 1704def : Pat<(xor GR64:$src1, i64immSExt32:$src2), 1705 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>; 1706 1707// and reg/reg 1708def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>; 1709def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>; 1710def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>; 1711def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>; 1712 1713// and reg/mem 1714def : Pat<(and GR8:$src1, (loadi8 addr:$src2)), 1715 (AND8rm GR8:$src1, addr:$src2)>; 1716def : Pat<(and GR16:$src1, (loadi16 addr:$src2)), 1717 (AND16rm GR16:$src1, addr:$src2)>; 1718def : Pat<(and GR32:$src1, (loadi32 addr:$src2)), 1719 (AND32rm GR32:$src1, addr:$src2)>; 1720def : Pat<(and GR64:$src1, (loadi64 addr:$src2)), 1721 (AND64rm GR64:$src1, addr:$src2)>; 1722 1723// and reg/imm 1724def : Pat<(and GR8:$src1, imm:$src2), 1725 (AND8ri GR8:$src1, imm:$src2)>; 1726def : Pat<(and GR16:$src1, imm:$src2), 1727 (AND16ri GR16:$src1, imm:$src2)>; 1728def : Pat<(and GR32:$src1, imm:$src2), 1729 (AND32ri GR32:$src1, imm:$src2)>; 1730def : Pat<(and GR16:$src1, i16immSExt8:$src2), 1731 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>; 1732def : Pat<(and GR32:$src1, i32immSExt8:$src2), 1733 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>; 1734def : Pat<(and GR64:$src1, i64immSExt8:$src2), 1735 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>; 1736def : Pat<(and GR64:$src1, i64immSExt32:$src2), 1737 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>; 1738