X86InstrCompiler.td revision 218893
1//===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the various pseudo instructions used by the compiler, 11// as well as Pat patterns used during instruction selection. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// Pattern Matching Support 17 18def GetLo32XForm : SDNodeXForm<imm, [{ 19 // Transformation function: get the low 32 bits. 20 return getI32Imm((unsigned)N->getZExtValue()); 21}]>; 22 23def GetLo8XForm : SDNodeXForm<imm, [{ 24 // Transformation function: get the low 8 bits. 25 return getI8Imm((uint8_t)N->getZExtValue()); 26}]>; 27 28 29//===----------------------------------------------------------------------===// 30// Random Pseudo Instructions. 31 32// PIC base construction. This expands to code that looks like this: 33// call $next_inst 34// popl %destreg" 35let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in 36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label), 37 "", []>; 38 39 40// ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into 41// a stack adjustment and the codegen must know that they may modify the stack 42// pointer before prolog-epilog rewriting occurs. 43// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 44// sub / add which can clobber EFLAGS. 45let Defs = [ESP, EFLAGS], Uses = [ESP] in { 46def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt), 47 "#ADJCALLSTACKDOWN", 48 [(X86callseq_start timm:$amt)]>, 49 Requires<[In32BitMode]>; 50def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 51 "#ADJCALLSTACKUP", 52 [(X86callseq_end timm:$amt1, timm:$amt2)]>, 53 Requires<[In32BitMode]>; 54} 55 56// ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into 57// a stack adjustment and the codegen must know that they may modify the stack 58// pointer before prolog-epilog rewriting occurs. 59// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 60// sub / add which can clobber EFLAGS. 61let Defs = [RSP, EFLAGS], Uses = [RSP] in { 62def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt), 63 "#ADJCALLSTACKDOWN", 64 [(X86callseq_start timm:$amt)]>, 65 Requires<[In64BitMode]>; 66def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 67 "#ADJCALLSTACKUP", 68 [(X86callseq_end timm:$amt1, timm:$amt2)]>, 69 Requires<[In64BitMode]>; 70} 71 72 73 74// x86-64 va_start lowering magic. 75let usesCustomInserter = 1 in { 76def VASTART_SAVE_XMM_REGS : I<0, Pseudo, 77 (outs), 78 (ins GR8:$al, 79 i64imm:$regsavefi, i64imm:$offset, 80 variable_ops), 81 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset", 82 [(X86vastart_save_xmm_regs GR8:$al, 83 imm:$regsavefi, 84 imm:$offset)]>; 85 86// The VAARG_64 pseudo-instruction takes the address of the va_list, 87// and places the address of the next argument into a register. 88let Defs = [EFLAGS] in 89def VAARG_64 : I<0, Pseudo, 90 (outs GR64:$dst), 91 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align), 92 "#VAARG_64 $dst, $ap, $size, $mode, $align", 93 [(set GR64:$dst, 94 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)), 95 (implicit EFLAGS)]>; 96 97// Dynamic stack allocation yields a _chkstk or _alloca call for all Windows 98// targets. These calls are needed to probe the stack when allocating more than 99// 4k bytes in one go. Touching the stack at 4K increments is necessary to 100// ensure that the guard pages used by the OS virtual memory manager are 101// allocated in correct sequence. 102// The main point of having separate instruction are extra unmodelled effects 103// (compared to ordinary calls) like stack pointer change. 104 105let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 106 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins), 107 "# dynamic stack allocation", 108 [(X86WinAlloca)]>; 109} 110 111 112 113//===----------------------------------------------------------------------===// 114// EH Pseudo Instructions 115// 116let isTerminator = 1, isReturn = 1, isBarrier = 1, 117 hasCtrlDep = 1, isCodeGenOnly = 1 in { 118def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr), 119 "ret\t#eh_return, addr: $addr", 120 [(X86ehret GR32:$addr)]>; 121 122} 123 124let isTerminator = 1, isReturn = 1, isBarrier = 1, 125 hasCtrlDep = 1, isCodeGenOnly = 1 in { 126def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr), 127 "ret\t#eh_return, addr: $addr", 128 [(X86ehret GR64:$addr)]>; 129 130} 131 132//===----------------------------------------------------------------------===// 133// Alias Instructions 134//===----------------------------------------------------------------------===// 135 136// Alias instructions that map movr0 to xor. 137// FIXME: remove when we can teach regalloc that xor reg, reg is ok. 138// FIXME: Set encoding to pseudo. 139let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1, 140 isCodeGenOnly = 1 in { 141def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "", 142 [(set GR8:$dst, 0)]>; 143 144// We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller 145// encoding and avoids a partial-register update sometimes, but doing so 146// at isel time interferes with rematerialization in the current register 147// allocator. For now, this is rewritten when the instruction is lowered 148// to an MCInst. 149def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins), 150 "", 151 [(set GR16:$dst, 0)]>, OpSize; 152 153// FIXME: Set encoding to pseudo. 154def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "", 155 [(set GR32:$dst, 0)]>; 156} 157 158// We want to rewrite MOV64r0 in terms of MOV32r0, because it's sometimes a 159// smaller encoding, but doing so at isel time interferes with rematerialization 160// in the current register allocator. For now, this is rewritten when the 161// instruction is lowered to an MCInst. 162// FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove 163// when we have a better way to specify isel priority. 164let Defs = [EFLAGS], isCodeGenOnly=1, 165 AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in 166def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins), "", 167 [(set GR64:$dst, 0)]>; 168 169// Materialize i64 constant where top 32-bits are zero. This could theoretically 170// use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however 171// that would make it more difficult to rematerialize. 172let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1, 173 isCodeGenOnly = 1 in 174def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src), 175 "", [(set GR64:$dst, i64immZExt32:$src)]>; 176 177// Use sbb to materialize carry bit. 178let Uses = [EFLAGS], Defs = [EFLAGS], isCodeGenOnly = 1 in { 179// FIXME: These are pseudo ops that should be replaced with Pat<> patterns. 180// However, Pat<> can't replicate the destination reg into the inputs of the 181// result. 182// FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces 183// X86CodeEmitter. 184def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "", 185 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 186def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "", 187 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>, 188 OpSize; 189def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "", 190 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 191def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins), "", 192 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 193} // isCodeGenOnly 194 195 196def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 197 (SETB_C16r)>; 198def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 199 (SETB_C32r)>; 200def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 201 (SETB_C64r)>; 202 203def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 204 (SETB_C16r)>; 205def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 206 (SETB_C32r)>; 207def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 208 (SETB_C64r)>; 209 210// We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and 211// will be eliminated and that the sbb can be extended up to a wider type. When 212// this happens, it is great. However, if we are left with an 8-bit sbb and an 213// and, we might as well just match it as a setb. 214def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), 215 (SETBr)>; 216 217//===----------------------------------------------------------------------===// 218// String Pseudo Instructions 219// 220let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in { 221def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}", 222 [(X86rep_movs i8)]>, REP; 223def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}", 224 [(X86rep_movs i16)]>, REP, OpSize; 225def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}", 226 [(X86rep_movs i32)]>, REP; 227} 228 229let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in 230def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}", 231 [(X86rep_movs i64)]>, REP; 232 233 234// FIXME: Should use "(X86rep_stos AL)" as the pattern. 235let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in 236def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}", 237 [(X86rep_stos i8)]>, REP; 238let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in 239def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}", 240 [(X86rep_stos i16)]>, REP, OpSize; 241let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in 242def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}", 243 [(X86rep_stos i32)]>, REP; 244 245let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI], isCodeGenOnly = 1 in 246def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}", 247 [(X86rep_stos i64)]>, REP; 248 249 250//===----------------------------------------------------------------------===// 251// Thread Local Storage Instructions 252// 253 254// ELF TLS Support 255// All calls clobber the non-callee saved registers. ESP is marked as 256// a use to prevent stack-pointer assignments that appear immediately 257// before calls from potentially appearing dead. 258let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, 259 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 260 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 261 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], 262 Uses = [ESP] in 263def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 264 "# TLS_addr32", 265 [(X86tlsaddr tls32addr:$sym)]>, 266 Requires<[In32BitMode]>; 267 268// All calls clobber the non-callee saved registers. RSP is marked as 269// a use to prevent stack-pointer assignments that appear immediately 270// before calls from potentially appearing dead. 271let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, 272 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1, 273 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 274 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 275 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], 276 Uses = [RSP] in 277def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 278 "# TLS_addr64", 279 [(X86tlsaddr tls64addr:$sym)]>, 280 Requires<[In64BitMode]>; 281 282// Darwin TLS Support 283// For i386, the address of the thunk is passed on the stack, on return the 284// address of the variable is in %eax. %ecx is trashed during the function 285// call. All other registers are preserved. 286let Defs = [EAX, ECX, EFLAGS], 287 Uses = [ESP], 288 usesCustomInserter = 1 in 289def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 290 "# TLSCall_32", 291 [(X86TLSCall addr:$sym)]>, 292 Requires<[In32BitMode]>; 293 294// For x86_64, the address of the thunk is passed in %rdi, on return 295// the address of the variable is in %rax. All other registers are preserved. 296let Defs = [RAX, EFLAGS], 297 Uses = [RSP, RDI], 298 usesCustomInserter = 1 in 299def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 300 "# TLSCall_64", 301 [(X86TLSCall addr:$sym)]>, 302 Requires<[In64BitMode]>; 303 304 305//===----------------------------------------------------------------------===// 306// Conditional Move Pseudo Instructions 307 308let Constraints = "$src1 = $dst" in { 309 310// Conditional moves 311let Uses = [EFLAGS] in { 312 313// X86 doesn't have 8-bit conditional moves. Use a customInserter to 314// emit control flow. An alternative to this is to mark i8 SELECT as Promote, 315// however that requires promoting the operands, and can induce additional 316// i8 register pressure. Note that CMOV_GR8 is conservatively considered to 317// clobber EFLAGS, because if one of the operands is zero, the expansion 318// could involve an xor. 319let usesCustomInserter = 1, Constraints = "", Defs = [EFLAGS] in { 320def CMOV_GR8 : I<0, Pseudo, 321 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond), 322 "#CMOV_GR8 PSEUDO!", 323 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2, 324 imm:$cond, EFLAGS))]>; 325 326let Predicates = [NoCMov] in { 327def CMOV_GR32 : I<0, Pseudo, 328 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond), 329 "#CMOV_GR32* PSEUDO!", 330 [(set GR32:$dst, 331 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>; 332def CMOV_GR16 : I<0, Pseudo, 333 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond), 334 "#CMOV_GR16* PSEUDO!", 335 [(set GR16:$dst, 336 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>; 337def CMOV_RFP32 : I<0, Pseudo, 338 (outs RFP32:$dst), 339 (ins RFP32:$src1, RFP32:$src2, i8imm:$cond), 340 "#CMOV_RFP32 PSEUDO!", 341 [(set RFP32:$dst, 342 (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond, 343 EFLAGS))]>; 344def CMOV_RFP64 : I<0, Pseudo, 345 (outs RFP64:$dst), 346 (ins RFP64:$src1, RFP64:$src2, i8imm:$cond), 347 "#CMOV_RFP64 PSEUDO!", 348 [(set RFP64:$dst, 349 (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond, 350 EFLAGS))]>; 351def CMOV_RFP80 : I<0, Pseudo, 352 (outs RFP80:$dst), 353 (ins RFP80:$src1, RFP80:$src2, i8imm:$cond), 354 "#CMOV_RFP80 PSEUDO!", 355 [(set RFP80:$dst, 356 (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond, 357 EFLAGS))]>; 358} // Predicates = [NoCMov] 359} // UsesCustomInserter = 1, Constraints = "", Defs = [EFLAGS] 360} // Uses = [EFLAGS] 361 362} // Constraints = "$src1 = $dst" in 363 364 365//===----------------------------------------------------------------------===// 366// Atomic Instruction Pseudo Instructions 367//===----------------------------------------------------------------------===// 368 369// Atomic exchange, and, or, xor 370let Constraints = "$val = $dst", Defs = [EFLAGS], 371 usesCustomInserter = 1 in { 372 373def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val), 374 "#ATOMAND8 PSEUDO!", 375 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>; 376def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val), 377 "#ATOMOR8 PSEUDO!", 378 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>; 379def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val), 380 "#ATOMXOR8 PSEUDO!", 381 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>; 382def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val), 383 "#ATOMNAND8 PSEUDO!", 384 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>; 385 386def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), 387 "#ATOMAND16 PSEUDO!", 388 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>; 389def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), 390 "#ATOMOR16 PSEUDO!", 391 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>; 392def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), 393 "#ATOMXOR16 PSEUDO!", 394 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>; 395def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), 396 "#ATOMNAND16 PSEUDO!", 397 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>; 398def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val), 399 "#ATOMMIN16 PSEUDO!", 400 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>; 401def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), 402 "#ATOMMAX16 PSEUDO!", 403 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>; 404def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), 405 "#ATOMUMIN16 PSEUDO!", 406 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>; 407def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), 408 "#ATOMUMAX16 PSEUDO!", 409 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>; 410 411 412def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), 413 "#ATOMAND32 PSEUDO!", 414 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>; 415def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), 416 "#ATOMOR32 PSEUDO!", 417 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>; 418def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), 419 "#ATOMXOR32 PSEUDO!", 420 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>; 421def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), 422 "#ATOMNAND32 PSEUDO!", 423 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>; 424def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val), 425 "#ATOMMIN32 PSEUDO!", 426 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>; 427def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), 428 "#ATOMMAX32 PSEUDO!", 429 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>; 430def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), 431 "#ATOMUMIN32 PSEUDO!", 432 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>; 433def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), 434 "#ATOMUMAX32 PSEUDO!", 435 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>; 436 437 438 439def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val), 440 "#ATOMAND64 PSEUDO!", 441 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>; 442def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val), 443 "#ATOMOR64 PSEUDO!", 444 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>; 445def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val), 446 "#ATOMXOR64 PSEUDO!", 447 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>; 448def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val), 449 "#ATOMNAND64 PSEUDO!", 450 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>; 451def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val), 452 "#ATOMMIN64 PSEUDO!", 453 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>; 454def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val), 455 "#ATOMMAX64 PSEUDO!", 456 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>; 457def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val), 458 "#ATOMUMIN64 PSEUDO!", 459 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>; 460def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val), 461 "#ATOMUMAX64 PSEUDO!", 462 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>; 463} 464 465let Constraints = "$val1 = $dst1, $val2 = $dst2", 466 Defs = [EFLAGS, EAX, EBX, ECX, EDX], 467 Uses = [EAX, EBX, ECX, EDX], 468 mayLoad = 1, mayStore = 1, 469 usesCustomInserter = 1 in { 470def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), 471 (ins i64mem:$ptr, GR32:$val1, GR32:$val2), 472 "#ATOMAND6432 PSEUDO!", []>; 473def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), 474 (ins i64mem:$ptr, GR32:$val1, GR32:$val2), 475 "#ATOMOR6432 PSEUDO!", []>; 476def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), 477 (ins i64mem:$ptr, GR32:$val1, GR32:$val2), 478 "#ATOMXOR6432 PSEUDO!", []>; 479def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), 480 (ins i64mem:$ptr, GR32:$val1, GR32:$val2), 481 "#ATOMNAND6432 PSEUDO!", []>; 482def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), 483 (ins i64mem:$ptr, GR32:$val1, GR32:$val2), 484 "#ATOMADD6432 PSEUDO!", []>; 485def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), 486 (ins i64mem:$ptr, GR32:$val1, GR32:$val2), 487 "#ATOMSUB6432 PSEUDO!", []>; 488def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), 489 (ins i64mem:$ptr, GR32:$val1, GR32:$val2), 490 "#ATOMSWAP6432 PSEUDO!", []>; 491} 492 493//===----------------------------------------------------------------------===// 494// Normal-Instructions-With-Lock-Prefix Pseudo Instructions 495//===----------------------------------------------------------------------===// 496 497// FIXME: Use normal instructions and add lock prefix dynamically. 498 499// Memory barriers 500 501// TODO: Get this to fold the constant into the instruction. 502let isCodeGenOnly = 1 in 503def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero), 504 "lock\n\t" 505 "or{l}\t{$zero, $dst|$dst, $zero}", 506 []>, Requires<[In32BitMode]>, LOCK; 507 508let hasSideEffects = 1 in 509def Int_MemBarrier : I<0, Pseudo, (outs), (ins), 510 "#MEMBARRIER", 511 [(X86MemBarrier)]>, Requires<[HasSSE2]>; 512 513// TODO: Get this to fold the constant into the instruction. 514let hasSideEffects = 1, Defs = [ESP], isCodeGenOnly = 1 in 515def Int_MemBarrierNoSSE64 : RI<0x09, MRM1r, (outs), (ins GR64:$zero), 516 "lock\n\t" 517 "or{q}\t{$zero, (%rsp)|(%rsp), $zero}", 518 [(X86MemBarrierNoSSE GR64:$zero)]>, 519 Requires<[In64BitMode]>, LOCK; 520 521 522// Optimized codegen when the non-memory output is not used. 523let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1 in { 524def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), 525 "lock\n\t" 526 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK; 527def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), 528 "lock\n\t" 529 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK; 530def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), 531 "lock\n\t" 532 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK; 533def LOCK_ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), 534 "lock\n\t" 535 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK; 536 537def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2), 538 "lock\n\t" 539 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK; 540def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2), 541 "lock\n\t" 542 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK; 543def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2), 544 "lock\n\t" 545 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK; 546def LOCK_ADD64mi32 : RIi32<0x81, MRM0m, (outs), 547 (ins i64mem:$dst, i64i32imm :$src2), 548 "lock\n\t" 549 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK; 550 551def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2), 552 "lock\n\t" 553 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK; 554def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2), 555 "lock\n\t" 556 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK; 557def LOCK_ADD64mi8 : RIi8<0x83, MRM0m, (outs), 558 (ins i64mem:$dst, i64i8imm :$src2), 559 "lock\n\t" 560 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK; 561 562def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2), 563 "lock\n\t" 564 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK; 565def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), 566 "lock\n\t" 567 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK; 568def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), 569 "lock\n\t" 570 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK; 571def LOCK_SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), 572 "lock\n\t" 573 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK; 574 575 576def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2), 577 "lock\n\t" 578 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK; 579def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2), 580 "lock\n\t" 581 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK; 582def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2), 583 "lock\n\t" 584 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK; 585def LOCK_SUB64mi32 : RIi32<0x81, MRM5m, (outs), 586 (ins i64mem:$dst, i64i32imm:$src2), 587 "lock\n\t" 588 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK; 589 590 591def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2), 592 "lock\n\t" 593 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK; 594def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2), 595 "lock\n\t" 596 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK; 597def LOCK_SUB64mi8 : RIi8<0x83, MRM5m, (outs), 598 (ins i64mem:$dst, i64i8imm :$src2), 599 "lock\n\t" 600 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK; 601 602def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), 603 "lock\n\t" 604 "inc{b}\t$dst", []>, LOCK; 605def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), 606 "lock\n\t" 607 "inc{w}\t$dst", []>, OpSize, LOCK; 608def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), 609 "lock\n\t" 610 "inc{l}\t$dst", []>, LOCK; 611def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), 612 "lock\n\t" 613 "inc{q}\t$dst", []>, LOCK; 614 615def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), 616 "lock\n\t" 617 "dec{b}\t$dst", []>, LOCK; 618def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), 619 "lock\n\t" 620 "dec{w}\t$dst", []>, OpSize, LOCK; 621def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), 622 "lock\n\t" 623 "dec{l}\t$dst", []>, LOCK; 624def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), 625 "lock\n\t" 626 "dec{q}\t$dst", []>, LOCK; 627} 628 629// Atomic compare and swap. 630let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX], 631 isCodeGenOnly = 1 in { 632def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr), 633 "lock\n\t" 634 "cmpxchg8b\t$ptr", 635 [(X86cas8 addr:$ptr)]>, TB, LOCK; 636} 637let Defs = [AL, EFLAGS], Uses = [AL], isCodeGenOnly = 1 in { 638def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap), 639 "lock\n\t" 640 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}", 641 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK; 642} 643 644let Defs = [AX, EFLAGS], Uses = [AX], isCodeGenOnly = 1 in { 645def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap), 646 "lock\n\t" 647 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}", 648 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK; 649} 650 651let Defs = [EAX, EFLAGS], Uses = [EAX], isCodeGenOnly = 1 in { 652def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap), 653 "lock\n\t" 654 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}", 655 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK; 656} 657 658let Defs = [RAX, EFLAGS], Uses = [RAX], isCodeGenOnly = 1 in { 659def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap), 660 "lock\n\t" 661 "cmpxchgq\t$swap,$ptr", 662 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK; 663} 664 665// Atomic exchange and add 666let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1 in { 667def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr), 668 "lock\n\t" 669 "xadd{b}\t{$val, $ptr|$ptr, $val}", 670 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>, 671 TB, LOCK; 672def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr), 673 "lock\n\t" 674 "xadd{w}\t{$val, $ptr|$ptr, $val}", 675 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>, 676 TB, OpSize, LOCK; 677def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr), 678 "lock\n\t" 679 "xadd{l}\t{$val, $ptr|$ptr, $val}", 680 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>, 681 TB, LOCK; 682def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins GR64:$val,i64mem:$ptr), 683 "lock\n\t" 684 "xadd\t$val, $ptr", 685 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>, 686 TB, LOCK; 687} 688 689//===----------------------------------------------------------------------===// 690// Conditional Move Pseudo Instructions. 691//===----------------------------------------------------------------------===// 692 693 694// CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after 695// instruction selection into a branch sequence. 696let Uses = [EFLAGS], usesCustomInserter = 1 in { 697 def CMOV_FR32 : I<0, Pseudo, 698 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond), 699 "#CMOV_FR32 PSEUDO!", 700 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond, 701 EFLAGS))]>; 702 def CMOV_FR64 : I<0, Pseudo, 703 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond), 704 "#CMOV_FR64 PSEUDO!", 705 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond, 706 EFLAGS))]>; 707 def CMOV_V4F32 : I<0, Pseudo, 708 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond), 709 "#CMOV_V4F32 PSEUDO!", 710 [(set VR128:$dst, 711 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond, 712 EFLAGS)))]>; 713 def CMOV_V2F64 : I<0, Pseudo, 714 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond), 715 "#CMOV_V2F64 PSEUDO!", 716 [(set VR128:$dst, 717 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond, 718 EFLAGS)))]>; 719 def CMOV_V2I64 : I<0, Pseudo, 720 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond), 721 "#CMOV_V2I64 PSEUDO!", 722 [(set VR128:$dst, 723 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond, 724 EFLAGS)))]>; 725} 726 727 728//===----------------------------------------------------------------------===// 729// DAG Pattern Matching Rules 730//===----------------------------------------------------------------------===// 731 732// ConstantPool GlobalAddress, ExternalSymbol, and JumpTable 733def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>; 734def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>; 735def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>; 736def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>; 737def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>; 738def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>; 739 740def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)), 741 (ADD32ri GR32:$src1, tconstpool:$src2)>; 742def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)), 743 (ADD32ri GR32:$src1, tjumptable:$src2)>; 744def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)), 745 (ADD32ri GR32:$src1, tglobaladdr:$src2)>; 746def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)), 747 (ADD32ri GR32:$src1, texternalsym:$src2)>; 748def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)), 749 (ADD32ri GR32:$src1, tblockaddress:$src2)>; 750 751def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst), 752 (MOV32mi addr:$dst, tglobaladdr:$src)>; 753def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst), 754 (MOV32mi addr:$dst, texternalsym:$src)>; 755def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst), 756 (MOV32mi addr:$dst, tblockaddress:$src)>; 757 758 759 760// ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small 761// code model mode, should use 'movabs'. FIXME: This is really a hack, the 762// 'movabs' predicate should handle this sort of thing. 763def : Pat<(i64 (X86Wrapper tconstpool :$dst)), 764 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>; 765def : Pat<(i64 (X86Wrapper tjumptable :$dst)), 766 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>; 767def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), 768 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>; 769def : Pat<(i64 (X86Wrapper texternalsym:$dst)), 770 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>; 771def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), 772 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>; 773 774// In static codegen with small code model, we can get the address of a label 775// into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of 776// the MOV64ri64i32 should accept these. 777def : Pat<(i64 (X86Wrapper tconstpool :$dst)), 778 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>; 779def : Pat<(i64 (X86Wrapper tjumptable :$dst)), 780 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>; 781def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), 782 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>; 783def : Pat<(i64 (X86Wrapper texternalsym:$dst)), 784 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>; 785def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), 786 (MOV64ri64i32 tblockaddress:$dst)>, Requires<[SmallCode]>; 787 788// In kernel code model, we can get the address of a label 789// into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of 790// the MOV64ri32 should accept these. 791def : Pat<(i64 (X86Wrapper tconstpool :$dst)), 792 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>; 793def : Pat<(i64 (X86Wrapper tjumptable :$dst)), 794 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>; 795def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), 796 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>; 797def : Pat<(i64 (X86Wrapper texternalsym:$dst)), 798 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>; 799def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), 800 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>; 801 802// If we have small model and -static mode, it is safe to store global addresses 803// directly as immediates. FIXME: This is really a hack, the 'imm' predicate 804// for MOV64mi32 should handle this sort of thing. 805def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst), 806 (MOV64mi32 addr:$dst, tconstpool:$src)>, 807 Requires<[NearData, IsStatic]>; 808def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst), 809 (MOV64mi32 addr:$dst, tjumptable:$src)>, 810 Requires<[NearData, IsStatic]>; 811def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst), 812 (MOV64mi32 addr:$dst, tglobaladdr:$src)>, 813 Requires<[NearData, IsStatic]>; 814def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst), 815 (MOV64mi32 addr:$dst, texternalsym:$src)>, 816 Requires<[NearData, IsStatic]>; 817def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst), 818 (MOV64mi32 addr:$dst, tblockaddress:$src)>, 819 Requires<[NearData, IsStatic]>; 820 821 822 823// Calls 824 825// tls has some funny stuff here... 826// This corresponds to movabs $foo@tpoff, %rax 827def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)), 828 (MOV64ri tglobaltlsaddr :$dst)>; 829// This corresponds to add $foo@tpoff, %rax 830def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)), 831 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>; 832// This corresponds to mov foo@tpoff(%rbx), %eax 833def : Pat<(load (i64 (X86Wrapper tglobaltlsaddr :$dst))), 834 (MOV64rm tglobaltlsaddr :$dst)>; 835 836 837// Direct PC relative function call for small code model. 32-bit displacement 838// sign extended to 64-bit. 839def : Pat<(X86call (i64 tglobaladdr:$dst)), 840 (CALL64pcrel32 tglobaladdr:$dst)>, Requires<[NotWin64]>; 841def : Pat<(X86call (i64 texternalsym:$dst)), 842 (CALL64pcrel32 texternalsym:$dst)>, Requires<[NotWin64]>; 843 844def : Pat<(X86call (i64 tglobaladdr:$dst)), 845 (WINCALL64pcrel32 tglobaladdr:$dst)>, Requires<[IsWin64]>; 846def : Pat<(X86call (i64 texternalsym:$dst)), 847 (WINCALL64pcrel32 texternalsym:$dst)>, Requires<[IsWin64]>; 848 849// tailcall stuff 850def : Pat<(X86tcret GR32_TC:$dst, imm:$off), 851 (TCRETURNri GR32_TC:$dst, imm:$off)>, 852 Requires<[In32BitMode]>; 853 854// FIXME: This is disabled for 32-bit PIC mode because the global base 855// register which is part of the address mode may be assigned a 856// callee-saved register. 857def : Pat<(X86tcret (load addr:$dst), imm:$off), 858 (TCRETURNmi addr:$dst, imm:$off)>, 859 Requires<[In32BitMode, IsNotPIC]>; 860 861def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off), 862 (TCRETURNdi texternalsym:$dst, imm:$off)>, 863 Requires<[In32BitMode]>; 864 865def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off), 866 (TCRETURNdi texternalsym:$dst, imm:$off)>, 867 Requires<[In32BitMode]>; 868 869def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), 870 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>, 871 Requires<[In64BitMode]>; 872 873def : Pat<(X86tcret (load addr:$dst), imm:$off), 874 (TCRETURNmi64 addr:$dst, imm:$off)>, 875 Requires<[In64BitMode]>; 876 877def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off), 878 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>, 879 Requires<[In64BitMode]>; 880 881def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off), 882 (TCRETURNdi64 texternalsym:$dst, imm:$off)>, 883 Requires<[In64BitMode]>; 884 885// Normal calls, with various flavors of addresses. 886def : Pat<(X86call (i32 tglobaladdr:$dst)), 887 (CALLpcrel32 tglobaladdr:$dst)>; 888def : Pat<(X86call (i32 texternalsym:$dst)), 889 (CALLpcrel32 texternalsym:$dst)>; 890def : Pat<(X86call (i32 imm:$dst)), 891 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>; 892 893// Comparisons. 894 895// TEST R,R is smaller than CMP R,0 896def : Pat<(X86cmp GR8:$src1, 0), 897 (TEST8rr GR8:$src1, GR8:$src1)>; 898def : Pat<(X86cmp GR16:$src1, 0), 899 (TEST16rr GR16:$src1, GR16:$src1)>; 900def : Pat<(X86cmp GR32:$src1, 0), 901 (TEST32rr GR32:$src1, GR32:$src1)>; 902def : Pat<(X86cmp GR64:$src1, 0), 903 (TEST64rr GR64:$src1, GR64:$src1)>; 904 905// Conditional moves with folded loads with operands swapped and conditions 906// inverted. 907multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32, 908 Instruction Inst64> { 909 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS), 910 (Inst16 GR16:$src2, addr:$src1)>; 911 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS), 912 (Inst32 GR32:$src2, addr:$src1)>; 913 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS), 914 (Inst64 GR64:$src2, addr:$src1)>; 915} 916 917defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>; 918defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>; 919defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>; 920defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>; 921defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>; 922defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>; 923defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>; 924defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>; 925defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>; 926defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>; 927defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>; 928defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>; 929defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>; 930defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>; 931defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>; 932defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>; 933 934// zextload bool -> zextload byte 935def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>; 936def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; 937def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; 938def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>; 939 940// extload bool -> extload byte 941// When extloading from 16-bit and smaller memory locations into 64-bit 942// registers, use zero-extending loads so that the entire 64-bit register is 943// defined, avoiding partial-register updates. 944 945def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>; 946def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; 947def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; 948def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>; 949def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>; 950def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>; 951 952def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>; 953def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>; 954def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>; 955// For other extloads, use subregs, since the high contents of the register are 956// defined after an extload. 957def : Pat<(extloadi64i32 addr:$src), 958 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), 959 sub_32bit)>; 960 961// anyext. Define these to do an explicit zero-extend to 962// avoid partial-register updates. 963def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>; 964def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>; 965 966// Except for i16 -> i32 since isel expect i16 ops to be promoted to i32. 967def : Pat<(i32 (anyext GR16:$src)), 968 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>; 969 970def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>; 971def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>; 972def : Pat<(i64 (anyext GR32:$src)), 973 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; 974 975 976// Any instruction that defines a 32-bit result leaves the high half of the 977// register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may 978// be copying from a truncate. And x86's cmov doesn't do anything if the 979// condition is false. But any other 32-bit operation will zero-extend 980// up to 64 bits. 981def def32 : PatLeaf<(i32 GR32:$src), [{ 982 return N->getOpcode() != ISD::TRUNCATE && 983 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG && 984 N->getOpcode() != ISD::CopyFromReg && 985 N->getOpcode() != X86ISD::CMOV; 986}]>; 987 988// In the case of a 32-bit def that is known to implicitly zero-extend, 989// we can use a SUBREG_TO_REG. 990def : Pat<(i64 (zext def32:$src)), 991 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; 992 993//===----------------------------------------------------------------------===// 994// Pattern match OR as ADD 995//===----------------------------------------------------------------------===// 996 997// If safe, we prefer to pattern match OR as ADD at isel time. ADD can be 998// 3-addressified into an LEA instruction to avoid copies. However, we also 999// want to finally emit these instructions as an or at the end of the code 1000// generator to make the generated code easier to read. To do this, we select 1001// into "disjoint bits" pseudo ops. 1002 1003// Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero. 1004def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{ 1005 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1006 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue()); 1007 1008 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits(); 1009 APInt Mask = APInt::getAllOnesValue(BitWidth); 1010 APInt KnownZero0, KnownOne0; 1011 CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0); 1012 APInt KnownZero1, KnownOne1; 1013 CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0); 1014 return (~KnownZero0 & ~KnownZero1) == 0; 1015}]>; 1016 1017 1018// (or x1, x2) -> (add x1, x2) if two operands are known not to share bits. 1019let AddedComplexity = 5 in { // Try this before the selecting to OR 1020 1021let isConvertibleToThreeAddress = 1, 1022 Constraints = "$src1 = $dst", Defs = [EFLAGS] in { 1023let isCommutable = 1 in { 1024def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 1025 "", // orw/addw REG, REG 1026 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>; 1027def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 1028 "", // orl/addl REG, REG 1029 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>; 1030def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 1031 "", // orq/addq REG, REG 1032 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>; 1033} // isCommutable 1034 1035// NOTE: These are order specific, we want the ri8 forms to be listed 1036// first so that they are slightly preferred to the ri forms. 1037 1038def ADD16ri8_DB : I<0, Pseudo, 1039 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), 1040 "", // orw/addw REG, imm8 1041 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>; 1042def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), 1043 "", // orw/addw REG, imm 1044 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>; 1045 1046def ADD32ri8_DB : I<0, Pseudo, 1047 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), 1048 "", // orl/addl REG, imm8 1049 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>; 1050def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 1051 "", // orl/addl REG, imm 1052 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>; 1053 1054 1055def ADD64ri8_DB : I<0, Pseudo, 1056 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), 1057 "", // orq/addq REG, imm8 1058 [(set GR64:$dst, (or_is_add GR64:$src1, 1059 i64immSExt8:$src2))]>; 1060def ADD64ri32_DB : I<0, Pseudo, 1061 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), 1062 "", // orq/addq REG, imm 1063 [(set GR64:$dst, (or_is_add GR64:$src1, 1064 i64immSExt32:$src2))]>; 1065} 1066} // AddedComplexity 1067 1068 1069//===----------------------------------------------------------------------===// 1070// Some peepholes 1071//===----------------------------------------------------------------------===// 1072 1073// Odd encoding trick: -128 fits into an 8-bit immediate field while 1074// +128 doesn't, so in this special case use a sub instead of an add. 1075def : Pat<(add GR16:$src1, 128), 1076 (SUB16ri8 GR16:$src1, -128)>; 1077def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst), 1078 (SUB16mi8 addr:$dst, -128)>; 1079 1080def : Pat<(add GR32:$src1, 128), 1081 (SUB32ri8 GR32:$src1, -128)>; 1082def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst), 1083 (SUB32mi8 addr:$dst, -128)>; 1084 1085def : Pat<(add GR64:$src1, 128), 1086 (SUB64ri8 GR64:$src1, -128)>; 1087def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst), 1088 (SUB64mi8 addr:$dst, -128)>; 1089 1090// The same trick applies for 32-bit immediate fields in 64-bit 1091// instructions. 1092def : Pat<(add GR64:$src1, 0x0000000080000000), 1093 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>; 1094def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst), 1095 (SUB64mi32 addr:$dst, 0xffffffff80000000)>; 1096 1097// To avoid needing to materialize an immediate in a register, use a 32-bit and 1098// with implicit zero-extension instead of a 64-bit and if the immediate has at 1099// least 32 bits of leading zeros. If in addition the last 32 bits can be 1100// represented with a sign extension of a 8 bit constant, use that. 1101 1102def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm), 1103 (SUBREG_TO_REG 1104 (i64 0), 1105 (AND32ri8 1106 (EXTRACT_SUBREG GR64:$src, sub_32bit), 1107 (i32 (GetLo8XForm imm:$imm))), 1108 sub_32bit)>; 1109 1110def : Pat<(and GR64:$src, i64immZExt32:$imm), 1111 (SUBREG_TO_REG 1112 (i64 0), 1113 (AND32ri 1114 (EXTRACT_SUBREG GR64:$src, sub_32bit), 1115 (i32 (GetLo32XForm imm:$imm))), 1116 sub_32bit)>; 1117 1118 1119// r & (2^16-1) ==> movz 1120def : Pat<(and GR32:$src1, 0xffff), 1121 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>; 1122// r & (2^8-1) ==> movz 1123def : Pat<(and GR32:$src1, 0xff), 1124 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1, 1125 GR32_ABCD)), 1126 sub_8bit))>, 1127 Requires<[In32BitMode]>; 1128// r & (2^8-1) ==> movz 1129def : Pat<(and GR16:$src1, 0xff), 1130 (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1, 1131 GR16_ABCD)), 1132 sub_8bit))>, 1133 Requires<[In32BitMode]>; 1134 1135// r & (2^32-1) ==> movz 1136def : Pat<(and GR64:$src, 0x00000000FFFFFFFF), 1137 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>; 1138// r & (2^16-1) ==> movz 1139def : Pat<(and GR64:$src, 0xffff), 1140 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit)))>; 1141// r & (2^8-1) ==> movz 1142def : Pat<(and GR64:$src, 0xff), 1143 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit)))>; 1144// r & (2^8-1) ==> movz 1145def : Pat<(and GR32:$src1, 0xff), 1146 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>, 1147 Requires<[In64BitMode]>; 1148// r & (2^8-1) ==> movz 1149def : Pat<(and GR16:$src1, 0xff), 1150 (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, sub_8bit)))>, 1151 Requires<[In64BitMode]>; 1152 1153 1154// sext_inreg patterns 1155def : Pat<(sext_inreg GR32:$src, i16), 1156 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>; 1157def : Pat<(sext_inreg GR32:$src, i8), 1158 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1159 GR32_ABCD)), 1160 sub_8bit))>, 1161 Requires<[In32BitMode]>; 1162def : Pat<(sext_inreg GR16:$src, i8), 1163 (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, 1164 GR16_ABCD)), 1165 sub_8bit))>, 1166 Requires<[In32BitMode]>; 1167 1168def : Pat<(sext_inreg GR64:$src, i32), 1169 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>; 1170def : Pat<(sext_inreg GR64:$src, i16), 1171 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>; 1172def : Pat<(sext_inreg GR64:$src, i8), 1173 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>; 1174def : Pat<(sext_inreg GR32:$src, i8), 1175 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>, 1176 Requires<[In64BitMode]>; 1177def : Pat<(sext_inreg GR16:$src, i8), 1178 (MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, sub_8bit)))>, 1179 Requires<[In64BitMode]>; 1180 1181 1182// trunc patterns 1183def : Pat<(i16 (trunc GR32:$src)), 1184 (EXTRACT_SUBREG GR32:$src, sub_16bit)>; 1185def : Pat<(i8 (trunc GR32:$src)), 1186 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1187 sub_8bit)>, 1188 Requires<[In32BitMode]>; 1189def : Pat<(i8 (trunc GR16:$src)), 1190 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1191 sub_8bit)>, 1192 Requires<[In32BitMode]>; 1193def : Pat<(i32 (trunc GR64:$src)), 1194 (EXTRACT_SUBREG GR64:$src, sub_32bit)>; 1195def : Pat<(i16 (trunc GR64:$src)), 1196 (EXTRACT_SUBREG GR64:$src, sub_16bit)>; 1197def : Pat<(i8 (trunc GR64:$src)), 1198 (EXTRACT_SUBREG GR64:$src, sub_8bit)>; 1199def : Pat<(i8 (trunc GR32:$src)), 1200 (EXTRACT_SUBREG GR32:$src, sub_8bit)>, 1201 Requires<[In64BitMode]>; 1202def : Pat<(i8 (trunc GR16:$src)), 1203 (EXTRACT_SUBREG GR16:$src, sub_8bit)>, 1204 Requires<[In64BitMode]>; 1205 1206// h-register tricks 1207def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))), 1208 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1209 sub_8bit_hi)>, 1210 Requires<[In32BitMode]>; 1211def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))), 1212 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1213 sub_8bit_hi)>, 1214 Requires<[In32BitMode]>; 1215def : Pat<(srl GR16:$src, (i8 8)), 1216 (EXTRACT_SUBREG 1217 (MOVZX32rr8 1218 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1219 sub_8bit_hi)), 1220 sub_16bit)>, 1221 Requires<[In32BitMode]>; 1222def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), 1223 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, 1224 GR16_ABCD)), 1225 sub_8bit_hi))>, 1226 Requires<[In32BitMode]>; 1227def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), 1228 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, 1229 GR16_ABCD)), 1230 sub_8bit_hi))>, 1231 Requires<[In32BitMode]>; 1232def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), 1233 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1234 GR32_ABCD)), 1235 sub_8bit_hi))>, 1236 Requires<[In32BitMode]>; 1237def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)), 1238 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1239 GR32_ABCD)), 1240 sub_8bit_hi))>, 1241 Requires<[In32BitMode]>; 1242 1243// h-register tricks. 1244// For now, be conservative on x86-64 and use an h-register extract only if the 1245// value is immediately zero-extended or stored, which are somewhat common 1246// cases. This uses a bunch of code to prevent a register requiring a REX prefix 1247// from being allocated in the same instruction as the h register, as there's 1248// currently no way to describe this requirement to the register allocator. 1249 1250// h-register extract and zero-extend. 1251def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)), 1252 (SUBREG_TO_REG 1253 (i64 0), 1254 (MOVZX32_NOREXrr8 1255 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)), 1256 sub_8bit_hi)), 1257 sub_32bit)>; 1258def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), 1259 (MOVZX32_NOREXrr8 1260 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1261 sub_8bit_hi))>, 1262 Requires<[In64BitMode]>; 1263def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)), 1264 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1265 GR32_ABCD)), 1266 sub_8bit_hi))>, 1267 Requires<[In64BitMode]>; 1268def : Pat<(srl GR16:$src, (i8 8)), 1269 (EXTRACT_SUBREG 1270 (MOVZX32_NOREXrr8 1271 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1272 sub_8bit_hi)), 1273 sub_16bit)>, 1274 Requires<[In64BitMode]>; 1275def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), 1276 (MOVZX32_NOREXrr8 1277 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1278 sub_8bit_hi))>, 1279 Requires<[In64BitMode]>; 1280def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), 1281 (MOVZX32_NOREXrr8 1282 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1283 sub_8bit_hi))>, 1284 Requires<[In64BitMode]>; 1285def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))), 1286 (SUBREG_TO_REG 1287 (i64 0), 1288 (MOVZX32_NOREXrr8 1289 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1290 sub_8bit_hi)), 1291 sub_32bit)>; 1292def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))), 1293 (SUBREG_TO_REG 1294 (i64 0), 1295 (MOVZX32_NOREXrr8 1296 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1297 sub_8bit_hi)), 1298 sub_32bit)>; 1299 1300// h-register extract and store. 1301def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst), 1302 (MOV8mr_NOREX 1303 addr:$dst, 1304 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)), 1305 sub_8bit_hi))>; 1306def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst), 1307 (MOV8mr_NOREX 1308 addr:$dst, 1309 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1310 sub_8bit_hi))>, 1311 Requires<[In64BitMode]>; 1312def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst), 1313 (MOV8mr_NOREX 1314 addr:$dst, 1315 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1316 sub_8bit_hi))>, 1317 Requires<[In64BitMode]>; 1318 1319 1320// (shl x, 1) ==> (add x, x) 1321def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>; 1322def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>; 1323def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>; 1324def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>; 1325 1326// (shl x (and y, 31)) ==> (shl x, y) 1327def : Pat<(shl GR8:$src1, (and CL, 31)), 1328 (SHL8rCL GR8:$src1)>; 1329def : Pat<(shl GR16:$src1, (and CL, 31)), 1330 (SHL16rCL GR16:$src1)>; 1331def : Pat<(shl GR32:$src1, (and CL, 31)), 1332 (SHL32rCL GR32:$src1)>; 1333def : Pat<(store (shl (loadi8 addr:$dst), (and CL, 31)), addr:$dst), 1334 (SHL8mCL addr:$dst)>; 1335def : Pat<(store (shl (loadi16 addr:$dst), (and CL, 31)), addr:$dst), 1336 (SHL16mCL addr:$dst)>; 1337def : Pat<(store (shl (loadi32 addr:$dst), (and CL, 31)), addr:$dst), 1338 (SHL32mCL addr:$dst)>; 1339 1340def : Pat<(srl GR8:$src1, (and CL, 31)), 1341 (SHR8rCL GR8:$src1)>; 1342def : Pat<(srl GR16:$src1, (and CL, 31)), 1343 (SHR16rCL GR16:$src1)>; 1344def : Pat<(srl GR32:$src1, (and CL, 31)), 1345 (SHR32rCL GR32:$src1)>; 1346def : Pat<(store (srl (loadi8 addr:$dst), (and CL, 31)), addr:$dst), 1347 (SHR8mCL addr:$dst)>; 1348def : Pat<(store (srl (loadi16 addr:$dst), (and CL, 31)), addr:$dst), 1349 (SHR16mCL addr:$dst)>; 1350def : Pat<(store (srl (loadi32 addr:$dst), (and CL, 31)), addr:$dst), 1351 (SHR32mCL addr:$dst)>; 1352 1353def : Pat<(sra GR8:$src1, (and CL, 31)), 1354 (SAR8rCL GR8:$src1)>; 1355def : Pat<(sra GR16:$src1, (and CL, 31)), 1356 (SAR16rCL GR16:$src1)>; 1357def : Pat<(sra GR32:$src1, (and CL, 31)), 1358 (SAR32rCL GR32:$src1)>; 1359def : Pat<(store (sra (loadi8 addr:$dst), (and CL, 31)), addr:$dst), 1360 (SAR8mCL addr:$dst)>; 1361def : Pat<(store (sra (loadi16 addr:$dst), (and CL, 31)), addr:$dst), 1362 (SAR16mCL addr:$dst)>; 1363def : Pat<(store (sra (loadi32 addr:$dst), (and CL, 31)), addr:$dst), 1364 (SAR32mCL addr:$dst)>; 1365 1366// (shl x (and y, 63)) ==> (shl x, y) 1367def : Pat<(shl GR64:$src1, (and CL, 63)), 1368 (SHL64rCL GR64:$src1)>; 1369def : Pat<(store (shl (loadi64 addr:$dst), (and CL, 63)), addr:$dst), 1370 (SHL64mCL addr:$dst)>; 1371 1372def : Pat<(srl GR64:$src1, (and CL, 63)), 1373 (SHR64rCL GR64:$src1)>; 1374def : Pat<(store (srl (loadi64 addr:$dst), (and CL, 63)), addr:$dst), 1375 (SHR64mCL addr:$dst)>; 1376 1377def : Pat<(sra GR64:$src1, (and CL, 63)), 1378 (SAR64rCL GR64:$src1)>; 1379def : Pat<(store (sra (loadi64 addr:$dst), (and CL, 63)), addr:$dst), 1380 (SAR64mCL addr:$dst)>; 1381 1382 1383// (anyext (setcc_carry)) -> (setcc_carry) 1384def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 1385 (SETB_C16r)>; 1386def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 1387 (SETB_C32r)>; 1388def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))), 1389 (SETB_C32r)>; 1390 1391 1392 1393 1394//===----------------------------------------------------------------------===// 1395// EFLAGS-defining Patterns 1396//===----------------------------------------------------------------------===// 1397 1398// add reg, reg 1399def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>; 1400def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>; 1401def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>; 1402 1403// add reg, mem 1404def : Pat<(add GR8:$src1, (loadi8 addr:$src2)), 1405 (ADD8rm GR8:$src1, addr:$src2)>; 1406def : Pat<(add GR16:$src1, (loadi16 addr:$src2)), 1407 (ADD16rm GR16:$src1, addr:$src2)>; 1408def : Pat<(add GR32:$src1, (loadi32 addr:$src2)), 1409 (ADD32rm GR32:$src1, addr:$src2)>; 1410 1411// add reg, imm 1412def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>; 1413def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>; 1414def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>; 1415def : Pat<(add GR16:$src1, i16immSExt8:$src2), 1416 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>; 1417def : Pat<(add GR32:$src1, i32immSExt8:$src2), 1418 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>; 1419 1420// sub reg, reg 1421def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>; 1422def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>; 1423def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>; 1424 1425// sub reg, mem 1426def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)), 1427 (SUB8rm GR8:$src1, addr:$src2)>; 1428def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)), 1429 (SUB16rm GR16:$src1, addr:$src2)>; 1430def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)), 1431 (SUB32rm GR32:$src1, addr:$src2)>; 1432 1433// sub reg, imm 1434def : Pat<(sub GR8:$src1, imm:$src2), 1435 (SUB8ri GR8:$src1, imm:$src2)>; 1436def : Pat<(sub GR16:$src1, imm:$src2), 1437 (SUB16ri GR16:$src1, imm:$src2)>; 1438def : Pat<(sub GR32:$src1, imm:$src2), 1439 (SUB32ri GR32:$src1, imm:$src2)>; 1440def : Pat<(sub GR16:$src1, i16immSExt8:$src2), 1441 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>; 1442def : Pat<(sub GR32:$src1, i32immSExt8:$src2), 1443 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>; 1444 1445// mul reg, reg 1446def : Pat<(mul GR16:$src1, GR16:$src2), 1447 (IMUL16rr GR16:$src1, GR16:$src2)>; 1448def : Pat<(mul GR32:$src1, GR32:$src2), 1449 (IMUL32rr GR32:$src1, GR32:$src2)>; 1450 1451// mul reg, mem 1452def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)), 1453 (IMUL16rm GR16:$src1, addr:$src2)>; 1454def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)), 1455 (IMUL32rm GR32:$src1, addr:$src2)>; 1456 1457// mul reg, imm 1458def : Pat<(mul GR16:$src1, imm:$src2), 1459 (IMUL16rri GR16:$src1, imm:$src2)>; 1460def : Pat<(mul GR32:$src1, imm:$src2), 1461 (IMUL32rri GR32:$src1, imm:$src2)>; 1462def : Pat<(mul GR16:$src1, i16immSExt8:$src2), 1463 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>; 1464def : Pat<(mul GR32:$src1, i32immSExt8:$src2), 1465 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>; 1466 1467// reg = mul mem, imm 1468def : Pat<(mul (loadi16 addr:$src1), imm:$src2), 1469 (IMUL16rmi addr:$src1, imm:$src2)>; 1470def : Pat<(mul (loadi32 addr:$src1), imm:$src2), 1471 (IMUL32rmi addr:$src1, imm:$src2)>; 1472def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2), 1473 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>; 1474def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2), 1475 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>; 1476 1477// Optimize multiply by 2 with EFLAGS result. 1478let AddedComplexity = 2 in { 1479def : Pat<(X86smul_flag GR16:$src1, 2), (ADD16rr GR16:$src1, GR16:$src1)>; 1480def : Pat<(X86smul_flag GR32:$src1, 2), (ADD32rr GR32:$src1, GR32:$src1)>; 1481} 1482 1483// Patterns for nodes that do not produce flags, for instructions that do. 1484 1485// addition 1486def : Pat<(add GR64:$src1, GR64:$src2), 1487 (ADD64rr GR64:$src1, GR64:$src2)>; 1488def : Pat<(add GR64:$src1, i64immSExt8:$src2), 1489 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>; 1490def : Pat<(add GR64:$src1, i64immSExt32:$src2), 1491 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>; 1492def : Pat<(add GR64:$src1, (loadi64 addr:$src2)), 1493 (ADD64rm GR64:$src1, addr:$src2)>; 1494 1495// subtraction 1496def : Pat<(sub GR64:$src1, GR64:$src2), 1497 (SUB64rr GR64:$src1, GR64:$src2)>; 1498def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)), 1499 (SUB64rm GR64:$src1, addr:$src2)>; 1500def : Pat<(sub GR64:$src1, i64immSExt8:$src2), 1501 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>; 1502def : Pat<(sub GR64:$src1, i64immSExt32:$src2), 1503 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>; 1504 1505// Multiply 1506def : Pat<(mul GR64:$src1, GR64:$src2), 1507 (IMUL64rr GR64:$src1, GR64:$src2)>; 1508def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)), 1509 (IMUL64rm GR64:$src1, addr:$src2)>; 1510def : Pat<(mul GR64:$src1, i64immSExt8:$src2), 1511 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>; 1512def : Pat<(mul GR64:$src1, i64immSExt32:$src2), 1513 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>; 1514def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2), 1515 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>; 1516def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2), 1517 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>; 1518 1519// Increment reg. 1520def : Pat<(add GR8 :$src, 1), (INC8r GR8 :$src)>; 1521def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>, Requires<[In32BitMode]>; 1522def : Pat<(add GR16:$src, 1), (INC64_16r GR16:$src)>, Requires<[In64BitMode]>; 1523def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>, Requires<[In32BitMode]>; 1524def : Pat<(add GR32:$src, 1), (INC64_32r GR32:$src)>, Requires<[In64BitMode]>; 1525def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>; 1526 1527// Decrement reg. 1528def : Pat<(add GR8 :$src, -1), (DEC8r GR8 :$src)>; 1529def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>, Requires<[In32BitMode]>; 1530def : Pat<(add GR16:$src, -1), (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>; 1531def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>, Requires<[In32BitMode]>; 1532def : Pat<(add GR32:$src, -1), (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>; 1533def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>; 1534 1535// or reg/reg. 1536def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>; 1537def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>; 1538def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>; 1539def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>; 1540 1541// or reg/mem 1542def : Pat<(or GR8:$src1, (loadi8 addr:$src2)), 1543 (OR8rm GR8:$src1, addr:$src2)>; 1544def : Pat<(or GR16:$src1, (loadi16 addr:$src2)), 1545 (OR16rm GR16:$src1, addr:$src2)>; 1546def : Pat<(or GR32:$src1, (loadi32 addr:$src2)), 1547 (OR32rm GR32:$src1, addr:$src2)>; 1548def : Pat<(or GR64:$src1, (loadi64 addr:$src2)), 1549 (OR64rm GR64:$src1, addr:$src2)>; 1550 1551// or reg/imm 1552def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>; 1553def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>; 1554def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>; 1555def : Pat<(or GR16:$src1, i16immSExt8:$src2), 1556 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>; 1557def : Pat<(or GR32:$src1, i32immSExt8:$src2), 1558 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>; 1559def : Pat<(or GR64:$src1, i64immSExt8:$src2), 1560 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>; 1561def : Pat<(or GR64:$src1, i64immSExt32:$src2), 1562 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>; 1563 1564// xor reg/reg 1565def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>; 1566def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>; 1567def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>; 1568def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>; 1569 1570// xor reg/mem 1571def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)), 1572 (XOR8rm GR8:$src1, addr:$src2)>; 1573def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)), 1574 (XOR16rm GR16:$src1, addr:$src2)>; 1575def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)), 1576 (XOR32rm GR32:$src1, addr:$src2)>; 1577def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)), 1578 (XOR64rm GR64:$src1, addr:$src2)>; 1579 1580// xor reg/imm 1581def : Pat<(xor GR8:$src1, imm:$src2), 1582 (XOR8ri GR8:$src1, imm:$src2)>; 1583def : Pat<(xor GR16:$src1, imm:$src2), 1584 (XOR16ri GR16:$src1, imm:$src2)>; 1585def : Pat<(xor GR32:$src1, imm:$src2), 1586 (XOR32ri GR32:$src1, imm:$src2)>; 1587def : Pat<(xor GR16:$src1, i16immSExt8:$src2), 1588 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>; 1589def : Pat<(xor GR32:$src1, i32immSExt8:$src2), 1590 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>; 1591def : Pat<(xor GR64:$src1, i64immSExt8:$src2), 1592 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>; 1593def : Pat<(xor GR64:$src1, i64immSExt32:$src2), 1594 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>; 1595 1596// and reg/reg 1597def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>; 1598def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>; 1599def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>; 1600def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>; 1601 1602// and reg/mem 1603def : Pat<(and GR8:$src1, (loadi8 addr:$src2)), 1604 (AND8rm GR8:$src1, addr:$src2)>; 1605def : Pat<(and GR16:$src1, (loadi16 addr:$src2)), 1606 (AND16rm GR16:$src1, addr:$src2)>; 1607def : Pat<(and GR32:$src1, (loadi32 addr:$src2)), 1608 (AND32rm GR32:$src1, addr:$src2)>; 1609def : Pat<(and GR64:$src1, (loadi64 addr:$src2)), 1610 (AND64rm GR64:$src1, addr:$src2)>; 1611 1612// and reg/imm 1613def : Pat<(and GR8:$src1, imm:$src2), 1614 (AND8ri GR8:$src1, imm:$src2)>; 1615def : Pat<(and GR16:$src1, imm:$src2), 1616 (AND16ri GR16:$src1, imm:$src2)>; 1617def : Pat<(and GR32:$src1, imm:$src2), 1618 (AND32ri GR32:$src1, imm:$src2)>; 1619def : Pat<(and GR16:$src1, i16immSExt8:$src2), 1620 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>; 1621def : Pat<(and GR32:$src1, i32immSExt8:$src2), 1622 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>; 1623def : Pat<(and GR64:$src1, i64immSExt8:$src2), 1624 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>; 1625def : Pat<(and GR64:$src1, i64immSExt32:$src2), 1626 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>; 1627